1 /* 2 * sun6i specific clock code 3 * 4 * (C) Copyright 2007-2012 5 * Allwinner Technology Co., Ltd. <www.allwinnertech.com> 6 * Tom Cubie <tangliang@allwinnertech.com> 7 * 8 * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net> 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 #include <common.h> 14 #include <asm/io.h> 15 #include <asm/arch/clock.h> 16 #include <asm/arch/prcm.h> 17 #include <asm/arch/sys_proto.h> 18 19 #ifdef CONFIG_SPL_BUILD 20 void clock_init_safe(void) 21 { 22 struct sunxi_ccm_reg * const ccm = 23 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 24 25 #if !defined(CONFIG_MACH_SUNXI_H3_H5) && !defined(CONFIG_MACH_SUN50I) 26 struct sunxi_prcm_reg * const prcm = 27 (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE; 28 29 /* Set PLL ldo voltage without this PLL6 does not work properly */ 30 clrsetbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK, 31 PRCM_PLL_CTRL_LDO_KEY); 32 clrsetbits_le32(&prcm->pll_ctrl1, ~PRCM_PLL_CTRL_LDO_KEY_MASK, 33 PRCM_PLL_CTRL_LDO_DIGITAL_EN | PRCM_PLL_CTRL_LDO_ANALOG_EN | 34 PRCM_PLL_CTRL_EXT_OSC_EN | PRCM_PLL_CTRL_LDO_OUT_L(1140)); 35 clrbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK); 36 #endif 37 38 #if defined(CONFIG_MACH_SUN8I_R40) || defined(CONFIG_MACH_SUN50I) 39 /* Set PLL lock enable bits and switch to old lock mode */ 40 writel(GENMASK(12, 0), &ccm->pll_lock_ctrl); 41 #endif 42 43 clock_set_pll1(408000000); 44 45 writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg); 46 while (!(readl(&ccm->pll6_cfg) & CCM_PLL6_CTRL_LOCK)) 47 ; 48 49 writel(AHB1_ABP1_DIV_DEFAULT, &ccm->ahb1_apb1_div); 50 51 writel(MBUS_CLK_DEFAULT, &ccm->mbus0_clk_cfg); 52 if (IS_ENABLED(CONFIG_MACH_SUN6I)) 53 writel(MBUS_CLK_DEFAULT, &ccm->mbus1_clk_cfg); 54 55 #if defined(CONFIG_MACH_SUN8I_R40) && defined(CONFIG_SUNXI_AHCI) 56 setbits_le32(&ccm->sata_pll_cfg, CCM_SATA_PLL_DEFAULT); 57 setbits_le32(&ccm->ahb_reset0_cfg, 0x1 << AHB_GATE_OFFSET_SATA); 58 setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_SATA); 59 setbits_le32(&ccm->sata_clk_cfg, CCM_SATA_CTRL_ENABLE); 60 #endif 61 } 62 #endif 63 64 void clock_init_sec(void) 65 { 66 #ifdef CONFIG_MACH_SUNXI_H3_H5 67 struct sunxi_ccm_reg * const ccm = 68 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 69 struct sunxi_prcm_reg * const prcm = 70 (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE; 71 72 setbits_le32(&ccm->ccu_sec_switch, 73 CCM_SEC_SWITCH_MBUS_NONSEC | 74 CCM_SEC_SWITCH_BUS_NONSEC | 75 CCM_SEC_SWITCH_PLL_NONSEC); 76 setbits_le32(&prcm->prcm_sec_switch, 77 PRCM_SEC_SWITCH_APB0_CLK_NONSEC | 78 PRCM_SEC_SWITCH_PLL_CFG_NONSEC | 79 PRCM_SEC_SWITCH_PWR_GATE_NONSEC); 80 #endif 81 } 82 83 void clock_init_uart(void) 84 { 85 #if CONFIG_CONS_INDEX < 5 86 struct sunxi_ccm_reg *const ccm = 87 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 88 89 /* uart clock source is apb2 */ 90 writel(APB2_CLK_SRC_OSC24M| 91 APB2_CLK_RATE_N_1| 92 APB2_CLK_RATE_M(1), 93 &ccm->apb2_div); 94 95 /* open the clock for uart */ 96 setbits_le32(&ccm->apb2_gate, 97 CLK_GATE_OPEN << (APB2_GATE_UART_SHIFT + 98 CONFIG_CONS_INDEX - 1)); 99 100 /* deassert uart reset */ 101 setbits_le32(&ccm->apb2_reset_cfg, 102 1 << (APB2_RESET_UART_SHIFT + 103 CONFIG_CONS_INDEX - 1)); 104 #else 105 /* enable R_PIO and R_UART clocks, and de-assert resets */ 106 prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_UART); 107 #endif 108 } 109 110 #ifdef CONFIG_SPL_BUILD 111 void clock_set_pll1(unsigned int clk) 112 { 113 struct sunxi_ccm_reg * const ccm = 114 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 115 const int p = 0; 116 int k = 1; 117 int m = 1; 118 119 if (clk > 1152000000) { 120 k = 2; 121 } else if (clk > 768000000) { 122 k = 3; 123 m = 2; 124 } 125 126 /* Switch to 24MHz clock while changing PLL1 */ 127 writel(AXI_DIV_3 << AXI_DIV_SHIFT | 128 ATB_DIV_2 << ATB_DIV_SHIFT | 129 CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT, 130 &ccm->cpu_axi_cfg); 131 132 /* 133 * sun6i: PLL1 rate = ((24000000 * n * k) >> 0) / m (p is ignored) 134 * sun8i: PLL1 rate = ((24000000 * n * k) >> p) / m 135 */ 136 writel(CCM_PLL1_CTRL_EN | CCM_PLL1_CTRL_P(p) | 137 CCM_PLL1_CTRL_N(clk / (24000000 * k / m)) | 138 CCM_PLL1_CTRL_K(k) | CCM_PLL1_CTRL_M(m), &ccm->pll1_cfg); 139 sdelay(200); 140 141 /* Switch CPU to PLL1 */ 142 writel(AXI_DIV_3 << AXI_DIV_SHIFT | 143 ATB_DIV_2 << ATB_DIV_SHIFT | 144 CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT, 145 &ccm->cpu_axi_cfg); 146 } 147 #endif 148 149 void clock_set_pll3(unsigned int clk) 150 { 151 struct sunxi_ccm_reg * const ccm = 152 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 153 const int m = 8; /* 3 MHz steps just like sun4i, sun5i and sun7i */ 154 155 if (clk == 0) { 156 clrbits_le32(&ccm->pll3_cfg, CCM_PLL3_CTRL_EN); 157 return; 158 } 159 160 /* PLL3 rate = 24000000 * n / m */ 161 writel(CCM_PLL3_CTRL_EN | CCM_PLL3_CTRL_INTEGER_MODE | 162 CCM_PLL3_CTRL_N(clk / (24000000 / m)) | CCM_PLL3_CTRL_M(m), 163 &ccm->pll3_cfg); 164 } 165 166 #ifdef CONFIG_SUNXI_DE2 167 void clock_set_pll3_factors(int m, int n) 168 { 169 struct sunxi_ccm_reg * const ccm = 170 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 171 172 /* PLL3 rate = 24000000 * n / m */ 173 writel(CCM_PLL3_CTRL_EN | CCM_PLL3_CTRL_INTEGER_MODE | 174 CCM_PLL3_CTRL_N(n) | CCM_PLL3_CTRL_M(m), 175 &ccm->pll3_cfg); 176 177 while (!(readl(&ccm->pll3_cfg) & CCM_PLL3_CTRL_LOCK)) 178 ; 179 } 180 #endif 181 182 void clock_set_pll5(unsigned int clk, bool sigma_delta_enable) 183 { 184 struct sunxi_ccm_reg * const ccm = 185 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 186 const int max_n = 32; 187 int k = 1, m = 2; 188 189 #ifdef CONFIG_MACH_SUNXI_H3_H5 190 clrsetbits_le32(&ccm->pll5_tuning_cfg, CCM_PLL5_TUN_LOCK_TIME_MASK | 191 CCM_PLL5_TUN_INIT_FREQ_MASK, 192 CCM_PLL5_TUN_LOCK_TIME(2) | CCM_PLL5_TUN_INIT_FREQ(16)); 193 #endif 194 195 if (sigma_delta_enable) 196 writel(CCM_PLL5_PATTERN, &ccm->pll5_pattern_cfg); 197 198 /* PLL5 rate = 24000000 * n * k / m */ 199 if (clk > 24000000 * k * max_n / m) { 200 m = 1; 201 if (clk > 24000000 * k * max_n / m) 202 k = 2; 203 } 204 writel(CCM_PLL5_CTRL_EN | 205 (sigma_delta_enable ? CCM_PLL5_CTRL_SIGMA_DELTA_EN : 0) | 206 CCM_PLL5_CTRL_UPD | 207 CCM_PLL5_CTRL_N(clk / (24000000 * k / m)) | 208 CCM_PLL5_CTRL_K(k) | CCM_PLL5_CTRL_M(m), &ccm->pll5_cfg); 209 210 udelay(5500); 211 } 212 213 #ifdef CONFIG_MACH_SUN6I 214 void clock_set_mipi_pll(unsigned int clk) 215 { 216 struct sunxi_ccm_reg * const ccm = 217 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 218 unsigned int k, m, n, value, diff; 219 unsigned best_k = 0, best_m = 0, best_n = 0, best_diff = 0xffffffff; 220 unsigned int src = clock_get_pll3(); 221 222 /* All calculations are in KHz to avoid overflows */ 223 clk /= 1000; 224 src /= 1000; 225 226 /* Pick the closest lower clock */ 227 for (k = 1; k <= 4; k++) { 228 for (m = 1; m <= 16; m++) { 229 for (n = 1; n <= 16; n++) { 230 value = src * n * k / m; 231 if (value > clk) 232 continue; 233 234 diff = clk - value; 235 if (diff < best_diff) { 236 best_diff = diff; 237 best_k = k; 238 best_m = m; 239 best_n = n; 240 } 241 if (diff == 0) 242 goto done; 243 } 244 } 245 } 246 247 done: 248 writel(CCM_MIPI_PLL_CTRL_EN | CCM_MIPI_PLL_CTRL_LDO_EN | 249 CCM_MIPI_PLL_CTRL_N(best_n) | CCM_MIPI_PLL_CTRL_K(best_k) | 250 CCM_MIPI_PLL_CTRL_M(best_m), &ccm->mipi_pll_cfg); 251 } 252 #endif 253 254 #ifdef CONFIG_SUNXI_DE2 255 void clock_set_pll10(unsigned int clk) 256 { 257 struct sunxi_ccm_reg * const ccm = 258 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 259 const int m = 2; /* 12 MHz steps */ 260 261 if (clk == 0) { 262 clrbits_le32(&ccm->pll10_cfg, CCM_PLL10_CTRL_EN); 263 return; 264 } 265 266 /* PLL10 rate = 24000000 * n / m */ 267 writel(CCM_PLL10_CTRL_EN | CCM_PLL10_CTRL_INTEGER_MODE | 268 CCM_PLL10_CTRL_N(clk / (24000000 / m)) | CCM_PLL10_CTRL_M(m), 269 &ccm->pll10_cfg); 270 271 while (!(readl(&ccm->pll10_cfg) & CCM_PLL10_CTRL_LOCK)) 272 ; 273 } 274 #endif 275 276 #if defined(CONFIG_MACH_SUN8I_A33) || \ 277 defined(CONFIG_MACH_SUN8I_R40) || \ 278 defined(CONFIG_MACH_SUN50I) 279 void clock_set_pll11(unsigned int clk, bool sigma_delta_enable) 280 { 281 struct sunxi_ccm_reg * const ccm = 282 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 283 284 if (sigma_delta_enable) 285 writel(CCM_PLL11_PATTERN, &ccm->pll11_pattern_cfg0); 286 287 writel(CCM_PLL11_CTRL_EN | CCM_PLL11_CTRL_UPD | 288 (sigma_delta_enable ? CCM_PLL11_CTRL_SIGMA_DELTA_EN : 0) | 289 CCM_PLL11_CTRL_N(clk / 24000000), &ccm->pll11_cfg); 290 291 while (readl(&ccm->pll11_cfg) & CCM_PLL11_CTRL_UPD) 292 ; 293 } 294 #endif 295 296 unsigned int clock_get_pll3(void) 297 { 298 struct sunxi_ccm_reg *const ccm = 299 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 300 uint32_t rval = readl(&ccm->pll3_cfg); 301 int n = ((rval & CCM_PLL3_CTRL_N_MASK) >> CCM_PLL3_CTRL_N_SHIFT) + 1; 302 int m = ((rval & CCM_PLL3_CTRL_M_MASK) >> CCM_PLL3_CTRL_M_SHIFT) + 1; 303 304 /* Multiply by 1000 after dividing by m to avoid integer overflows */ 305 return (24000 * n / m) * 1000; 306 } 307 308 unsigned int clock_get_pll6(void) 309 { 310 struct sunxi_ccm_reg *const ccm = 311 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 312 uint32_t rval = readl(&ccm->pll6_cfg); 313 int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT) + 1; 314 int k = ((rval & CCM_PLL6_CTRL_K_MASK) >> CCM_PLL6_CTRL_K_SHIFT) + 1; 315 return 24000000 * n * k / 2; 316 } 317 318 unsigned int clock_get_mipi_pll(void) 319 { 320 struct sunxi_ccm_reg *const ccm = 321 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 322 uint32_t rval = readl(&ccm->mipi_pll_cfg); 323 unsigned int n = ((rval & CCM_MIPI_PLL_CTRL_N_MASK) >> CCM_MIPI_PLL_CTRL_N_SHIFT) + 1; 324 unsigned int k = ((rval & CCM_MIPI_PLL_CTRL_K_MASK) >> CCM_MIPI_PLL_CTRL_K_SHIFT) + 1; 325 unsigned int m = ((rval & CCM_MIPI_PLL_CTRL_M_MASK) >> CCM_MIPI_PLL_CTRL_M_SHIFT) + 1; 326 unsigned int src = clock_get_pll3(); 327 328 /* Multiply by 1000 after dividing by m to avoid integer overflows */ 329 return ((src / 1000) * n * k / m) * 1000; 330 } 331 332 void clock_set_de_mod_clock(u32 *clk_cfg, unsigned int hz) 333 { 334 int pll = clock_get_pll6() * 2; 335 int div = 1; 336 337 while ((pll / div) > hz) 338 div++; 339 340 writel(CCM_DE_CTRL_GATE | CCM_DE_CTRL_PLL6_2X | CCM_DE_CTRL_M(div), 341 clk_cfg); 342 } 343