1 /* 2 * sun6i specific clock code 3 * 4 * (C) Copyright 2007-2012 5 * Allwinner Technology Co., Ltd. <www.allwinnertech.com> 6 * Tom Cubie <tangliang@allwinnertech.com> 7 * 8 * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net> 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 #include <common.h> 14 #include <asm/io.h> 15 #include <asm/arch/clock.h> 16 #include <asm/arch/prcm.h> 17 #include <asm/arch/sys_proto.h> 18 19 #ifdef CONFIG_SPL_BUILD 20 void clock_init_safe(void) 21 { 22 struct sunxi_ccm_reg * const ccm = 23 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 24 25 #if !defined(CONFIG_MACH_SUNXI_H3_H5) && !defined(CONFIG_MACH_SUN50I) 26 struct sunxi_prcm_reg * const prcm = 27 (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE; 28 29 /* Set PLL ldo voltage without this PLL6 does not work properly */ 30 clrsetbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK, 31 PRCM_PLL_CTRL_LDO_KEY); 32 clrsetbits_le32(&prcm->pll_ctrl1, ~PRCM_PLL_CTRL_LDO_KEY_MASK, 33 PRCM_PLL_CTRL_LDO_DIGITAL_EN | PRCM_PLL_CTRL_LDO_ANALOG_EN | 34 PRCM_PLL_CTRL_EXT_OSC_EN | PRCM_PLL_CTRL_LDO_OUT_L(1140)); 35 clrbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK); 36 #endif 37 38 #if defined(CONFIG_MACH_SUN8I_R40) || defined(CONFIG_MACH_SUN50I) 39 /* Set PLL lock enable bits and switch to old lock mode */ 40 writel(GENMASK(12, 0), &ccm->pll_lock_ctrl); 41 #endif 42 43 clock_set_pll1(408000000); 44 45 writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg); 46 while (!(readl(&ccm->pll6_cfg) & CCM_PLL6_CTRL_LOCK)) 47 ; 48 49 writel(AHB1_ABP1_DIV_DEFAULT, &ccm->ahb1_apb1_div); 50 51 writel(MBUS_CLK_DEFAULT, &ccm->mbus0_clk_cfg); 52 if (IS_ENABLED(CONFIG_MACH_SUN6I)) 53 writel(MBUS_CLK_DEFAULT, &ccm->mbus1_clk_cfg); 54 55 #if defined(CONFIG_MACH_SUN8I_R40) && defined(CONFIG_SUNXI_AHCI) 56 setbits_le32(&ccm->sata_pll_cfg, CCM_SATA_PLL_DEFAULT); 57 setbits_le32(&ccm->ahb_reset0_cfg, 0x1 << AHB_GATE_OFFSET_SATA); 58 setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_SATA); 59 setbits_le32(&ccm->sata_clk_cfg, CCM_SATA_CTRL_ENABLE); 60 #endif 61 } 62 #endif 63 64 void clock_init_sec(void) 65 { 66 #ifdef CONFIG_MACH_SUNXI_H3_H5 67 struct sunxi_ccm_reg * const ccm = 68 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 69 70 setbits_le32(&ccm->ccu_sec_switch, 71 CCM_SEC_SWITCH_MBUS_NONSEC | 72 CCM_SEC_SWITCH_BUS_NONSEC | 73 CCM_SEC_SWITCH_PLL_NONSEC); 74 #endif 75 } 76 77 void clock_init_uart(void) 78 { 79 #if CONFIG_CONS_INDEX < 5 80 struct sunxi_ccm_reg *const ccm = 81 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 82 83 /* uart clock source is apb2 */ 84 writel(APB2_CLK_SRC_OSC24M| 85 APB2_CLK_RATE_N_1| 86 APB2_CLK_RATE_M(1), 87 &ccm->apb2_div); 88 89 /* open the clock for uart */ 90 setbits_le32(&ccm->apb2_gate, 91 CLK_GATE_OPEN << (APB2_GATE_UART_SHIFT + 92 CONFIG_CONS_INDEX - 1)); 93 94 /* deassert uart reset */ 95 setbits_le32(&ccm->apb2_reset_cfg, 96 1 << (APB2_RESET_UART_SHIFT + 97 CONFIG_CONS_INDEX - 1)); 98 #else 99 /* enable R_PIO and R_UART clocks, and de-assert resets */ 100 prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_UART); 101 #endif 102 } 103 104 #ifdef CONFIG_SPL_BUILD 105 void clock_set_pll1(unsigned int clk) 106 { 107 struct sunxi_ccm_reg * const ccm = 108 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 109 const int p = 0; 110 int k = 1; 111 int m = 1; 112 113 if (clk > 1152000000) { 114 k = 2; 115 } else if (clk > 768000000) { 116 k = 3; 117 m = 2; 118 } 119 120 /* Switch to 24MHz clock while changing PLL1 */ 121 writel(AXI_DIV_3 << AXI_DIV_SHIFT | 122 ATB_DIV_2 << ATB_DIV_SHIFT | 123 CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT, 124 &ccm->cpu_axi_cfg); 125 126 /* 127 * sun6i: PLL1 rate = ((24000000 * n * k) >> 0) / m (p is ignored) 128 * sun8i: PLL1 rate = ((24000000 * n * k) >> p) / m 129 */ 130 writel(CCM_PLL1_CTRL_EN | CCM_PLL1_CTRL_P(p) | 131 CCM_PLL1_CTRL_N(clk / (24000000 * k / m)) | 132 CCM_PLL1_CTRL_K(k) | CCM_PLL1_CTRL_M(m), &ccm->pll1_cfg); 133 sdelay(200); 134 135 /* Switch CPU to PLL1 */ 136 writel(AXI_DIV_3 << AXI_DIV_SHIFT | 137 ATB_DIV_2 << ATB_DIV_SHIFT | 138 CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT, 139 &ccm->cpu_axi_cfg); 140 } 141 #endif 142 143 void clock_set_pll3(unsigned int clk) 144 { 145 struct sunxi_ccm_reg * const ccm = 146 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 147 const int m = 8; /* 3 MHz steps just like sun4i, sun5i and sun7i */ 148 149 if (clk == 0) { 150 clrbits_le32(&ccm->pll3_cfg, CCM_PLL3_CTRL_EN); 151 return; 152 } 153 154 /* PLL3 rate = 24000000 * n / m */ 155 writel(CCM_PLL3_CTRL_EN | CCM_PLL3_CTRL_INTEGER_MODE | 156 CCM_PLL3_CTRL_N(clk / (24000000 / m)) | CCM_PLL3_CTRL_M(m), 157 &ccm->pll3_cfg); 158 } 159 160 #ifdef CONFIG_SUNXI_DE2 161 void clock_set_pll3_factors(int m, int n) 162 { 163 struct sunxi_ccm_reg * const ccm = 164 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 165 166 /* PLL3 rate = 24000000 * n / m */ 167 writel(CCM_PLL3_CTRL_EN | CCM_PLL3_CTRL_INTEGER_MODE | 168 CCM_PLL3_CTRL_N(n) | CCM_PLL3_CTRL_M(m), 169 &ccm->pll3_cfg); 170 171 while (!(readl(&ccm->pll3_cfg) & CCM_PLL3_CTRL_LOCK)) 172 ; 173 } 174 #endif 175 176 void clock_set_pll5(unsigned int clk, bool sigma_delta_enable) 177 { 178 struct sunxi_ccm_reg * const ccm = 179 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 180 const int max_n = 32; 181 int k = 1, m = 2; 182 183 #ifdef CONFIG_MACH_SUNXI_H3_H5 184 clrsetbits_le32(&ccm->pll5_tuning_cfg, CCM_PLL5_TUN_LOCK_TIME_MASK | 185 CCM_PLL5_TUN_INIT_FREQ_MASK, 186 CCM_PLL5_TUN_LOCK_TIME(2) | CCM_PLL5_TUN_INIT_FREQ(16)); 187 #endif 188 189 if (sigma_delta_enable) 190 writel(CCM_PLL5_PATTERN, &ccm->pll5_pattern_cfg); 191 192 /* PLL5 rate = 24000000 * n * k / m */ 193 if (clk > 24000000 * k * max_n / m) { 194 m = 1; 195 if (clk > 24000000 * k * max_n / m) 196 k = 2; 197 } 198 writel(CCM_PLL5_CTRL_EN | 199 (sigma_delta_enable ? CCM_PLL5_CTRL_SIGMA_DELTA_EN : 0) | 200 CCM_PLL5_CTRL_UPD | 201 CCM_PLL5_CTRL_N(clk / (24000000 * k / m)) | 202 CCM_PLL5_CTRL_K(k) | CCM_PLL5_CTRL_M(m), &ccm->pll5_cfg); 203 204 udelay(5500); 205 } 206 207 #ifdef CONFIG_MACH_SUN6I 208 void clock_set_mipi_pll(unsigned int clk) 209 { 210 struct sunxi_ccm_reg * const ccm = 211 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 212 unsigned int k, m, n, value, diff; 213 unsigned best_k = 0, best_m = 0, best_n = 0, best_diff = 0xffffffff; 214 unsigned int src = clock_get_pll3(); 215 216 /* All calculations are in KHz to avoid overflows */ 217 clk /= 1000; 218 src /= 1000; 219 220 /* Pick the closest lower clock */ 221 for (k = 1; k <= 4; k++) { 222 for (m = 1; m <= 16; m++) { 223 for (n = 1; n <= 16; n++) { 224 value = src * n * k / m; 225 if (value > clk) 226 continue; 227 228 diff = clk - value; 229 if (diff < best_diff) { 230 best_diff = diff; 231 best_k = k; 232 best_m = m; 233 best_n = n; 234 } 235 if (diff == 0) 236 goto done; 237 } 238 } 239 } 240 241 done: 242 writel(CCM_MIPI_PLL_CTRL_EN | CCM_MIPI_PLL_CTRL_LDO_EN | 243 CCM_MIPI_PLL_CTRL_N(best_n) | CCM_MIPI_PLL_CTRL_K(best_k) | 244 CCM_MIPI_PLL_CTRL_M(best_m), &ccm->mipi_pll_cfg); 245 } 246 #endif 247 248 #ifdef CONFIG_SUNXI_DE2 249 void clock_set_pll10(unsigned int clk) 250 { 251 struct sunxi_ccm_reg * const ccm = 252 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 253 const int m = 2; /* 12 MHz steps */ 254 255 if (clk == 0) { 256 clrbits_le32(&ccm->pll10_cfg, CCM_PLL10_CTRL_EN); 257 return; 258 } 259 260 /* PLL10 rate = 24000000 * n / m */ 261 writel(CCM_PLL10_CTRL_EN | CCM_PLL10_CTRL_INTEGER_MODE | 262 CCM_PLL10_CTRL_N(clk / (24000000 / m)) | CCM_PLL10_CTRL_M(m), 263 &ccm->pll10_cfg); 264 265 while (!(readl(&ccm->pll10_cfg) & CCM_PLL10_CTRL_LOCK)) 266 ; 267 } 268 #endif 269 270 #if defined(CONFIG_MACH_SUN8I_A33) || \ 271 defined(CONFIG_MACH_SUN8I_R40) || \ 272 defined(CONFIG_MACH_SUN50I) 273 void clock_set_pll11(unsigned int clk, bool sigma_delta_enable) 274 { 275 struct sunxi_ccm_reg * const ccm = 276 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 277 278 if (sigma_delta_enable) 279 writel(CCM_PLL11_PATTERN, &ccm->pll11_pattern_cfg0); 280 281 writel(CCM_PLL11_CTRL_EN | CCM_PLL11_CTRL_UPD | 282 (sigma_delta_enable ? CCM_PLL11_CTRL_SIGMA_DELTA_EN : 0) | 283 CCM_PLL11_CTRL_N(clk / 24000000), &ccm->pll11_cfg); 284 285 while (readl(&ccm->pll11_cfg) & CCM_PLL11_CTRL_UPD) 286 ; 287 } 288 #endif 289 290 unsigned int clock_get_pll3(void) 291 { 292 struct sunxi_ccm_reg *const ccm = 293 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 294 uint32_t rval = readl(&ccm->pll3_cfg); 295 int n = ((rval & CCM_PLL3_CTRL_N_MASK) >> CCM_PLL3_CTRL_N_SHIFT) + 1; 296 int m = ((rval & CCM_PLL3_CTRL_M_MASK) >> CCM_PLL3_CTRL_M_SHIFT) + 1; 297 298 /* Multiply by 1000 after dividing by m to avoid integer overflows */ 299 return (24000 * n / m) * 1000; 300 } 301 302 unsigned int clock_get_pll6(void) 303 { 304 struct sunxi_ccm_reg *const ccm = 305 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 306 uint32_t rval = readl(&ccm->pll6_cfg); 307 int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT) + 1; 308 int k = ((rval & CCM_PLL6_CTRL_K_MASK) >> CCM_PLL6_CTRL_K_SHIFT) + 1; 309 return 24000000 * n * k / 2; 310 } 311 312 unsigned int clock_get_mipi_pll(void) 313 { 314 struct sunxi_ccm_reg *const ccm = 315 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 316 uint32_t rval = readl(&ccm->mipi_pll_cfg); 317 unsigned int n = ((rval & CCM_MIPI_PLL_CTRL_N_MASK) >> CCM_MIPI_PLL_CTRL_N_SHIFT) + 1; 318 unsigned int k = ((rval & CCM_MIPI_PLL_CTRL_K_MASK) >> CCM_MIPI_PLL_CTRL_K_SHIFT) + 1; 319 unsigned int m = ((rval & CCM_MIPI_PLL_CTRL_M_MASK) >> CCM_MIPI_PLL_CTRL_M_SHIFT) + 1; 320 unsigned int src = clock_get_pll3(); 321 322 /* Multiply by 1000 after dividing by m to avoid integer overflows */ 323 return ((src / 1000) * n * k / m) * 1000; 324 } 325 326 void clock_set_de_mod_clock(u32 *clk_cfg, unsigned int hz) 327 { 328 int pll = clock_get_pll6() * 2; 329 int div = 1; 330 331 while ((pll / div) > hz) 332 div++; 333 334 writel(CCM_DE_CTRL_GATE | CCM_DE_CTRL_PLL6_2X | CCM_DE_CTRL_M(div), 335 clk_cfg); 336 } 337