1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * sun6i specific clock code
4  *
5  * (C) Copyright 2007-2012
6  * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
7  * Tom Cubie <tangliang@allwinnertech.com>
8  *
9  * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
10  */
11 
12 #include <common.h>
13 #include <asm/io.h>
14 #include <asm/arch/clock.h>
15 #include <asm/arch/prcm.h>
16 #include <asm/arch/sys_proto.h>
17 
18 #ifdef CONFIG_SPL_BUILD
19 void clock_init_safe(void)
20 {
21 	struct sunxi_ccm_reg * const ccm =
22 		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
23 
24 #if !defined(CONFIG_MACH_SUNXI_H3_H5) && !defined(CONFIG_MACH_SUN50I)
25 	struct sunxi_prcm_reg * const prcm =
26 		(struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
27 
28 	/* Set PLL ldo voltage without this PLL6 does not work properly */
29 	clrsetbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK,
30 			PRCM_PLL_CTRL_LDO_KEY);
31 	clrsetbits_le32(&prcm->pll_ctrl1, ~PRCM_PLL_CTRL_LDO_KEY_MASK,
32 		PRCM_PLL_CTRL_LDO_DIGITAL_EN | PRCM_PLL_CTRL_LDO_ANALOG_EN |
33 		PRCM_PLL_CTRL_EXT_OSC_EN | PRCM_PLL_CTRL_LDO_OUT_L(1140));
34 	clrbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK);
35 #endif
36 
37 #if defined(CONFIG_MACH_SUN8I_R40) || defined(CONFIG_MACH_SUN50I)
38 	/* Set PLL lock enable bits and switch to old lock mode */
39 	writel(GENMASK(12, 0), &ccm->pll_lock_ctrl);
40 #endif
41 
42 	clock_set_pll1(408000000);
43 
44 	writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
45 	while (!(readl(&ccm->pll6_cfg) & CCM_PLL6_CTRL_LOCK))
46 		;
47 
48 	writel(AHB1_ABP1_DIV_DEFAULT, &ccm->ahb1_apb1_div);
49 
50 	writel(MBUS_CLK_DEFAULT, &ccm->mbus0_clk_cfg);
51 	if (IS_ENABLED(CONFIG_MACH_SUN6I))
52 		writel(MBUS_CLK_DEFAULT, &ccm->mbus1_clk_cfg);
53 
54 #if defined(CONFIG_MACH_SUN8I_R40) && defined(CONFIG_SUNXI_AHCI)
55 	setbits_le32(&ccm->sata_pll_cfg, CCM_SATA_PLL_DEFAULT);
56 	setbits_le32(&ccm->ahb_reset0_cfg, 0x1 << AHB_GATE_OFFSET_SATA);
57 	setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_SATA);
58 	setbits_le32(&ccm->sata_clk_cfg, CCM_SATA_CTRL_ENABLE);
59 #endif
60 }
61 #endif
62 
63 void clock_init_sec(void)
64 {
65 #ifdef CONFIG_MACH_SUNXI_H3_H5
66 	struct sunxi_ccm_reg * const ccm =
67 		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
68 	struct sunxi_prcm_reg * const prcm =
69 		(struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
70 
71 	setbits_le32(&ccm->ccu_sec_switch,
72 		     CCM_SEC_SWITCH_MBUS_NONSEC |
73 		     CCM_SEC_SWITCH_BUS_NONSEC |
74 		     CCM_SEC_SWITCH_PLL_NONSEC);
75 	setbits_le32(&prcm->prcm_sec_switch,
76 		     PRCM_SEC_SWITCH_APB0_CLK_NONSEC |
77 		     PRCM_SEC_SWITCH_PLL_CFG_NONSEC |
78 		     PRCM_SEC_SWITCH_PWR_GATE_NONSEC);
79 #endif
80 }
81 
82 void clock_init_uart(void)
83 {
84 #if CONFIG_CONS_INDEX < 5
85 	struct sunxi_ccm_reg *const ccm =
86 		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
87 
88 	/* uart clock source is apb2 */
89 	writel(APB2_CLK_SRC_OSC24M|
90 	       APB2_CLK_RATE_N_1|
91 	       APB2_CLK_RATE_M(1),
92 	       &ccm->apb2_div);
93 
94 	/* open the clock for uart */
95 	setbits_le32(&ccm->apb2_gate,
96 		     CLK_GATE_OPEN << (APB2_GATE_UART_SHIFT +
97 				       CONFIG_CONS_INDEX - 1));
98 
99 	/* deassert uart reset */
100 	setbits_le32(&ccm->apb2_reset_cfg,
101 		     1 << (APB2_RESET_UART_SHIFT +
102 			   CONFIG_CONS_INDEX - 1));
103 #else
104 	/* enable R_PIO and R_UART clocks, and de-assert resets */
105 	prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_UART);
106 #endif
107 }
108 
109 #ifdef CONFIG_SPL_BUILD
110 void clock_set_pll1(unsigned int clk)
111 {
112 	struct sunxi_ccm_reg * const ccm =
113 		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
114 	const int p = 0;
115 	int k = 1;
116 	int m = 1;
117 
118 	if (clk > 1152000000) {
119 		k = 2;
120 	} else if (clk > 768000000) {
121 		k = 3;
122 		m = 2;
123 	}
124 
125 	/* Switch to 24MHz clock while changing PLL1 */
126 	writel(AXI_DIV_3 << AXI_DIV_SHIFT |
127 	       ATB_DIV_2 << ATB_DIV_SHIFT |
128 	       CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT,
129 	       &ccm->cpu_axi_cfg);
130 
131 	/*
132 	 * sun6i: PLL1 rate = ((24000000 * n * k) >> 0) / m   (p is ignored)
133 	 * sun8i: PLL1 rate = ((24000000 * n * k) >> p) / m
134 	 */
135 	writel(CCM_PLL1_CTRL_EN | CCM_PLL1_CTRL_P(p) |
136 	       CCM_PLL1_CTRL_N(clk / (24000000 * k / m)) |
137 	       CCM_PLL1_CTRL_K(k) | CCM_PLL1_CTRL_M(m), &ccm->pll1_cfg);
138 	sdelay(200);
139 
140 	/* Switch CPU to PLL1 */
141 	writel(AXI_DIV_3 << AXI_DIV_SHIFT |
142 	       ATB_DIV_2 << ATB_DIV_SHIFT |
143 	       CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT,
144 	       &ccm->cpu_axi_cfg);
145 }
146 #endif
147 
148 void clock_set_pll3(unsigned int clk)
149 {
150 	struct sunxi_ccm_reg * const ccm =
151 		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
152 #ifdef CONFIG_SUNXI_DE2
153 	const int m = 4; /* 6 MHz steps to allow higher frequency for DE2 */
154 #else
155 	const int m = 8; /* 3 MHz steps just like sun4i, sun5i and sun7i */
156 #endif
157 
158 	if (clk == 0) {
159 		clrbits_le32(&ccm->pll3_cfg, CCM_PLL3_CTRL_EN);
160 		return;
161 	}
162 
163 	/* PLL3 rate = 24000000 * n / m */
164 	writel(CCM_PLL3_CTRL_EN | CCM_PLL3_CTRL_INTEGER_MODE |
165 	       CCM_PLL3_CTRL_N(clk / (24000000 / m)) | CCM_PLL3_CTRL_M(m),
166 	       &ccm->pll3_cfg);
167 }
168 
169 #ifdef CONFIG_SUNXI_DE2
170 void clock_set_pll3_factors(int m, int n)
171 {
172 	struct sunxi_ccm_reg * const ccm =
173 		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
174 
175 	/* PLL3 rate = 24000000 * n / m */
176 	writel(CCM_PLL3_CTRL_EN | CCM_PLL3_CTRL_INTEGER_MODE |
177 	       CCM_PLL3_CTRL_N(n) | CCM_PLL3_CTRL_M(m),
178 	       &ccm->pll3_cfg);
179 
180 	while (!(readl(&ccm->pll3_cfg) & CCM_PLL3_CTRL_LOCK))
181 		;
182 }
183 #endif
184 
185 void clock_set_pll5(unsigned int clk, bool sigma_delta_enable)
186 {
187 	struct sunxi_ccm_reg * const ccm =
188 		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
189 	const int max_n = 32;
190 	int k = 1, m = 2;
191 
192 #ifdef CONFIG_MACH_SUNXI_H3_H5
193 	clrsetbits_le32(&ccm->pll5_tuning_cfg, CCM_PLL5_TUN_LOCK_TIME_MASK |
194 			CCM_PLL5_TUN_INIT_FREQ_MASK,
195 			CCM_PLL5_TUN_LOCK_TIME(2) | CCM_PLL5_TUN_INIT_FREQ(16));
196 #endif
197 
198 	if (sigma_delta_enable)
199 		writel(CCM_PLL5_PATTERN, &ccm->pll5_pattern_cfg);
200 
201 	/* PLL5 rate = 24000000 * n * k / m */
202 	if (clk > 24000000 * k * max_n / m) {
203 		m = 1;
204 		if (clk > 24000000 * k * max_n / m)
205 			k = 2;
206 	}
207 	writel(CCM_PLL5_CTRL_EN |
208 	       (sigma_delta_enable ? CCM_PLL5_CTRL_SIGMA_DELTA_EN : 0) |
209 	       CCM_PLL5_CTRL_UPD |
210 	       CCM_PLL5_CTRL_N(clk / (24000000 * k / m)) |
211 	       CCM_PLL5_CTRL_K(k) | CCM_PLL5_CTRL_M(m), &ccm->pll5_cfg);
212 
213 	udelay(5500);
214 }
215 
216 #ifdef CONFIG_MACH_SUN6I
217 void clock_set_mipi_pll(unsigned int clk)
218 {
219 	struct sunxi_ccm_reg * const ccm =
220 		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
221 	unsigned int k, m, n, value, diff;
222 	unsigned best_k = 0, best_m = 0, best_n = 0, best_diff = 0xffffffff;
223 	unsigned int src = clock_get_pll3();
224 
225 	/* All calculations are in KHz to avoid overflows */
226 	clk /= 1000;
227 	src /= 1000;
228 
229 	/* Pick the closest lower clock */
230 	for (k = 1; k <= 4; k++) {
231 		for (m = 1; m <= 16; m++) {
232 			for (n = 1; n <= 16; n++) {
233 				value = src * n * k / m;
234 				if (value > clk)
235 					continue;
236 
237 				diff = clk - value;
238 				if (diff < best_diff) {
239 					best_diff = diff;
240 					best_k = k;
241 					best_m = m;
242 					best_n = n;
243 				}
244 				if (diff == 0)
245 					goto done;
246 			}
247 		}
248 	}
249 
250 done:
251 	writel(CCM_MIPI_PLL_CTRL_EN | CCM_MIPI_PLL_CTRL_LDO_EN |
252 	       CCM_MIPI_PLL_CTRL_N(best_n) | CCM_MIPI_PLL_CTRL_K(best_k) |
253 	       CCM_MIPI_PLL_CTRL_M(best_m), &ccm->mipi_pll_cfg);
254 }
255 #endif
256 
257 #ifdef CONFIG_SUNXI_DE2
258 void clock_set_pll10(unsigned int clk)
259 {
260 	struct sunxi_ccm_reg * const ccm =
261 		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
262 	const int m = 2; /* 12 MHz steps */
263 
264 	if (clk == 0) {
265 		clrbits_le32(&ccm->pll10_cfg, CCM_PLL10_CTRL_EN);
266 		return;
267 	}
268 
269 	/* PLL10 rate = 24000000 * n / m */
270 	writel(CCM_PLL10_CTRL_EN | CCM_PLL10_CTRL_INTEGER_MODE |
271 	       CCM_PLL10_CTRL_N(clk / (24000000 / m)) | CCM_PLL10_CTRL_M(m),
272 	       &ccm->pll10_cfg);
273 
274 	while (!(readl(&ccm->pll10_cfg) & CCM_PLL10_CTRL_LOCK))
275 		;
276 }
277 #endif
278 
279 #if defined(CONFIG_MACH_SUN8I_A33) || \
280     defined(CONFIG_MACH_SUN8I_R40) || \
281     defined(CONFIG_MACH_SUN50I)
282 void clock_set_pll11(unsigned int clk, bool sigma_delta_enable)
283 {
284 	struct sunxi_ccm_reg * const ccm =
285 		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
286 
287 	if (sigma_delta_enable)
288 		writel(CCM_PLL11_PATTERN, &ccm->pll11_pattern_cfg0);
289 
290 	writel(CCM_PLL11_CTRL_EN | CCM_PLL11_CTRL_UPD |
291 	       (sigma_delta_enable ? CCM_PLL11_CTRL_SIGMA_DELTA_EN : 0) |
292 	       CCM_PLL11_CTRL_N(clk / 24000000), &ccm->pll11_cfg);
293 
294 	while (readl(&ccm->pll11_cfg) & CCM_PLL11_CTRL_UPD)
295 		;
296 }
297 #endif
298 
299 unsigned int clock_get_pll3(void)
300 {
301 	struct sunxi_ccm_reg *const ccm =
302 		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
303 	uint32_t rval = readl(&ccm->pll3_cfg);
304 	int n = ((rval & CCM_PLL3_CTRL_N_MASK) >> CCM_PLL3_CTRL_N_SHIFT) + 1;
305 	int m = ((rval & CCM_PLL3_CTRL_M_MASK) >> CCM_PLL3_CTRL_M_SHIFT) + 1;
306 
307 	/* Multiply by 1000 after dividing by m to avoid integer overflows */
308 	return (24000 * n / m) * 1000;
309 }
310 
311 unsigned int clock_get_pll6(void)
312 {
313 	struct sunxi_ccm_reg *const ccm =
314 		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
315 	uint32_t rval = readl(&ccm->pll6_cfg);
316 	int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT) + 1;
317 	int k = ((rval & CCM_PLL6_CTRL_K_MASK) >> CCM_PLL6_CTRL_K_SHIFT) + 1;
318 	return 24000000 * n * k / 2;
319 }
320 
321 unsigned int clock_get_mipi_pll(void)
322 {
323 	struct sunxi_ccm_reg *const ccm =
324 		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
325 	uint32_t rval = readl(&ccm->mipi_pll_cfg);
326 	unsigned int n = ((rval & CCM_MIPI_PLL_CTRL_N_MASK) >> CCM_MIPI_PLL_CTRL_N_SHIFT) + 1;
327 	unsigned int k = ((rval & CCM_MIPI_PLL_CTRL_K_MASK) >> CCM_MIPI_PLL_CTRL_K_SHIFT) + 1;
328 	unsigned int m = ((rval & CCM_MIPI_PLL_CTRL_M_MASK) >> CCM_MIPI_PLL_CTRL_M_SHIFT) + 1;
329 	unsigned int src = clock_get_pll3();
330 
331 	/* Multiply by 1000 after dividing by m to avoid integer overflows */
332 	return ((src / 1000) * n * k / m) * 1000;
333 }
334 
335 void clock_set_de_mod_clock(u32 *clk_cfg, unsigned int hz)
336 {
337 	int pll = clock_get_pll6() * 2;
338 	int div = 1;
339 
340 	while ((pll / div) > hz)
341 		div++;
342 
343 	writel(CCM_DE_CTRL_GATE | CCM_DE_CTRL_PLL6_2X | CCM_DE_CTRL_M(div),
344 	       clk_cfg);
345 }
346