1 /* 2 * sun6i specific clock code 3 * 4 * (C) Copyright 2007-2012 5 * Allwinner Technology Co., Ltd. <www.allwinnertech.com> 6 * Tom Cubie <tangliang@allwinnertech.com> 7 * 8 * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net> 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 #include <common.h> 14 #include <asm/io.h> 15 #include <asm/arch/clock.h> 16 #include <asm/arch/prcm.h> 17 #include <asm/arch/sys_proto.h> 18 19 #ifdef CONFIG_SPL_BUILD 20 void clock_init_safe(void) 21 { 22 struct sunxi_ccm_reg * const ccm = 23 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 24 struct sunxi_prcm_reg * const prcm = 25 (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE; 26 27 /* Set PLL ldo voltage without this PLL6 does not work properly */ 28 clrsetbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK, 29 PRCM_PLL_CTRL_LDO_KEY); 30 clrsetbits_le32(&prcm->pll_ctrl1, ~PRCM_PLL_CTRL_LDO_KEY_MASK, 31 PRCM_PLL_CTRL_LDO_DIGITAL_EN | PRCM_PLL_CTRL_LDO_ANALOG_EN | 32 PRCM_PLL_CTRL_EXT_OSC_EN | PRCM_PLL_CTRL_LDO_OUT_L(1140)); 33 clrbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK); 34 35 clock_set_pll1(408000000); 36 37 writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg); 38 while (!(readl(&ccm->pll6_cfg) & CCM_PLL6_CTRL_LOCK)) 39 ; 40 41 writel(AHB1_ABP1_DIV_DEFAULT, &ccm->ahb1_apb1_div); 42 43 writel(MBUS_CLK_DEFAULT, &ccm->mbus0_clk_cfg); 44 writel(MBUS_CLK_DEFAULT, &ccm->mbus1_clk_cfg); 45 } 46 #endif 47 48 void clock_init_sec(void) 49 { 50 #ifdef CONFIG_MACH_SUN8I_H3 51 struct sunxi_ccm_reg * const ccm = 52 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 53 54 setbits_le32(&ccm->ccu_sec_switch, 55 CCM_SEC_SWITCH_MBUS_NONSEC | 56 CCM_SEC_SWITCH_BUS_NONSEC | 57 CCM_SEC_SWITCH_PLL_NONSEC); 58 #endif 59 } 60 61 void clock_init_uart(void) 62 { 63 #if CONFIG_CONS_INDEX < 5 64 struct sunxi_ccm_reg *const ccm = 65 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 66 67 /* uart clock source is apb2 */ 68 writel(APB2_CLK_SRC_OSC24M| 69 APB2_CLK_RATE_N_1| 70 APB2_CLK_RATE_M(1), 71 &ccm->apb2_div); 72 73 /* open the clock for uart */ 74 setbits_le32(&ccm->apb2_gate, 75 CLK_GATE_OPEN << (APB2_GATE_UART_SHIFT + 76 CONFIG_CONS_INDEX - 1)); 77 78 /* deassert uart reset */ 79 setbits_le32(&ccm->apb2_reset_cfg, 80 1 << (APB2_RESET_UART_SHIFT + 81 CONFIG_CONS_INDEX - 1)); 82 #else 83 /* enable R_PIO and R_UART clocks, and de-assert resets */ 84 prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_UART); 85 #endif 86 } 87 88 #ifdef CONFIG_SPL_BUILD 89 void clock_set_pll1(unsigned int clk) 90 { 91 struct sunxi_ccm_reg * const ccm = 92 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 93 const int p = 0; 94 int k = 1; 95 int m = 1; 96 97 if (clk > 1152000000) { 98 k = 2; 99 } else if (clk > 768000000) { 100 k = 3; 101 m = 2; 102 } 103 104 /* Switch to 24MHz clock while changing PLL1 */ 105 writel(AXI_DIV_3 << AXI_DIV_SHIFT | 106 ATB_DIV_2 << ATB_DIV_SHIFT | 107 CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT, 108 &ccm->cpu_axi_cfg); 109 110 /* 111 * sun6i: PLL1 rate = ((24000000 * n * k) >> 0) / m (p is ignored) 112 * sun8i: PLL1 rate = ((24000000 * n * k) >> p) / m 113 */ 114 writel(CCM_PLL1_CTRL_EN | CCM_PLL1_CTRL_P(p) | 115 CCM_PLL1_CTRL_N(clk / (24000000 * k / m)) | 116 CCM_PLL1_CTRL_K(k) | CCM_PLL1_CTRL_M(m), &ccm->pll1_cfg); 117 sdelay(200); 118 119 /* Switch CPU to PLL1 */ 120 writel(AXI_DIV_3 << AXI_DIV_SHIFT | 121 ATB_DIV_2 << ATB_DIV_SHIFT | 122 CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT, 123 &ccm->cpu_axi_cfg); 124 } 125 #endif 126 127 void clock_set_pll3(unsigned int clk) 128 { 129 struct sunxi_ccm_reg * const ccm = 130 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 131 const int m = 8; /* 3 MHz steps just like sun4i, sun5i and sun7i */ 132 133 if (clk == 0) { 134 clrbits_le32(&ccm->pll3_cfg, CCM_PLL3_CTRL_EN); 135 return; 136 } 137 138 /* PLL3 rate = 24000000 * n / m */ 139 writel(CCM_PLL3_CTRL_EN | CCM_PLL3_CTRL_INTEGER_MODE | 140 CCM_PLL3_CTRL_N(clk / (24000000 / m)) | CCM_PLL3_CTRL_M(m), 141 &ccm->pll3_cfg); 142 } 143 144 void clock_set_pll5(unsigned int clk, bool sigma_delta_enable) 145 { 146 struct sunxi_ccm_reg * const ccm = 147 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 148 const int max_n = 32; 149 int k = 1, m = 2; 150 151 #ifdef CONFIG_MACH_SUN8I_H3 152 clrsetbits_le32(&ccm->pll5_tuning_cfg, CCM_PLL5_TUN_LOCK_TIME_MASK | 153 CCM_PLL5_TUN_INIT_FREQ_MASK, 154 CCM_PLL5_TUN_LOCK_TIME(2) | CCM_PLL5_TUN_INIT_FREQ(16)); 155 #endif 156 157 if (sigma_delta_enable) 158 writel(CCM_PLL5_PATTERN, &ccm->pll5_pattern_cfg); 159 160 /* PLL5 rate = 24000000 * n * k / m */ 161 if (clk > 24000000 * k * max_n / m) { 162 m = 1; 163 if (clk > 24000000 * k * max_n / m) 164 k = 2; 165 } 166 writel(CCM_PLL5_CTRL_EN | 167 (sigma_delta_enable ? CCM_PLL5_CTRL_SIGMA_DELTA_EN : 0) | 168 CCM_PLL5_CTRL_UPD | 169 CCM_PLL5_CTRL_N(clk / (24000000 * k / m)) | 170 CCM_PLL5_CTRL_K(k) | CCM_PLL5_CTRL_M(m), &ccm->pll5_cfg); 171 172 udelay(5500); 173 } 174 175 #ifdef CONFIG_MACH_SUN6I 176 void clock_set_mipi_pll(unsigned int clk) 177 { 178 struct sunxi_ccm_reg * const ccm = 179 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 180 unsigned int k, m, n, value, diff; 181 unsigned best_k = 0, best_m = 0, best_n = 0, best_diff = 0xffffffff; 182 unsigned int src = clock_get_pll3(); 183 184 /* All calculations are in KHz to avoid overflows */ 185 clk /= 1000; 186 src /= 1000; 187 188 /* Pick the closest lower clock */ 189 for (k = 1; k <= 4; k++) { 190 for (m = 1; m <= 16; m++) { 191 for (n = 1; n <= 16; n++) { 192 value = src * n * k / m; 193 if (value > clk) 194 continue; 195 196 diff = clk - value; 197 if (diff < best_diff) { 198 best_diff = diff; 199 best_k = k; 200 best_m = m; 201 best_n = n; 202 } 203 if (diff == 0) 204 goto done; 205 } 206 } 207 } 208 209 done: 210 writel(CCM_MIPI_PLL_CTRL_EN | CCM_MIPI_PLL_CTRL_LDO_EN | 211 CCM_MIPI_PLL_CTRL_N(best_n) | CCM_MIPI_PLL_CTRL_K(best_k) | 212 CCM_MIPI_PLL_CTRL_M(best_m), &ccm->mipi_pll_cfg); 213 } 214 #endif 215 216 #ifdef CONFIG_MACH_SUN8I_A33 217 void clock_set_pll11(unsigned int clk, bool sigma_delta_enable) 218 { 219 struct sunxi_ccm_reg * const ccm = 220 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 221 222 if (sigma_delta_enable) 223 writel(CCM_PLL11_PATTERN, &ccm->pll5_pattern_cfg); 224 225 writel(CCM_PLL11_CTRL_EN | CCM_PLL11_CTRL_UPD | 226 (sigma_delta_enable ? CCM_PLL11_CTRL_SIGMA_DELTA_EN : 0) | 227 CCM_PLL11_CTRL_N(clk / 24000000), &ccm->pll11_cfg); 228 229 while (readl(&ccm->pll11_cfg) & CCM_PLL11_CTRL_UPD) 230 ; 231 } 232 #endif 233 234 unsigned int clock_get_pll3(void) 235 { 236 struct sunxi_ccm_reg *const ccm = 237 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 238 uint32_t rval = readl(&ccm->pll3_cfg); 239 int n = ((rval & CCM_PLL3_CTRL_N_MASK) >> CCM_PLL3_CTRL_N_SHIFT) + 1; 240 int m = ((rval & CCM_PLL3_CTRL_M_MASK) >> CCM_PLL3_CTRL_M_SHIFT) + 1; 241 242 /* Multiply by 1000 after dividing by m to avoid integer overflows */ 243 return (24000 * n / m) * 1000; 244 } 245 246 unsigned int clock_get_pll6(void) 247 { 248 struct sunxi_ccm_reg *const ccm = 249 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 250 uint32_t rval = readl(&ccm->pll6_cfg); 251 int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT) + 1; 252 int k = ((rval & CCM_PLL6_CTRL_K_MASK) >> CCM_PLL6_CTRL_K_SHIFT) + 1; 253 return 24000000 * n * k / 2; 254 } 255 256 unsigned int clock_get_mipi_pll(void) 257 { 258 struct sunxi_ccm_reg *const ccm = 259 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 260 uint32_t rval = readl(&ccm->mipi_pll_cfg); 261 unsigned int n = ((rval & CCM_MIPI_PLL_CTRL_N_MASK) >> CCM_MIPI_PLL_CTRL_N_SHIFT) + 1; 262 unsigned int k = ((rval & CCM_MIPI_PLL_CTRL_K_MASK) >> CCM_MIPI_PLL_CTRL_K_SHIFT) + 1; 263 unsigned int m = ((rval & CCM_MIPI_PLL_CTRL_M_MASK) >> CCM_MIPI_PLL_CTRL_M_SHIFT) + 1; 264 unsigned int src = clock_get_pll3(); 265 266 /* Multiply by 1000 after dividing by m to avoid integer overflows */ 267 return ((src / 1000) * n * k / m) * 1000; 268 } 269 270 void clock_set_de_mod_clock(u32 *clk_cfg, unsigned int hz) 271 { 272 int pll = clock_get_pll6() * 2; 273 int div = 1; 274 275 while ((pll / div) > hz) 276 div++; 277 278 writel(CCM_DE_CTRL_GATE | CCM_DE_CTRL_PLL6_2X | CCM_DE_CTRL_M(div), 279 clk_cfg); 280 } 281