1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net> 4 * 5 * (C) Copyright 2007-2011 6 * Allwinner Technology Co., Ltd. <www.allwinnertech.com> 7 * Tom Cubie <tangliang@allwinnertech.com> 8 * 9 * Some init for sunxi platform. 10 */ 11 12 #include <common.h> 13 #include <mmc.h> 14 #include <i2c.h> 15 #include <serial.h> 16 #include <spl.h> 17 #include <asm/gpio.h> 18 #include <asm/io.h> 19 #include <asm/arch/clock.h> 20 #include <asm/arch/gpio.h> 21 #include <asm/arch/spl.h> 22 #include <asm/arch/sys_proto.h> 23 #include <asm/arch/timer.h> 24 #include <asm/arch/tzpc.h> 25 #include <asm/arch/mmc.h> 26 27 #include <linux/compiler.h> 28 29 struct fel_stash { 30 uint32_t sp; 31 uint32_t lr; 32 uint32_t cpsr; 33 uint32_t sctlr; 34 uint32_t vbar; 35 uint32_t cr; 36 }; 37 38 struct fel_stash fel_stash __attribute__((section(".data"))); 39 40 #ifdef CONFIG_ARM64 41 #include <asm/armv8/mmu.h> 42 43 static struct mm_region sunxi_mem_map[] = { 44 { 45 /* SRAM, MMIO regions */ 46 .virt = 0x0UL, 47 .phys = 0x0UL, 48 .size = 0x40000000UL, 49 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 50 PTE_BLOCK_NON_SHARE 51 }, { 52 /* RAM */ 53 .virt = 0x40000000UL, 54 .phys = 0x40000000UL, 55 .size = 0x80000000UL, 56 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | 57 PTE_BLOCK_INNER_SHARE 58 }, { 59 /* List terminator */ 60 0, 61 } 62 }; 63 struct mm_region *mem_map = sunxi_mem_map; 64 #endif 65 66 static int gpio_init(void) 67 { 68 #if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F) 69 #if defined(CONFIG_MACH_SUN4I) || \ 70 defined(CONFIG_MACH_SUN7I) || \ 71 defined(CONFIG_MACH_SUN8I_R40) 72 /* disable GPB22,23 as uart0 tx,rx to avoid conflict */ 73 sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUNXI_GPIO_INPUT); 74 sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT); 75 #endif 76 #if defined(CONFIG_MACH_SUN8I) && !defined(CONFIG_MACH_SUN8I_R40) 77 sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUN8I_GPF_UART0); 78 sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUN8I_GPF_UART0); 79 #else 80 sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUNXI_GPF_UART0); 81 sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF_UART0); 82 #endif 83 sunxi_gpio_set_pull(SUNXI_GPF(4), 1); 84 #elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_MACH_SUN4I) || \ 85 defined(CONFIG_MACH_SUN7I) || \ 86 defined(CONFIG_MACH_SUN8I_R40)) 87 sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB_UART0); 88 sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB_UART0); 89 sunxi_gpio_set_pull(SUNXI_GPB(23), SUNXI_GPIO_PULL_UP); 90 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN5I) 91 sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB_UART0); 92 sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB_UART0); 93 sunxi_gpio_set_pull(SUNXI_GPB(20), SUNXI_GPIO_PULL_UP); 94 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN6I) 95 sunxi_gpio_set_cfgpin(SUNXI_GPH(20), SUN6I_GPH_UART0); 96 sunxi_gpio_set_cfgpin(SUNXI_GPH(21), SUN6I_GPH_UART0); 97 sunxi_gpio_set_pull(SUNXI_GPH(21), SUNXI_GPIO_PULL_UP); 98 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A33) 99 sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_A33_GPB_UART0); 100 sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_A33_GPB_UART0); 101 sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP); 102 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUNXI_H3_H5) 103 sunxi_gpio_set_cfgpin(SUNXI_GPA(4), SUN8I_H3_GPA_UART0); 104 sunxi_gpio_set_cfgpin(SUNXI_GPA(5), SUN8I_H3_GPA_UART0); 105 sunxi_gpio_set_pull(SUNXI_GPA(5), SUNXI_GPIO_PULL_UP); 106 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN50I) 107 sunxi_gpio_set_cfgpin(SUNXI_GPB(8), SUN50I_GPB_UART0); 108 sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN50I_GPB_UART0); 109 sunxi_gpio_set_pull(SUNXI_GPB(9), SUNXI_GPIO_PULL_UP); 110 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A83T) 111 sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_A83T_GPB_UART0); 112 sunxi_gpio_set_cfgpin(SUNXI_GPB(10), SUN8I_A83T_GPB_UART0); 113 sunxi_gpio_set_pull(SUNXI_GPB(10), SUNXI_GPIO_PULL_UP); 114 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_V3S) 115 sunxi_gpio_set_cfgpin(SUNXI_GPB(8), SUN8I_V3S_GPB_UART0); 116 sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_V3S_GPB_UART0); 117 sunxi_gpio_set_pull(SUNXI_GPB(9), SUNXI_GPIO_PULL_UP); 118 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN9I) 119 sunxi_gpio_set_cfgpin(SUNXI_GPH(12), SUN9I_GPH_UART0); 120 sunxi_gpio_set_cfgpin(SUNXI_GPH(13), SUN9I_GPH_UART0); 121 sunxi_gpio_set_pull(SUNXI_GPH(13), SUNXI_GPIO_PULL_UP); 122 #elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I) 123 sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG_UART1); 124 sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG_UART1); 125 sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP); 126 #elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I) 127 sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_GPB_UART2); 128 sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_GPB_UART2); 129 sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP); 130 #elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I) 131 sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL_R_UART); 132 sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL_R_UART); 133 sunxi_gpio_set_pull(SUNXI_GPL(3), SUNXI_GPIO_PULL_UP); 134 #else 135 #error Unsupported console port number. Please fix pin mux settings in board.c 136 #endif 137 138 return 0; 139 } 140 141 #if defined(CONFIG_SPL_BOARD_LOAD_IMAGE) && defined(CONFIG_SPL_BUILD) 142 static int spl_board_load_image(struct spl_image_info *spl_image, 143 struct spl_boot_device *bootdev) 144 { 145 debug("Returning to FEL sp=%x, lr=%x\n", fel_stash.sp, fel_stash.lr); 146 return_to_fel(fel_stash.sp, fel_stash.lr); 147 148 return 0; 149 } 150 SPL_LOAD_IMAGE_METHOD("FEL", 0, BOOT_DEVICE_BOARD, spl_board_load_image); 151 #endif 152 153 void s_init(void) 154 { 155 /* 156 * Undocumented magic taken from boot0, without this DRAM 157 * access gets messed up (seems cache related). 158 * The boot0 sources describe this as: "config ema for cache sram" 159 */ 160 #if defined CONFIG_MACH_SUN6I 161 setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800); 162 #elif defined CONFIG_MACH_SUN8I 163 __maybe_unused uint version; 164 165 /* Unlock sram version info reg, read it, relock */ 166 setbits_le32(SUNXI_SRAMC_BASE + 0x24, (1 << 15)); 167 version = readl(SUNXI_SRAMC_BASE + 0x24) >> 16; 168 clrbits_le32(SUNXI_SRAMC_BASE + 0x24, (1 << 15)); 169 170 /* 171 * Ideally this would be a switch case, but we do not know exactly 172 * which versions there are and which version needs which settings, 173 * so reproduce the per SoC code from the BSP. 174 */ 175 #if defined CONFIG_MACH_SUN8I_A23 176 if (version == 0x1650) 177 setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800); 178 else /* 0x1661 ? */ 179 setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0xc0); 180 #elif defined CONFIG_MACH_SUN8I_A33 181 if (version != 0x1667) 182 setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0xc0); 183 #endif 184 /* A83T BSP never modifies SUNXI_SRAMC_BASE + 0x44 */ 185 /* No H3 BSP, boot0 seems to not modify SUNXI_SRAMC_BASE + 0x44 */ 186 #endif 187 188 #if !defined(CONFIG_ARM_CORTEX_CPU_IS_UP) && !defined(CONFIG_ARM64) 189 /* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */ 190 asm volatile( 191 "mrc p15, 0, r0, c1, c0, 1\n" 192 "orr r0, r0, #1 << 6\n" 193 "mcr p15, 0, r0, c1, c0, 1\n" 194 ::: "r0"); 195 #endif 196 #if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I_H3 197 /* Enable non-secure access to some peripherals */ 198 tzpc_init(); 199 #endif 200 201 clock_init(); 202 timer_init(); 203 gpio_init(); 204 #ifndef CONFIG_DM_I2C 205 i2c_init_board(); 206 #endif 207 eth_init_board(); 208 } 209 210 #ifdef CONFIG_SPL_BUILD 211 #endif 212 213 /* The sunxi internal brom will try to loader external bootloader 214 * from mmc0, nand flash, mmc2. 215 */ 216 uint32_t sunxi_get_boot_device(void) 217 { 218 int boot_source; 219 220 /* 221 * When booting from the SD card or NAND memory, the "eGON.BT0" 222 * signature is expected to be found in memory at the address 0x0004 223 * (see the "mksunxiboot" tool, which generates this header). 224 * 225 * When booting in the FEL mode over USB, this signature is patched in 226 * memory and replaced with something else by the 'fel' tool. This other 227 * signature is selected in such a way, that it can't be present in a 228 * valid bootable SD card image (because the BROM would refuse to 229 * execute the SPL in this case). 230 * 231 * This checks for the signature and if it is not found returns to 232 * the FEL code in the BROM to wait and receive the main u-boot 233 * binary over USB. If it is found, it determines where SPL was 234 * read from. 235 */ 236 if (!is_boot0_magic(SPL_ADDR + 4)) /* eGON.BT0 */ 237 return BOOT_DEVICE_BOARD; 238 239 boot_source = readb(SPL_ADDR + 0x28); 240 switch (boot_source) { 241 case SUNXI_BOOTED_FROM_MMC0: 242 return BOOT_DEVICE_MMC1; 243 case SUNXI_BOOTED_FROM_NAND: 244 return BOOT_DEVICE_NAND; 245 case SUNXI_BOOTED_FROM_MMC2: 246 return BOOT_DEVICE_MMC2; 247 case SUNXI_BOOTED_FROM_SPI: 248 return BOOT_DEVICE_SPI; 249 } 250 251 panic("Unknown boot source %d\n", boot_source); 252 return -1; /* Never reached */ 253 } 254 255 #ifdef CONFIG_SPL_BUILD 256 u32 spl_boot_device(void) 257 { 258 return sunxi_get_boot_device(); 259 } 260 261 void board_init_f(ulong dummy) 262 { 263 spl_init(); 264 preloader_console_init(); 265 266 #ifdef CONFIG_SPL_I2C_SUPPORT 267 /* Needed early by sunxi_board_init if PMU is enabled */ 268 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); 269 #endif 270 sunxi_board_init(); 271 } 272 #endif 273 274 void reset_cpu(ulong addr) 275 { 276 #if defined(CONFIG_SUNXI_GEN_SUN4I) || defined(CONFIG_MACH_SUN8I_R40) 277 static const struct sunxi_wdog *wdog = 278 &((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog; 279 280 /* Set the watchdog for its shortest interval (.5s) and wait */ 281 writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode); 282 writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl); 283 284 while (1) { 285 /* sun5i sometimes gets stuck without this */ 286 writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode); 287 } 288 #elif defined(CONFIG_SUNXI_GEN_SUN6I) 289 static const struct sunxi_wdog *wdog = 290 ((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog; 291 292 /* Set the watchdog for its shortest interval (.5s) and wait */ 293 writel(WDT_CFG_RESET, &wdog->cfg); 294 writel(WDT_MODE_EN, &wdog->mode); 295 writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl); 296 while (1) { } 297 #endif 298 } 299 300 #if !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_ARM64) 301 void enable_caches(void) 302 { 303 /* Enable D-cache. I-cache is already enabled in start.S */ 304 dcache_enable(); 305 } 306 #endif 307