1 /* 2 * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net> 3 * 4 * (C) Copyright 2007-2011 5 * Allwinner Technology Co., Ltd. <www.allwinnertech.com> 6 * Tom Cubie <tangliang@allwinnertech.com> 7 * 8 * Some init for sunxi platform. 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 #include <common.h> 14 #include <mmc.h> 15 #include <i2c.h> 16 #include <serial.h> 17 #ifdef CONFIG_SPL_BUILD 18 #include <spl.h> 19 #endif 20 #include <asm/gpio.h> 21 #include <asm/io.h> 22 #include <asm/arch/clock.h> 23 #include <asm/arch/gpio.h> 24 #include <asm/arch/spl.h> 25 #include <asm/arch/sys_proto.h> 26 #include <asm/arch/timer.h> 27 #include <asm/arch/tzpc.h> 28 #include <asm/arch/mmc.h> 29 30 #include <linux/compiler.h> 31 32 struct fel_stash { 33 uint32_t sp; 34 uint32_t lr; 35 uint32_t cpsr; 36 uint32_t sctlr; 37 uint32_t vbar; 38 uint32_t cr; 39 }; 40 41 struct fel_stash fel_stash __attribute__((section(".data"))); 42 43 #ifdef CONFIG_ARM64 44 #include <asm/armv8/mmu.h> 45 46 static struct mm_region sunxi_mem_map[] = { 47 { 48 /* SRAM, MMIO regions */ 49 .virt = 0x0UL, 50 .phys = 0x0UL, 51 .size = 0x40000000UL, 52 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 53 PTE_BLOCK_NON_SHARE 54 }, { 55 /* RAM */ 56 .virt = 0x40000000UL, 57 .phys = 0x40000000UL, 58 .size = 0x80000000UL, 59 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | 60 PTE_BLOCK_INNER_SHARE 61 }, { 62 /* List terminator */ 63 0, 64 } 65 }; 66 struct mm_region *mem_map = sunxi_mem_map; 67 #endif 68 69 static int gpio_init(void) 70 { 71 #if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F) 72 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) 73 /* disable GPB22,23 as uart0 tx,rx to avoid conflict */ 74 sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUNXI_GPIO_INPUT); 75 sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT); 76 #endif 77 #if defined(CONFIG_MACH_SUN8I) 78 sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUN8I_GPF_UART0); 79 sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUN8I_GPF_UART0); 80 #else 81 sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUNXI_GPF_UART0); 82 sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF_UART0); 83 #endif 84 sunxi_gpio_set_pull(SUNXI_GPF(4), 1); 85 #elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)) 86 sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB_UART0); 87 sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB_UART0); 88 sunxi_gpio_set_pull(SUNXI_GPB(23), SUNXI_GPIO_PULL_UP); 89 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN5I) 90 sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB_UART0); 91 sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB_UART0); 92 sunxi_gpio_set_pull(SUNXI_GPB(20), SUNXI_GPIO_PULL_UP); 93 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN6I) 94 sunxi_gpio_set_cfgpin(SUNXI_GPH(20), SUN6I_GPH_UART0); 95 sunxi_gpio_set_cfgpin(SUNXI_GPH(21), SUN6I_GPH_UART0); 96 sunxi_gpio_set_pull(SUNXI_GPH(21), SUNXI_GPIO_PULL_UP); 97 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A33) 98 sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_A33_GPB_UART0); 99 sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_A33_GPB_UART0); 100 sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP); 101 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUNXI_H3_H5) 102 sunxi_gpio_set_cfgpin(SUNXI_GPA(4), SUN8I_H3_GPA_UART0); 103 sunxi_gpio_set_cfgpin(SUNXI_GPA(5), SUN8I_H3_GPA_UART0); 104 sunxi_gpio_set_pull(SUNXI_GPA(5), SUNXI_GPIO_PULL_UP); 105 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN50I) 106 sunxi_gpio_set_cfgpin(SUNXI_GPB(8), SUN50I_GPB_UART0); 107 sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN50I_GPB_UART0); 108 sunxi_gpio_set_pull(SUNXI_GPB(9), SUNXI_GPIO_PULL_UP); 109 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A83T) 110 sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_A83T_GPB_UART0); 111 sunxi_gpio_set_cfgpin(SUNXI_GPB(10), SUN8I_A83T_GPB_UART0); 112 sunxi_gpio_set_pull(SUNXI_GPB(10), SUNXI_GPIO_PULL_UP); 113 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN9I) 114 sunxi_gpio_set_cfgpin(SUNXI_GPH(12), SUN9I_GPH_UART0); 115 sunxi_gpio_set_cfgpin(SUNXI_GPH(13), SUN9I_GPH_UART0); 116 sunxi_gpio_set_pull(SUNXI_GPH(13), SUNXI_GPIO_PULL_UP); 117 #elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I) 118 sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG_UART1); 119 sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG_UART1); 120 sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP); 121 #elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I) 122 sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_GPB_UART2); 123 sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_GPB_UART2); 124 sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP); 125 #elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I) 126 sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL_R_UART); 127 sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL_R_UART); 128 sunxi_gpio_set_pull(SUNXI_GPL(3), SUNXI_GPIO_PULL_UP); 129 #else 130 #error Unsupported console port number. Please fix pin mux settings in board.c 131 #endif 132 133 return 0; 134 } 135 136 #if defined(CONFIG_SPL_BOARD_LOAD_IMAGE) && defined(CONFIG_SPL_BUILD) 137 static int spl_board_load_image(struct spl_image_info *spl_image, 138 struct spl_boot_device *bootdev) 139 { 140 debug("Returning to FEL sp=%x, lr=%x\n", fel_stash.sp, fel_stash.lr); 141 return_to_fel(fel_stash.sp, fel_stash.lr); 142 143 return 0; 144 } 145 SPL_LOAD_IMAGE_METHOD("FEL", 0, BOOT_DEVICE_BOARD, spl_board_load_image); 146 #endif 147 148 void s_init(void) 149 { 150 /* 151 * Undocumented magic taken from boot0, without this DRAM 152 * access gets messed up (seems cache related). 153 * The boot0 sources describe this as: "config ema for cache sram" 154 */ 155 #if defined CONFIG_MACH_SUN6I 156 setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800); 157 #elif defined CONFIG_MACH_SUN8I 158 __maybe_unused uint version; 159 160 /* Unlock sram version info reg, read it, relock */ 161 setbits_le32(SUNXI_SRAMC_BASE + 0x24, (1 << 15)); 162 version = readl(SUNXI_SRAMC_BASE + 0x24) >> 16; 163 clrbits_le32(SUNXI_SRAMC_BASE + 0x24, (1 << 15)); 164 165 /* 166 * Ideally this would be a switch case, but we do not know exactly 167 * which versions there are and which version needs which settings, 168 * so reproduce the per SoC code from the BSP. 169 */ 170 #if defined CONFIG_MACH_SUN8I_A23 171 if (version == 0x1650) 172 setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800); 173 else /* 0x1661 ? */ 174 setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0xc0); 175 #elif defined CONFIG_MACH_SUN8I_A33 176 if (version != 0x1667) 177 setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0xc0); 178 #endif 179 /* A83T BSP never modifies SUNXI_SRAMC_BASE + 0x44 */ 180 /* No H3 BSP, boot0 seems to not modify SUNXI_SRAMC_BASE + 0x44 */ 181 #endif 182 183 #if !defined(CONFIG_ARM_CORTEX_CPU_IS_UP) && !defined(CONFIG_ARM64) 184 /* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */ 185 asm volatile( 186 "mrc p15, 0, r0, c1, c0, 1\n" 187 "orr r0, r0, #1 << 6\n" 188 "mcr p15, 0, r0, c1, c0, 1\n" 189 ::: "r0"); 190 #endif 191 #if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I_H3 192 /* Enable non-secure access to some peripherals */ 193 tzpc_init(); 194 #endif 195 196 clock_init(); 197 timer_init(); 198 gpio_init(); 199 i2c_init_board(); 200 eth_init_board(); 201 } 202 203 #ifdef CONFIG_SPL_BUILD 204 DECLARE_GLOBAL_DATA_PTR; 205 206 /* The sunxi internal brom will try to loader external bootloader 207 * from mmc0, nand flash, mmc2. 208 */ 209 u32 spl_boot_device(void) 210 { 211 int boot_source; 212 213 /* 214 * When booting from the SD card or NAND memory, the "eGON.BT0" 215 * signature is expected to be found in memory at the address 0x0004 216 * (see the "mksunxiboot" tool, which generates this header). 217 * 218 * When booting in the FEL mode over USB, this signature is patched in 219 * memory and replaced with something else by the 'fel' tool. This other 220 * signature is selected in such a way, that it can't be present in a 221 * valid bootable SD card image (because the BROM would refuse to 222 * execute the SPL in this case). 223 * 224 * This checks for the signature and if it is not found returns to 225 * the FEL code in the BROM to wait and receive the main u-boot 226 * binary over USB. If it is found, it determines where SPL was 227 * read from. 228 */ 229 if (!is_boot0_magic(SPL_ADDR + 4)) /* eGON.BT0 */ 230 return BOOT_DEVICE_BOARD; 231 232 boot_source = readb(SPL_ADDR + 0x28); 233 switch (boot_source) { 234 case SUNXI_BOOTED_FROM_MMC0: 235 return BOOT_DEVICE_MMC1; 236 case SUNXI_BOOTED_FROM_NAND: 237 return BOOT_DEVICE_NAND; 238 case SUNXI_BOOTED_FROM_MMC2: 239 return BOOT_DEVICE_MMC2; 240 case SUNXI_BOOTED_FROM_SPI: 241 return BOOT_DEVICE_SPI; 242 } 243 244 panic("Unknown boot source %d\n", boot_source); 245 return -1; /* Never reached */ 246 } 247 248 /* No confirmation data available in SPL yet. Hardcode bootmode */ 249 u32 spl_boot_mode(const u32 boot_device) 250 { 251 return MMCSD_MODE_RAW; 252 } 253 254 void board_init_f(ulong dummy) 255 { 256 spl_init(); 257 preloader_console_init(); 258 259 #ifdef CONFIG_SPL_I2C_SUPPORT 260 /* Needed early by sunxi_board_init if PMU is enabled */ 261 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); 262 #endif 263 sunxi_board_init(); 264 } 265 #endif 266 267 void reset_cpu(ulong addr) 268 { 269 #ifdef CONFIG_SUNXI_GEN_SUN4I 270 static const struct sunxi_wdog *wdog = 271 &((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog; 272 273 /* Set the watchdog for its shortest interval (.5s) and wait */ 274 writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode); 275 writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl); 276 277 while (1) { 278 /* sun5i sometimes gets stuck without this */ 279 writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode); 280 } 281 #endif 282 #ifdef CONFIG_SUNXI_GEN_SUN6I 283 static const struct sunxi_wdog *wdog = 284 ((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog; 285 286 /* Set the watchdog for its shortest interval (.5s) and wait */ 287 writel(WDT_CFG_RESET, &wdog->cfg); 288 writel(WDT_MODE_EN, &wdog->mode); 289 writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl); 290 while (1) { } 291 #endif 292 } 293 294 #if !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_ARM64) 295 void enable_caches(void) 296 { 297 /* Enable D-cache. I-cache is already enabled in start.S */ 298 dcache_enable(); 299 } 300 #endif 301