xref: /openbmc/u-boot/arch/arm/mach-sunxi/Kconfig (revision fbe502e9)
1if ARCH_SUNXI
2
3config SPL_LDSCRIPT
4	default "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" if !ARM64
5
6config IDENT_STRING
7	default " Allwinner Technology"
8
9config DRAM_SUN4I
10	bool
11	help
12	  Select this dram controller driver for Sun4/5/7i platforms,
13	  like A10/A13/A20.
14
15config DRAM_SUN6I
16	bool
17	help
18	  Select this dram controller driver for Sun6i platforms,
19	  like A31/A31s.
20
21config DRAM_SUN8I_A23
22	bool
23	help
24	  Select this dram controller driver for Sun8i platforms,
25	  for A23 SOC.
26
27config DRAM_SUN8I_A33
28	bool
29	help
30	  Select this dram controller driver for Sun8i platforms,
31	  for A33 SOC.
32
33config DRAM_SUN8I_A83T
34	bool
35	help
36	  Select this dram controller driver for Sun8i platforms,
37	  for A83T SOC.
38
39config DRAM_SUN9I
40	bool
41	help
42	  Select this dram controller driver for Sun9i platforms,
43	  like A80.
44
45config SUN6I_P2WI
46	bool "Allwinner sun6i internal P2WI controller"
47	help
48	  If you say yes to this option, support will be included for the
49	  P2WI (Push/Pull 2 Wire Interface) controller embedded in some sunxi
50	  SOCs.
51	  The P2WI looks like an SMBus controller (which supports only byte
52	  accesses), except that it only supports one slave device.
53	  This interface is used to connect to specific PMIC devices (like the
54	  AXP221).
55
56config SUN6I_PRCM
57	bool
58	help
59	  Support for the PRCM (Power/Reset/Clock Management) unit available
60	  in A31 SoC.
61
62config AXP_PMIC_BUS
63	bool "Sunxi AXP PMIC bus access helpers"
64	help
65	  Select this PMIC bus access helpers for Sunxi platform PRCM or other
66	  AXP family PMIC devices.
67
68config SUN8I_RSB
69	bool "Allwinner sunXi Reduced Serial Bus Driver"
70	help
71	  Say y here to enable support for Allwinner's Reduced Serial Bus
72	  (RSB) support. This controller is responsible for communicating
73	  with various RSB based devices, such as AXP223, AXP8XX PMICs,
74	  and AC100/AC200 ICs.
75
76config SUNXI_HIGH_SRAM
77	bool
78	default n
79	---help---
80	Older Allwinner SoCs have their mask boot ROM mapped just below 4GB,
81	with the first SRAM region being located at address 0.
82	Some newer SoCs map the boot ROM at address 0 instead and move the
83	SRAM to 64KB, just behind the mask ROM.
84	Chips using the latter setup are supposed to select this option to
85	adjust the addresses accordingly.
86
87# Note only one of these may be selected at a time! But hidden choices are
88# not supported by Kconfig
89config SUNXI_GEN_SUN4I
90	bool
91	---help---
92	Select this for sunxi SoCs which have resets and clocks set up
93	as the original A10 (mach-sun4i).
94
95config SUNXI_GEN_SUN6I
96	bool
97	---help---
98	Select this for sunxi SoCs which have sun6i like periphery, like
99	separate ahb reset control registers, custom pmic bus, new style
100	watchdog, etc.
101
102config SUNXI_DRAM_DW
103	bool
104	---help---
105	Select this for sunxi SoCs which uses a DRAM controller like the
106	DesignWare controller used in H3, mainly SoCs after H3, which do
107	not have official open-source DRAM initialization code, but can
108	use modified H3 DRAM initialization code.
109
110if SUNXI_DRAM_DW
111config SUNXI_DRAM_DW_16BIT
112	bool
113	---help---
114	Select this for sunxi SoCs with DesignWare DRAM controller and
115	have only 16-bit memory buswidth.
116
117config SUNXI_DRAM_DW_32BIT
118	bool
119	---help---
120	Select this for sunxi SoCs with DesignWare DRAM controller with
121	32-bit memory buswidth.
122endif
123
124config MACH_SUNXI_H3_H5
125	bool
126	select DM_I2C
127	select SUNXI_DE2
128	select SUNXI_DRAM_DW
129	select SUNXI_DRAM_DW_32BIT
130	select SUNXI_GEN_SUN6I
131	select SUPPORT_SPL
132
133choice
134	prompt "Sunxi SoC Variant"
135	optional
136
137config MACH_SUN4I
138	bool "sun4i (Allwinner A10)"
139	select CPU_V7A
140	select ARM_CORTEX_CPU_IS_UP
141	select DRAM_SUN4I
142	select SUNXI_GEN_SUN4I
143	select SUPPORT_SPL
144
145config MACH_SUN5I
146	bool "sun5i (Allwinner A13)"
147	select CPU_V7A
148	select ARM_CORTEX_CPU_IS_UP
149	select DRAM_SUN4I
150	select SUNXI_GEN_SUN4I
151	select SUPPORT_SPL
152	imply CONS_INDEX_2 if !DM_SERIAL
153
154config MACH_SUN6I
155	bool "sun6i (Allwinner A31)"
156	select CPU_V7A
157	select CPU_V7_HAS_NONSEC
158	select CPU_V7_HAS_VIRT
159	select ARCH_SUPPORT_PSCI
160	select DRAM_SUN6I
161	select SUN6I_P2WI
162	select SUN6I_PRCM
163	select SUNXI_GEN_SUN6I
164	select SUPPORT_SPL
165	select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
166
167config MACH_SUN7I
168	bool "sun7i (Allwinner A20)"
169	select CPU_V7A
170	select CPU_V7_HAS_NONSEC
171	select CPU_V7_HAS_VIRT
172	select ARCH_SUPPORT_PSCI
173	select DRAM_SUN4I
174	select SUNXI_GEN_SUN4I
175	select SUPPORT_SPL
176	select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
177
178config MACH_SUN8I_A23
179	bool "sun8i (Allwinner A23)"
180	select CPU_V7A
181	select CPU_V7_HAS_NONSEC
182	select CPU_V7_HAS_VIRT
183	select ARCH_SUPPORT_PSCI
184	select DRAM_SUN8I_A23
185	select SUNXI_GEN_SUN6I
186	select SUPPORT_SPL
187	select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
188	imply CONS_INDEX_5 if !DM_SERIAL
189
190config MACH_SUN8I_A33
191	bool "sun8i (Allwinner A33)"
192	select CPU_V7A
193	select CPU_V7_HAS_NONSEC
194	select CPU_V7_HAS_VIRT
195	select ARCH_SUPPORT_PSCI
196	select DRAM_SUN8I_A33
197	select SUNXI_GEN_SUN6I
198	select SUPPORT_SPL
199	select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
200	imply CONS_INDEX_5 if !DM_SERIAL
201
202config MACH_SUN8I_A83T
203	bool "sun8i (Allwinner A83T)"
204	select CPU_V7A
205	select DRAM_SUN8I_A83T
206	select SUNXI_GEN_SUN6I
207	select MMC_SUNXI_HAS_NEW_MODE
208	select SUPPORT_SPL
209
210config MACH_SUN8I_H3
211	bool "sun8i (Allwinner H3)"
212	select CPU_V7A
213	select CPU_V7_HAS_NONSEC
214	select CPU_V7_HAS_VIRT
215	select ARCH_SUPPORT_PSCI
216	select MACH_SUNXI_H3_H5
217	select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
218
219config MACH_SUN8I_R40
220	bool "sun8i (Allwinner R40)"
221	select CPU_V7A
222	select CPU_V7_HAS_NONSEC
223	select CPU_V7_HAS_VIRT
224	select ARCH_SUPPORT_PSCI
225	select SUNXI_GEN_SUN6I
226	select SUPPORT_SPL
227	select SUNXI_DRAM_DW
228	select SUNXI_DRAM_DW_32BIT
229
230config MACH_SUN8I_V3S
231	bool "sun8i (Allwinner V3s)"
232	select CPU_V7A
233	select CPU_V7_HAS_NONSEC
234	select CPU_V7_HAS_VIRT
235	select ARCH_SUPPORT_PSCI
236	select SUNXI_GEN_SUN6I
237	select SUNXI_DRAM_DW
238	select SUNXI_DRAM_DW_16BIT
239	select SUPPORT_SPL
240	select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
241
242config MACH_SUN9I
243	bool "sun9i (Allwinner A80)"
244	select CPU_V7A
245	select DRAM_SUN9I
246	select SUN6I_PRCM
247	select SUNXI_HIGH_SRAM
248	select SUNXI_GEN_SUN6I
249	select SUN8I_RSB
250	select SUPPORT_SPL
251
252config MACH_SUN50I
253	bool "sun50i (Allwinner A64)"
254	select ARM64
255	select DM_I2C
256	select SUNXI_DE2
257	select SUNXI_GEN_SUN6I
258	select SUNXI_HIGH_SRAM
259	select SUPPORT_SPL
260	select SUNXI_DRAM_DW
261	select SUNXI_DRAM_DW_32BIT
262	select FIT
263	select SPL_LOAD_FIT
264
265config MACH_SUN50I_H5
266	bool "sun50i (Allwinner H5)"
267	select ARM64
268	select MACH_SUNXI_H3_H5
269	select SUNXI_HIGH_SRAM
270	select FIT
271	select SPL_LOAD_FIT
272
273endchoice
274
275# The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
276config MACH_SUN8I
277	bool
278	select SUN8I_RSB
279	select SUN6I_PRCM
280	default y if MACH_SUN8I_A23
281	default y if MACH_SUN8I_A33
282	default y if MACH_SUN8I_A83T
283	default y if MACH_SUNXI_H3_H5
284	default y if MACH_SUN8I_R40
285	default y if MACH_SUN8I_V3S
286
287config RESERVE_ALLWINNER_BOOT0_HEADER
288	bool "reserve space for Allwinner boot0 header"
289	select ENABLE_ARM_SOC_BOOT0_HOOK
290	---help---
291	Prepend a 1536 byte (empty) header to the U-Boot image file, to be
292	filled with magic values post build. The Allwinner provided boot0
293	blob relies on this information to load and execute U-Boot.
294	Only needed on 64-bit Allwinner boards so far when using boot0.
295
296config ARM_BOOT_HOOK_RMR
297	bool
298	depends on ARM64
299	default y
300	select ENABLE_ARM_SOC_BOOT0_HOOK
301	---help---
302	Insert some ARM32 code at the very beginning of the U-Boot binary
303	which uses an RMR register write to bring the core into AArch64 mode.
304	The very first instruction acts as a switch, since it's carefully
305	chosen to be a NOP in one mode and a branch in the other, so the
306	code would only be executed if not already in AArch64.
307	This allows both the SPL and the U-Boot proper to be entered in
308	either mode and switch to AArch64 if needed.
309
310if SUNXI_DRAM_DW
311config SUNXI_DRAM_DDR3
312	bool
313
314config SUNXI_DRAM_DDR2
315	bool
316
317config SUNXI_DRAM_LPDDR3
318	bool
319
320choice
321	prompt "DRAM Type and Timing"
322	default SUNXI_DRAM_DDR3_1333 if !MACH_SUN8I_V3S
323	default SUNXI_DRAM_DDR2_V3S if MACH_SUN8I_V3S
324
325config SUNXI_DRAM_DDR3_1333
326	bool "DDR3 1333"
327	select SUNXI_DRAM_DDR3
328	depends on !MACH_SUN8I_V3S
329	---help---
330	This option is the original only supported memory type, which suits
331	many H3/H5/A64 boards available now.
332
333config SUNXI_DRAM_LPDDR3_STOCK
334	bool "LPDDR3 with Allwinner stock configuration"
335	select SUNXI_DRAM_LPDDR3
336	---help---
337	This option is the LPDDR3 timing used by the stock boot0 by
338	Allwinner.
339
340config SUNXI_DRAM_DDR2_V3S
341	bool "DDR2 found in V3s chip"
342	select SUNXI_DRAM_DDR2
343	depends on MACH_SUN8I_V3S
344	---help---
345	This option is only for the DDR2 memory chip which is co-packaged in
346	Allwinner V3s SoC.
347
348endchoice
349endif
350
351config DRAM_TYPE
352	int "sunxi dram type"
353	depends on MACH_SUN8I_A83T
354	default 3
355	---help---
356	Set the dram type, 3: DDR3, 7: LPDDR3
357
358config DRAM_CLK
359	int "sunxi dram clock speed"
360	default 792 if MACH_SUN9I
361	default 648 if MACH_SUN8I_R40
362	default 312 if MACH_SUN6I || MACH_SUN8I
363	default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || \
364		       MACH_SUN8I_V3S
365	default 672 if MACH_SUN50I
366	---help---
367	Set the dram clock speed, valid range 240 - 480 (prior to sun9i),
368	must be a multiple of 24. For the sun9i (A80), the tested values
369	(for DDR3-1600) are 312 to 792.
370
371if MACH_SUN5I || MACH_SUN7I
372config DRAM_MBUS_CLK
373	int "sunxi mbus clock speed"
374	default 300
375	---help---
376	Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
377
378endif
379
380config DRAM_ZQ
381	int "sunxi dram zq value"
382	default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
383	default 127 if MACH_SUN7I
384	default 14779 if MACH_SUN8I_V3S
385	default 3881979 if MACH_SUN8I_R40
386	default 4145117 if MACH_SUN9I
387	default 3881915 if MACH_SUN50I
388	---help---
389	Set the dram zq value.
390
391config DRAM_ODT_EN
392	bool "sunxi dram odt enable"
393	default n if !MACH_SUN8I_A23
394	default y if MACH_SUN8I_A23
395	default y if MACH_SUN8I_R40
396	default y if MACH_SUN50I
397	---help---
398	Select this to enable dram odt (on die termination).
399
400if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
401config DRAM_EMR1
402	int "sunxi dram emr1 value"
403	default 0 if MACH_SUN4I
404	default 4 if MACH_SUN5I || MACH_SUN7I
405	---help---
406	Set the dram controller emr1 value.
407
408config DRAM_TPR3
409	hex "sunxi dram tpr3 value"
410	default 0
411	---help---
412	Set the dram controller tpr3 parameter. This parameter configures
413	the delay on the command lane and also phase shifts, which are
414	applied for sampling incoming read data. The default value 0
415	means that no phase/delay adjustments are necessary. Properly
416	configuring this parameter increases reliability at high DRAM
417	clock speeds.
418
419config DRAM_DQS_GATING_DELAY
420	hex "sunxi dram dqs_gating_delay value"
421	default 0
422	---help---
423	Set the dram controller dqs_gating_delay parmeter. Each byte
424	encodes the DQS gating delay for each byte lane. The delay
425	granularity is 1/4 cycle. For example, the value 0x05060606
426	means that the delay is 5 quarter-cycles for one lane (1.25
427	cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
428	The default value 0 means autodetection. The results of hardware
429	autodetection are not very reliable and depend on the chip
430	temperature (sometimes producing different results on cold start
431	and warm reboot). But the accuracy of hardware autodetection
432	is usually good enough, unless running at really high DRAM
433	clocks speeds (up to 600MHz). If unsure, keep as 0.
434
435choice
436	prompt "sunxi dram timings"
437	default DRAM_TIMINGS_VENDOR_MAGIC
438	---help---
439	Select the timings of the DDR3 chips.
440
441config DRAM_TIMINGS_VENDOR_MAGIC
442	bool "Magic vendor timings from Android"
443	---help---
444	The same DRAM timings as in the Allwinner boot0 bootloader.
445
446config DRAM_TIMINGS_DDR3_1066F_1333H
447	bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
448	---help---
449	Use the timings of the standard JEDEC DDR3-1066F speed bin for
450	DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
451	for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
452	used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
453	or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
454	that down binning to DDR3-1066F is supported (because DDR3-1066F
455	uses a bit faster timings than DDR3-1333H).
456
457config DRAM_TIMINGS_DDR3_800E_1066G_1333J
458	bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
459	---help---
460	Use the timings of the slowest possible JEDEC speed bin for the
461	selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
462	DDR3-800E, DDR3-1066G or DDR3-1333J.
463
464endchoice
465
466endif
467
468if MACH_SUN8I_A23
469config DRAM_ODT_CORRECTION
470	int "sunxi dram odt correction value"
471	default 0
472	---help---
473	Set the dram odt correction value (range -255 - 255). In allwinner
474	fex files, this option is found in bits 8-15 of the u32 odt_en variable
475	in the [dram] section. When bit 31 of the odt_en variable is set
476	then the correction is negative. Usually the value for this is 0.
477endif
478
479config SYS_CLK_FREQ
480	default 1008000000 if MACH_SUN4I
481	default 1008000000 if MACH_SUN5I
482	default 1008000000 if MACH_SUN6I
483	default 912000000 if MACH_SUN7I
484	default 816000000 if MACH_SUN50I || MACH_SUN50I_H5
485	default 1008000000 if MACH_SUN8I
486	default 1008000000 if MACH_SUN9I
487
488config SYS_CONFIG_NAME
489	default "sun4i" if MACH_SUN4I
490	default "sun5i" if MACH_SUN5I
491	default "sun6i" if MACH_SUN6I
492	default "sun7i" if MACH_SUN7I
493	default "sun8i" if MACH_SUN8I
494	default "sun9i" if MACH_SUN9I
495	default "sun50i" if MACH_SUN50I
496
497config SYS_BOARD
498	default "sunxi"
499
500config SYS_SOC
501	default "sunxi"
502
503config UART0_PORT_F
504	bool "UART0 on MicroSD breakout board"
505	default n
506	---help---
507	Repurpose the SD card slot for getting access to the UART0 serial
508	console. Primarily useful only for low level u-boot debugging on
509	tablets, where normal UART0 is difficult to access and requires
510	device disassembly and/or soldering. As the SD card can't be used
511	at the same time, the system can be only booted in the FEL mode.
512	Only enable this if you really know what you are doing.
513
514config OLD_SUNXI_KERNEL_COMPAT
515	bool "Enable workarounds for booting old kernels"
516	default n
517	---help---
518	Set this to enable various workarounds for old kernels, this results in
519	sub-optimal settings for newer kernels, only enable if needed.
520
521config MACPWR
522	string "MAC power pin"
523	default ""
524	help
525	  Set the pin used to power the MAC. This takes a string in the format
526	  understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
527
528config MMC0_CD_PIN
529	string "Card detect pin for mmc0"
530	default "PF6" if MACH_SUN8I_A83T || MACH_SUNXI_H3_H5 || MACH_SUN50I
531	default ""
532	---help---
533	Set the card detect pin for mmc0, leave empty to not use cd. This
534	takes a string in the format understood by sunxi_name_to_gpio, e.g.
535	PH1 for pin 1 of port H.
536
537config MMC1_CD_PIN
538	string "Card detect pin for mmc1"
539	default ""
540	---help---
541	See MMC0_CD_PIN help text.
542
543config MMC2_CD_PIN
544	string "Card detect pin for mmc2"
545	default ""
546	---help---
547	See MMC0_CD_PIN help text.
548
549config MMC3_CD_PIN
550	string "Card detect pin for mmc3"
551	default ""
552	---help---
553	See MMC0_CD_PIN help text.
554
555config MMC1_PINS
556	string "Pins for mmc1"
557	default ""
558	---help---
559	Set the pins used for mmc1, when applicable. This takes a string in the
560	format understood by sunxi_name_to_gpio_bank, e.g. PH for port H.
561
562config MMC2_PINS
563	string "Pins for mmc2"
564	default ""
565	---help---
566	See MMC1_PINS help text.
567
568config MMC3_PINS
569	string "Pins for mmc3"
570	default ""
571	---help---
572	See MMC1_PINS help text.
573
574config MMC_SUNXI_SLOT_EXTRA
575	int "mmc extra slot number"
576	default -1
577	---help---
578	sunxi builds always enable mmc0, some boards also have a second sdcard
579	slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
580	support for this.
581
582config INITIAL_USB_SCAN_DELAY
583	int "delay initial usb scan by x ms to allow builtin devices to init"
584	default 0
585	---help---
586	Some boards have on board usb devices which need longer than the
587	USB spec's 1 second to connect from board powerup. Set this config
588	option to a non 0 value to add an extra delay before the first usb
589	bus scan.
590
591config USB0_VBUS_PIN
592	string "Vbus enable pin for usb0 (otg)"
593	default ""
594	---help---
595	Set the Vbus enable pin for usb0 (otg). This takes a string in the
596	format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
597
598config USB0_VBUS_DET
599	string "Vbus detect pin for usb0 (otg)"
600	default ""
601	---help---
602	Set the Vbus detect pin for usb0 (otg). This takes a string in the
603	format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
604
605config USB0_ID_DET
606	string "ID detect pin for usb0 (otg)"
607	default ""
608	---help---
609	Set the ID detect pin for usb0 (otg). This takes a string in the
610	format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
611
612config USB1_VBUS_PIN
613	string "Vbus enable pin for usb1 (ehci0)"
614	default "PH6" if MACH_SUN4I || MACH_SUN7I
615	default "PH27" if MACH_SUN6I
616	---help---
617	Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
618	a string in the format understood by sunxi_name_to_gpio, e.g.
619	PH1 for pin 1 of port H.
620
621config USB2_VBUS_PIN
622	string "Vbus enable pin for usb2 (ehci1)"
623	default "PH3" if MACH_SUN4I || MACH_SUN7I
624	default "PH24" if MACH_SUN6I
625	---help---
626	See USB1_VBUS_PIN help text.
627
628config USB3_VBUS_PIN
629	string "Vbus enable pin for usb3 (ehci2)"
630	default ""
631	---help---
632	See USB1_VBUS_PIN help text.
633
634config I2C0_ENABLE
635	bool "Enable I2C/TWI controller 0"
636	default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_R40
637	default n if MACH_SUN6I || MACH_SUN8I
638	select CMD_I2C
639	---help---
640	This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
641	its clock and setting up the bus. This is especially useful on devices
642	with slaves connected to the bus or with pins exposed through e.g. an
643	expansion port/header.
644
645config I2C1_ENABLE
646	bool "Enable I2C/TWI controller 1"
647	default n
648	select CMD_I2C
649	---help---
650	See I2C0_ENABLE help text.
651
652config I2C2_ENABLE
653	bool "Enable I2C/TWI controller 2"
654	default n
655	select CMD_I2C
656	---help---
657	See I2C0_ENABLE help text.
658
659if MACH_SUN6I || MACH_SUN7I
660config I2C3_ENABLE
661	bool "Enable I2C/TWI controller 3"
662	default n
663	select CMD_I2C
664	---help---
665	See I2C0_ENABLE help text.
666endif
667
668if SUNXI_GEN_SUN6I
669config R_I2C_ENABLE
670	bool "Enable the PRCM I2C/TWI controller"
671	# This is used for the pmic on H3
672	default y if SY8106A_POWER
673	select CMD_I2C
674	---help---
675	Set this to y to enable the I2C controller which is part of the PRCM.
676endif
677
678if MACH_SUN7I
679config I2C4_ENABLE
680	bool "Enable I2C/TWI controller 4"
681	default n
682	select CMD_I2C
683	---help---
684	See I2C0_ENABLE help text.
685endif
686
687config AXP_GPIO
688	bool "Enable support for gpio-s on axp PMICs"
689	default n
690	---help---
691	Say Y here to enable support for the gpio pins of the axp PMIC ICs.
692
693config VIDEO_SUNXI
694	bool "Enable graphical uboot console on HDMI, LCD or VGA"
695	depends on !MACH_SUN8I_A83T
696	depends on !MACH_SUNXI_H3_H5
697	depends on !MACH_SUN8I_R40
698	depends on !MACH_SUN8I_V3S
699	depends on !MACH_SUN9I
700	depends on !MACH_SUN50I
701	select VIDEO
702	imply VIDEO_DT_SIMPLEFB
703	default y
704	---help---
705	Say Y here to add support for using a cfb console on the HDMI, LCD
706	or VGA output found on most sunxi devices. See doc/README.video for
707	info on how to select the video output and mode.
708
709config VIDEO_HDMI
710	bool "HDMI output support"
711	depends on VIDEO_SUNXI && !MACH_SUN8I
712	default y
713	---help---
714	Say Y here to add support for outputting video over HDMI.
715
716config VIDEO_VGA
717	bool "VGA output support"
718	depends on VIDEO_SUNXI && (MACH_SUN4I || MACH_SUN7I)
719	default n
720	---help---
721	Say Y here to add support for outputting video over VGA.
722
723config VIDEO_VGA_VIA_LCD
724	bool "VGA via LCD controller support"
725	depends on VIDEO_SUNXI && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
726	default n
727	---help---
728	Say Y here to add support for external DACs connected to the parallel
729	LCD interface driving a VGA connector, such as found on the
730	Olimex A13 boards.
731
732config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
733	bool "Force sync active high for VGA via LCD controller support"
734	depends on VIDEO_VGA_VIA_LCD
735	default n
736	---help---
737	Say Y here if you've a board which uses opendrain drivers for the vga
738	hsync and vsync signals. Opendrain drivers cannot generate steep enough
739	positive edges for a stable video output, so on boards with opendrain
740	drivers the sync signals must always be active high.
741
742config VIDEO_VGA_EXTERNAL_DAC_EN
743	string "LCD panel power enable pin"
744	depends on VIDEO_VGA_VIA_LCD
745	default ""
746	---help---
747	Set the enable pin for the external VGA DAC. This takes a string in the
748	format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
749
750config VIDEO_COMPOSITE
751	bool "Composite video output support"
752	depends on VIDEO_SUNXI && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
753	default n
754	---help---
755	Say Y here to add support for outputting composite video.
756
757config VIDEO_LCD_MODE
758	string "LCD panel timing details"
759	depends on VIDEO_SUNXI
760	default ""
761	---help---
762	LCD panel timing details string, leave empty if there is no LCD panel.
763	This is in drivers/video/videomodes.c: video_get_params() format, e.g.
764	x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
765	Also see: http://linux-sunxi.org/LCD
766
767config VIDEO_LCD_DCLK_PHASE
768	int "LCD panel display clock phase"
769	depends on VIDEO_SUNXI || DM_VIDEO
770	default 1
771	---help---
772	Select LCD panel display clock phase shift, range 0-3.
773
774config VIDEO_LCD_POWER
775	string "LCD panel power enable pin"
776	depends on VIDEO_SUNXI
777	default ""
778	---help---
779	Set the power enable pin for the LCD panel. This takes a string in the
780	format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
781
782config VIDEO_LCD_RESET
783	string "LCD panel reset pin"
784	depends on VIDEO_SUNXI
785	default ""
786	---help---
787	Set the reset pin for the LCD panel. This takes a string in the format
788	understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
789
790config VIDEO_LCD_BL_EN
791	string "LCD panel backlight enable pin"
792	depends on VIDEO_SUNXI
793	default ""
794	---help---
795	Set the backlight enable pin for the LCD panel. This takes a string in the
796	the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
797	port H.
798
799config VIDEO_LCD_BL_PWM
800	string "LCD panel backlight pwm pin"
801	depends on VIDEO_SUNXI
802	default ""
803	---help---
804	Set the backlight pwm pin for the LCD panel. This takes a string in the
805	format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
806
807config VIDEO_LCD_BL_PWM_ACTIVE_LOW
808	bool "LCD panel backlight pwm is inverted"
809	depends on VIDEO_SUNXI
810	default y
811	---help---
812	Set this if the backlight pwm output is active low.
813
814config VIDEO_LCD_PANEL_I2C
815	bool "LCD panel needs to be configured via i2c"
816	depends on VIDEO_SUNXI
817	default n
818	select CMD_I2C
819	---help---
820	Say y here if the LCD panel needs to be configured via i2c. This
821	will add a bitbang i2c controller using gpios to talk to the LCD.
822
823config VIDEO_LCD_PANEL_I2C_SDA
824	string "LCD panel i2c interface SDA pin"
825	depends on VIDEO_LCD_PANEL_I2C
826	default "PG12"
827	---help---
828	Set the SDA pin for the LCD i2c interface. This takes a string in the
829	format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
830
831config VIDEO_LCD_PANEL_I2C_SCL
832	string "LCD panel i2c interface SCL pin"
833	depends on VIDEO_LCD_PANEL_I2C
834	default "PG10"
835	---help---
836	Set the SCL pin for the LCD i2c interface. This takes a string in the
837	format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
838
839
840# Note only one of these may be selected at a time! But hidden choices are
841# not supported by Kconfig
842config VIDEO_LCD_IF_PARALLEL
843	bool
844
845config VIDEO_LCD_IF_LVDS
846	bool
847
848config SUNXI_DE2
849	bool
850	default n
851
852config VIDEO_DE2
853	bool "Display Engine 2 video driver"
854	depends on SUNXI_DE2
855	select DM_VIDEO
856	select DISPLAY
857	imply VIDEO_DT_SIMPLEFB
858	default y
859	---help---
860	Say y here if you want to build DE2 video driver which is present on
861	newer SoCs. Currently only HDMI output is supported.
862
863
864choice
865	prompt "LCD panel support"
866	depends on VIDEO_SUNXI
867	---help---
868	Select which type of LCD panel to support.
869
870config VIDEO_LCD_PANEL_PARALLEL
871	bool "Generic parallel interface LCD panel"
872	select VIDEO_LCD_IF_PARALLEL
873
874config VIDEO_LCD_PANEL_LVDS
875	bool "Generic lvds interface LCD panel"
876	select VIDEO_LCD_IF_LVDS
877
878config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
879	bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
880	select VIDEO_LCD_SSD2828
881	select VIDEO_LCD_IF_PARALLEL
882	---help---
883	7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
884
885config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
886	bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip"
887	select VIDEO_LCD_ANX9804
888	select VIDEO_LCD_IF_PARALLEL
889	select VIDEO_LCD_PANEL_I2C
890	---help---
891	Select this for eDP LCD panels with 4 lanes running at 1.62G,
892	connected via an ANX9804 bridge chip.
893
894config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
895	bool "Hitachi tx18d42vm LCD panel"
896	select VIDEO_LCD_HITACHI_TX18D42VM
897	select VIDEO_LCD_IF_LVDS
898	---help---
899	7.85" 1024x768 Hitachi tx18d42vm LCD panel support
900
901config VIDEO_LCD_TL059WV5C0
902	bool "tl059wv5c0 LCD panel"
903	select VIDEO_LCD_PANEL_I2C
904	select VIDEO_LCD_IF_PARALLEL
905	---help---
906	6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and
907	Aigo M60/M608/M606 tablets.
908
909endchoice
910
911config SATAPWR
912	string "SATA power pin"
913	default ""
914	help
915	  Set the pins used to power the SATA. This takes a string in the
916	  format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
917	  port H.
918
919config GMAC_TX_DELAY
920	int "GMAC Transmit Clock Delay Chain"
921	default 0
922	---help---
923	Set the GMAC Transmit Clock Delay Chain value.
924
925config SPL_STACK_R_ADDR
926	default 0x4fe00000 if MACH_SUN4I
927	default 0x4fe00000 if MACH_SUN5I
928	default 0x4fe00000 if MACH_SUN6I
929	default 0x4fe00000 if MACH_SUN7I
930	default 0x4fe00000 if MACH_SUN8I
931	default 0x2fe00000 if MACH_SUN9I
932	default 0x4fe00000 if MACH_SUN50I
933
934config SPL_SPI_SUNXI
935	bool "Support for SPI Flash on Allwinner SoCs in SPL"
936	depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I
937	help
938	  Enable support for SPI Flash. This option allows SPL to read from
939	  sunxi SPI Flash. It uses the same method as the boot ROM, so does
940	  not need any extra configuration.
941
942endif
943