xref: /openbmc/u-boot/arch/arm/mach-sunxi/Kconfig (revision f7ce2d6e)
1if ARCH_SUNXI
2
3config SPL_LDSCRIPT
4	default "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" if !ARM64
5
6config IDENT_STRING
7	default " Allwinner Technology"
8
9config DRAM_SUN4I
10	bool
11	help
12	  Select this dram controller driver for Sun4/5/7i platforms,
13	  like A10/A13/A20.
14
15config DRAM_SUN6I
16	bool
17	help
18	  Select this dram controller driver for Sun6i platforms,
19	  like A31/A31s.
20
21config DRAM_SUN8I_A23
22	bool
23	help
24	  Select this dram controller driver for Sun8i platforms,
25	  for A23 SOC.
26
27config DRAM_SUN8I_A33
28	bool
29	help
30	  Select this dram controller driver for Sun8i platforms,
31	  for A33 SOC.
32
33config DRAM_SUN8I_A83T
34	bool
35	help
36	  Select this dram controller driver for Sun8i platforms,
37	  for A83T SOC.
38
39config DRAM_SUN9I
40	bool
41	help
42	  Select this dram controller driver for Sun9i platforms,
43	  like A80.
44
45config DRAM_SUN50I_H6
46	bool
47	help
48	  Select this dram controller driver for some sun50i platforms,
49	  like H6.
50
51config SUN6I_P2WI
52	bool "Allwinner sun6i internal P2WI controller"
53	help
54	  If you say yes to this option, support will be included for the
55	  P2WI (Push/Pull 2 Wire Interface) controller embedded in some sunxi
56	  SOCs.
57	  The P2WI looks like an SMBus controller (which supports only byte
58	  accesses), except that it only supports one slave device.
59	  This interface is used to connect to specific PMIC devices (like the
60	  AXP221).
61
62config SUN6I_PRCM
63	bool
64	help
65	  Support for the PRCM (Power/Reset/Clock Management) unit available
66	  in A31 SoC.
67
68config AXP_PMIC_BUS
69	bool "Sunxi AXP PMIC bus access helpers"
70	help
71	  Select this PMIC bus access helpers for Sunxi platform PRCM or other
72	  AXP family PMIC devices.
73
74config SUN8I_RSB
75	bool "Allwinner sunXi Reduced Serial Bus Driver"
76	help
77	  Say y here to enable support for Allwinner's Reduced Serial Bus
78	  (RSB) support. This controller is responsible for communicating
79	  with various RSB based devices, such as AXP223, AXP8XX PMICs,
80	  and AC100/AC200 ICs.
81
82config SUNXI_SRAM_ADDRESS
83	hex
84	default 0x10000 if MACH_SUN9I || MACH_SUN50I || MACH_SUN50I_H5
85	default 0x20000 if MACH_SUN50I_H6
86	default 0x0
87	---help---
88	Older Allwinner SoCs have their mask boot ROM mapped just below 4GB,
89	with the first SRAM region being located at address 0.
90	Some newer SoCs map the boot ROM at address 0 instead and move the
91	SRAM to a different address.
92
93config SUNXI_A64_TIMER_ERRATUM
94	bool
95
96# Note only one of these may be selected at a time! But hidden choices are
97# not supported by Kconfig
98config SUNXI_GEN_SUN4I
99	bool
100	---help---
101	Select this for sunxi SoCs which have resets and clocks set up
102	as the original A10 (mach-sun4i).
103
104config SUNXI_GEN_SUN6I
105	bool
106	---help---
107	Select this for sunxi SoCs which have sun6i like periphery, like
108	separate ahb reset control registers, custom pmic bus, new style
109	watchdog, etc.
110
111config SUNXI_DRAM_DW
112	bool
113	---help---
114	Select this for sunxi SoCs which uses a DRAM controller like the
115	DesignWare controller used in H3, mainly SoCs after H3, which do
116	not have official open-source DRAM initialization code, but can
117	use modified H3 DRAM initialization code.
118
119if SUNXI_DRAM_DW
120config SUNXI_DRAM_DW_16BIT
121	bool
122	---help---
123	Select this for sunxi SoCs with DesignWare DRAM controller and
124	have only 16-bit memory buswidth.
125
126config SUNXI_DRAM_DW_32BIT
127	bool
128	---help---
129	Select this for sunxi SoCs with DesignWare DRAM controller with
130	32-bit memory buswidth.
131endif
132
133config MACH_SUNXI_H3_H5
134	bool
135	select DM_I2C
136	select PHY_SUN4I_USB
137	select SUNXI_DE2
138	select SUNXI_DRAM_DW
139	select SUNXI_DRAM_DW_32BIT
140	select SUNXI_GEN_SUN6I
141	select SUPPORT_SPL
142
143choice
144	prompt "Sunxi SoC Variant"
145	optional
146
147config MACH_SUN4I
148	bool "sun4i (Allwinner A10)"
149	select CPU_V7A
150	select ARM_CORTEX_CPU_IS_UP
151	select DM_MMC if MMC
152	select DM_SCSI if SCSI
153	select PHY_SUN4I_USB
154	select DRAM_SUN4I
155	select SUNXI_GEN_SUN4I
156	select SUPPORT_SPL
157
158config MACH_SUN5I
159	bool "sun5i (Allwinner A13)"
160	select CPU_V7A
161	select ARM_CORTEX_CPU_IS_UP
162	select DRAM_SUN4I
163	select PHY_SUN4I_USB
164	select SUNXI_GEN_SUN4I
165	select SUPPORT_SPL
166	imply CONS_INDEX_2 if !DM_SERIAL
167
168config MACH_SUN6I
169	bool "sun6i (Allwinner A31)"
170	select CPU_V7A
171	select CPU_V7_HAS_NONSEC
172	select CPU_V7_HAS_VIRT
173	select ARCH_SUPPORT_PSCI
174	select DRAM_SUN6I
175	select PHY_SUN4I_USB
176	select SUN6I_P2WI
177	select SUN6I_PRCM
178	select SUNXI_GEN_SUN6I
179	select SUPPORT_SPL
180	select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
181
182config MACH_SUN7I
183	bool "sun7i (Allwinner A20)"
184	select CPU_V7A
185	select CPU_V7_HAS_NONSEC
186	select CPU_V7_HAS_VIRT
187	select ARCH_SUPPORT_PSCI
188	select DRAM_SUN4I
189	select PHY_SUN4I_USB
190	select SUNXI_GEN_SUN4I
191	select SUPPORT_SPL
192	select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
193
194config MACH_SUN8I_A23
195	bool "sun8i (Allwinner A23)"
196	select CPU_V7A
197	select CPU_V7_HAS_NONSEC
198	select CPU_V7_HAS_VIRT
199	select ARCH_SUPPORT_PSCI
200	select DRAM_SUN8I_A23
201	select PHY_SUN4I_USB
202	select SUNXI_GEN_SUN6I
203	select SUPPORT_SPL
204	select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
205	imply CONS_INDEX_5 if !DM_SERIAL
206
207config MACH_SUN8I_A33
208	bool "sun8i (Allwinner A33)"
209	select CPU_V7A
210	select CPU_V7_HAS_NONSEC
211	select CPU_V7_HAS_VIRT
212	select ARCH_SUPPORT_PSCI
213	select DRAM_SUN8I_A33
214	select PHY_SUN4I_USB
215	select SUNXI_GEN_SUN6I
216	select SUPPORT_SPL
217	select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
218	imply CONS_INDEX_5 if !DM_SERIAL
219
220config MACH_SUN8I_A83T
221	bool "sun8i (Allwinner A83T)"
222	select CPU_V7A
223	select DRAM_SUN8I_A83T
224	select PHY_SUN4I_USB
225	select SUNXI_GEN_SUN6I
226	select MMC_SUNXI_HAS_NEW_MODE
227	select SUPPORT_SPL
228
229config MACH_SUN8I_H3
230	bool "sun8i (Allwinner H3)"
231	select CPU_V7A
232	select CPU_V7_HAS_NONSEC
233	select CPU_V7_HAS_VIRT
234	select ARCH_SUPPORT_PSCI
235	select MACH_SUNXI_H3_H5
236	select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
237
238config MACH_SUN8I_R40
239	bool "sun8i (Allwinner R40)"
240	select CPU_V7A
241	select CPU_V7_HAS_NONSEC
242	select CPU_V7_HAS_VIRT
243	select ARCH_SUPPORT_PSCI
244	select SUNXI_GEN_SUN6I
245	select SUPPORT_SPL
246	select SUNXI_DRAM_DW
247	select SUNXI_DRAM_DW_32BIT
248
249config MACH_SUN8I_V3S
250	bool "sun8i (Allwinner V3s)"
251	select CPU_V7A
252	select CPU_V7_HAS_NONSEC
253	select CPU_V7_HAS_VIRT
254	select ARCH_SUPPORT_PSCI
255	select SUNXI_GEN_SUN6I
256	select SUNXI_DRAM_DW
257	select SUNXI_DRAM_DW_16BIT
258	select SUPPORT_SPL
259	select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
260
261config MACH_SUN9I
262	bool "sun9i (Allwinner A80)"
263	select CPU_V7A
264	select DRAM_SUN9I
265	select SUN6I_PRCM
266	select SUNXI_GEN_SUN6I
267	select SUN8I_RSB
268	select SUPPORT_SPL
269
270config MACH_SUN50I
271	bool "sun50i (Allwinner A64)"
272	select ARM64
273	select DM_I2C
274	select PHY_SUN4I_USB
275	select SUNXI_DE2
276	select SUNXI_GEN_SUN6I
277	select SUPPORT_SPL
278	select SUNXI_DRAM_DW
279	select SUNXI_DRAM_DW_32BIT
280	select FIT
281	select SPL_LOAD_FIT
282	select SUNXI_A64_TIMER_ERRATUM
283
284config MACH_SUN50I_H5
285	bool "sun50i (Allwinner H5)"
286	select ARM64
287	select MACH_SUNXI_H3_H5
288	select FIT
289	select SPL_LOAD_FIT
290
291config MACH_SUN50I_H6
292	bool "sun50i (Allwinner H6)"
293	select ARM64
294	select SUPPORT_SPL
295	select FIT
296	select SPL_LOAD_FIT
297	select DRAM_SUN50I_H6
298
299endchoice
300
301# The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
302config MACH_SUN8I
303	bool
304	select SUN8I_RSB
305	select SUN6I_PRCM
306	default y if MACH_SUN8I_A23
307	default y if MACH_SUN8I_A33
308	default y if MACH_SUN8I_A83T
309	default y if MACH_SUNXI_H3_H5
310	default y if MACH_SUN8I_R40
311	default y if MACH_SUN8I_V3S
312
313config RESERVE_ALLWINNER_BOOT0_HEADER
314	bool "reserve space for Allwinner boot0 header"
315	select ENABLE_ARM_SOC_BOOT0_HOOK
316	---help---
317	Prepend a 1536 byte (empty) header to the U-Boot image file, to be
318	filled with magic values post build. The Allwinner provided boot0
319	blob relies on this information to load and execute U-Boot.
320	Only needed on 64-bit Allwinner boards so far when using boot0.
321
322config ARM_BOOT_HOOK_RMR
323	bool
324	depends on ARM64
325	default y
326	select ENABLE_ARM_SOC_BOOT0_HOOK
327	---help---
328	Insert some ARM32 code at the very beginning of the U-Boot binary
329	which uses an RMR register write to bring the core into AArch64 mode.
330	The very first instruction acts as a switch, since it's carefully
331	chosen to be a NOP in one mode and a branch in the other, so the
332	code would only be executed if not already in AArch64.
333	This allows both the SPL and the U-Boot proper to be entered in
334	either mode and switch to AArch64 if needed.
335
336if SUNXI_DRAM_DW
337config SUNXI_DRAM_DDR3
338	bool
339
340config SUNXI_DRAM_DDR2
341	bool
342
343config SUNXI_DRAM_LPDDR3
344	bool
345
346choice
347	prompt "DRAM Type and Timing"
348	default SUNXI_DRAM_DDR3_1333 if !MACH_SUN8I_V3S
349	default SUNXI_DRAM_DDR2_V3S if MACH_SUN8I_V3S
350
351config SUNXI_DRAM_DDR3_1333
352	bool "DDR3 1333"
353	select SUNXI_DRAM_DDR3
354	depends on !MACH_SUN8I_V3S
355	---help---
356	This option is the original only supported memory type, which suits
357	many H3/H5/A64 boards available now.
358
359config SUNXI_DRAM_LPDDR3_STOCK
360	bool "LPDDR3 with Allwinner stock configuration"
361	select SUNXI_DRAM_LPDDR3
362	---help---
363	This option is the LPDDR3 timing used by the stock boot0 by
364	Allwinner.
365
366config SUNXI_DRAM_DDR2_V3S
367	bool "DDR2 found in V3s chip"
368	select SUNXI_DRAM_DDR2
369	depends on MACH_SUN8I_V3S
370	---help---
371	This option is only for the DDR2 memory chip which is co-packaged in
372	Allwinner V3s SoC.
373
374endchoice
375endif
376
377config DRAM_TYPE
378	int "sunxi dram type"
379	depends on MACH_SUN8I_A83T
380	default 3
381	---help---
382	Set the dram type, 3: DDR3, 7: LPDDR3
383
384config DRAM_CLK
385	int "sunxi dram clock speed"
386	default 792 if MACH_SUN9I
387	default 648 if MACH_SUN8I_R40
388	default 312 if MACH_SUN6I || MACH_SUN8I
389	default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || \
390		       MACH_SUN8I_V3S
391	default 672 if MACH_SUN50I
392	default 744 if MACH_SUN50I_H6
393	---help---
394	Set the dram clock speed, valid range 240 - 480 (prior to sun9i),
395	must be a multiple of 24. For the sun9i (A80), the tested values
396	(for DDR3-1600) are 312 to 792.
397
398if MACH_SUN5I || MACH_SUN7I
399config DRAM_MBUS_CLK
400	int "sunxi mbus clock speed"
401	default 300
402	---help---
403	Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
404
405endif
406
407config DRAM_ZQ
408	int "sunxi dram zq value"
409	default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
410	default 127 if MACH_SUN7I
411	default 14779 if MACH_SUN8I_V3S
412	default 3881979 if MACH_SUN8I_R40 || MACH_SUN50I_H6
413	default 4145117 if MACH_SUN9I
414	default 3881915 if MACH_SUN50I
415	---help---
416	Set the dram zq value.
417
418config DRAM_ODT_EN
419	bool "sunxi dram odt enable"
420	default y if MACH_SUN8I_A23
421	default y if MACH_SUN8I_R40
422	default y if MACH_SUN50I
423	default y if MACH_SUN50I_H6
424	---help---
425	Select this to enable dram odt (on die termination).
426
427if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
428config DRAM_EMR1
429	int "sunxi dram emr1 value"
430	default 0 if MACH_SUN4I
431	default 4 if MACH_SUN5I || MACH_SUN7I
432	---help---
433	Set the dram controller emr1 value.
434
435config DRAM_TPR3
436	hex "sunxi dram tpr3 value"
437	default 0
438	---help---
439	Set the dram controller tpr3 parameter. This parameter configures
440	the delay on the command lane and also phase shifts, which are
441	applied for sampling incoming read data. The default value 0
442	means that no phase/delay adjustments are necessary. Properly
443	configuring this parameter increases reliability at high DRAM
444	clock speeds.
445
446config DRAM_DQS_GATING_DELAY
447	hex "sunxi dram dqs_gating_delay value"
448	default 0
449	---help---
450	Set the dram controller dqs_gating_delay parmeter. Each byte
451	encodes the DQS gating delay for each byte lane. The delay
452	granularity is 1/4 cycle. For example, the value 0x05060606
453	means that the delay is 5 quarter-cycles for one lane (1.25
454	cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
455	The default value 0 means autodetection. The results of hardware
456	autodetection are not very reliable and depend on the chip
457	temperature (sometimes producing different results on cold start
458	and warm reboot). But the accuracy of hardware autodetection
459	is usually good enough, unless running at really high DRAM
460	clocks speeds (up to 600MHz). If unsure, keep as 0.
461
462choice
463	prompt "sunxi dram timings"
464	default DRAM_TIMINGS_VENDOR_MAGIC
465	---help---
466	Select the timings of the DDR3 chips.
467
468config DRAM_TIMINGS_VENDOR_MAGIC
469	bool "Magic vendor timings from Android"
470	---help---
471	The same DRAM timings as in the Allwinner boot0 bootloader.
472
473config DRAM_TIMINGS_DDR3_1066F_1333H
474	bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
475	---help---
476	Use the timings of the standard JEDEC DDR3-1066F speed bin for
477	DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
478	for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
479	used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
480	or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
481	that down binning to DDR3-1066F is supported (because DDR3-1066F
482	uses a bit faster timings than DDR3-1333H).
483
484config DRAM_TIMINGS_DDR3_800E_1066G_1333J
485	bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
486	---help---
487	Use the timings of the slowest possible JEDEC speed bin for the
488	selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
489	DDR3-800E, DDR3-1066G or DDR3-1333J.
490
491endchoice
492
493endif
494
495if MACH_SUN8I_A23
496config DRAM_ODT_CORRECTION
497	int "sunxi dram odt correction value"
498	default 0
499	---help---
500	Set the dram odt correction value (range -255 - 255). In allwinner
501	fex files, this option is found in bits 8-15 of the u32 odt_en variable
502	in the [dram] section. When bit 31 of the odt_en variable is set
503	then the correction is negative. Usually the value for this is 0.
504endif
505
506config SYS_CLK_FREQ
507	default 1008000000 if MACH_SUN4I
508	default 1008000000 if MACH_SUN5I
509	default 1008000000 if MACH_SUN6I
510	default 912000000 if MACH_SUN7I
511	default 816000000 if MACH_SUN50I || MACH_SUN50I_H5
512	default 1008000000 if MACH_SUN8I
513	default 1008000000 if MACH_SUN9I
514	default 888000000 if MACH_SUN50I_H6
515
516config SYS_CONFIG_NAME
517	default "sun4i" if MACH_SUN4I
518	default "sun5i" if MACH_SUN5I
519	default "sun6i" if MACH_SUN6I
520	default "sun7i" if MACH_SUN7I
521	default "sun8i" if MACH_SUN8I
522	default "sun9i" if MACH_SUN9I
523	default "sun50i" if MACH_SUN50I
524	default "sun50i" if MACH_SUN50I_H6
525
526config SYS_BOARD
527	default "sunxi"
528
529config SYS_SOC
530	default "sunxi"
531
532config UART0_PORT_F
533	bool "UART0 on MicroSD breakout board"
534	default n
535	---help---
536	Repurpose the SD card slot for getting access to the UART0 serial
537	console. Primarily useful only for low level u-boot debugging on
538	tablets, where normal UART0 is difficult to access and requires
539	device disassembly and/or soldering. As the SD card can't be used
540	at the same time, the system can be only booted in the FEL mode.
541	Only enable this if you really know what you are doing.
542
543config OLD_SUNXI_KERNEL_COMPAT
544	bool "Enable workarounds for booting old kernels"
545	default n
546	---help---
547	Set this to enable various workarounds for old kernels, this results in
548	sub-optimal settings for newer kernels, only enable if needed.
549
550config MACPWR
551	string "MAC power pin"
552	default ""
553	help
554	  Set the pin used to power the MAC. This takes a string in the format
555	  understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
556
557config MMC0_CD_PIN
558	string "Card detect pin for mmc0"
559	default "PF6" if MACH_SUN8I_A83T || MACH_SUNXI_H3_H5 || MACH_SUN50I
560	default ""
561	---help---
562	Set the card detect pin for mmc0, leave empty to not use cd. This
563	takes a string in the format understood by sunxi_name_to_gpio, e.g.
564	PH1 for pin 1 of port H.
565
566config MMC1_CD_PIN
567	string "Card detect pin for mmc1"
568	default ""
569	---help---
570	See MMC0_CD_PIN help text.
571
572config MMC2_CD_PIN
573	string "Card detect pin for mmc2"
574	default ""
575	---help---
576	See MMC0_CD_PIN help text.
577
578config MMC3_CD_PIN
579	string "Card detect pin for mmc3"
580	default ""
581	---help---
582	See MMC0_CD_PIN help text.
583
584config MMC1_PINS
585	string "Pins for mmc1"
586	default ""
587	---help---
588	Set the pins used for mmc1, when applicable. This takes a string in the
589	format understood by sunxi_name_to_gpio_bank, e.g. PH for port H.
590
591config MMC2_PINS
592	string "Pins for mmc2"
593	default ""
594	---help---
595	See MMC1_PINS help text.
596
597config MMC3_PINS
598	string "Pins for mmc3"
599	default ""
600	---help---
601	See MMC1_PINS help text.
602
603config MMC_SUNXI_SLOT_EXTRA
604	int "mmc extra slot number"
605	default -1
606	---help---
607	sunxi builds always enable mmc0, some boards also have a second sdcard
608	slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
609	support for this.
610
611config INITIAL_USB_SCAN_DELAY
612	int "delay initial usb scan by x ms to allow builtin devices to init"
613	default 0
614	---help---
615	Some boards have on board usb devices which need longer than the
616	USB spec's 1 second to connect from board powerup. Set this config
617	option to a non 0 value to add an extra delay before the first usb
618	bus scan.
619
620config USB0_VBUS_PIN
621	string "Vbus enable pin for usb0 (otg)"
622	default ""
623	---help---
624	Set the Vbus enable pin for usb0 (otg). This takes a string in the
625	format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
626
627config USB0_VBUS_DET
628	string "Vbus detect pin for usb0 (otg)"
629	default ""
630	---help---
631	Set the Vbus detect pin for usb0 (otg). This takes a string in the
632	format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
633
634config USB0_ID_DET
635	string "ID detect pin for usb0 (otg)"
636	default ""
637	---help---
638	Set the ID detect pin for usb0 (otg). This takes a string in the
639	format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
640
641config USB1_VBUS_PIN
642	string "Vbus enable pin for usb1 (ehci0)"
643	default "PH6" if MACH_SUN4I || MACH_SUN7I
644	default "PH27" if MACH_SUN6I
645	---help---
646	Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
647	a string in the format understood by sunxi_name_to_gpio, e.g.
648	PH1 for pin 1 of port H.
649
650config USB2_VBUS_PIN
651	string "Vbus enable pin for usb2 (ehci1)"
652	default "PH3" if MACH_SUN4I || MACH_SUN7I
653	default "PH24" if MACH_SUN6I
654	---help---
655	See USB1_VBUS_PIN help text.
656
657config USB3_VBUS_PIN
658	string "Vbus enable pin for usb3 (ehci2)"
659	default ""
660	---help---
661	See USB1_VBUS_PIN help text.
662
663config I2C0_ENABLE
664	bool "Enable I2C/TWI controller 0"
665	default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_R40
666	default n if MACH_SUN6I || MACH_SUN8I
667	select CMD_I2C
668	---help---
669	This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
670	its clock and setting up the bus. This is especially useful on devices
671	with slaves connected to the bus or with pins exposed through e.g. an
672	expansion port/header.
673
674config I2C1_ENABLE
675	bool "Enable I2C/TWI controller 1"
676	default n
677	select CMD_I2C
678	---help---
679	See I2C0_ENABLE help text.
680
681config I2C2_ENABLE
682	bool "Enable I2C/TWI controller 2"
683	default n
684	select CMD_I2C
685	---help---
686	See I2C0_ENABLE help text.
687
688if MACH_SUN6I || MACH_SUN7I
689config I2C3_ENABLE
690	bool "Enable I2C/TWI controller 3"
691	default n
692	select CMD_I2C
693	---help---
694	See I2C0_ENABLE help text.
695endif
696
697if SUNXI_GEN_SUN6I
698config R_I2C_ENABLE
699	bool "Enable the PRCM I2C/TWI controller"
700	# This is used for the pmic on H3
701	default y if SY8106A_POWER
702	select CMD_I2C
703	---help---
704	Set this to y to enable the I2C controller which is part of the PRCM.
705endif
706
707if MACH_SUN7I
708config I2C4_ENABLE
709	bool "Enable I2C/TWI controller 4"
710	default n
711	select CMD_I2C
712	---help---
713	See I2C0_ENABLE help text.
714endif
715
716config AXP_GPIO
717	bool "Enable support for gpio-s on axp PMICs"
718	default n
719	---help---
720	Say Y here to enable support for the gpio pins of the axp PMIC ICs.
721
722config VIDEO_SUNXI
723	bool "Enable graphical uboot console on HDMI, LCD or VGA"
724	depends on !MACH_SUN8I_A83T
725	depends on !MACH_SUNXI_H3_H5
726	depends on !MACH_SUN8I_R40
727	depends on !MACH_SUN8I_V3S
728	depends on !MACH_SUN9I
729	depends on !MACH_SUN50I
730	depends on !MACH_SUN50I_H6
731	select VIDEO
732	imply VIDEO_DT_SIMPLEFB
733	default y
734	---help---
735	Say Y here to add support for using a cfb console on the HDMI, LCD
736	or VGA output found on most sunxi devices. See doc/README.video for
737	info on how to select the video output and mode.
738
739config VIDEO_HDMI
740	bool "HDMI output support"
741	depends on VIDEO_SUNXI && !MACH_SUN8I
742	default y
743	---help---
744	Say Y here to add support for outputting video over HDMI.
745
746config VIDEO_VGA
747	bool "VGA output support"
748	depends on VIDEO_SUNXI && (MACH_SUN4I || MACH_SUN7I)
749	default n
750	---help---
751	Say Y here to add support for outputting video over VGA.
752
753config VIDEO_VGA_VIA_LCD
754	bool "VGA via LCD controller support"
755	depends on VIDEO_SUNXI && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
756	default n
757	---help---
758	Say Y here to add support for external DACs connected to the parallel
759	LCD interface driving a VGA connector, such as found on the
760	Olimex A13 boards.
761
762config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
763	bool "Force sync active high for VGA via LCD controller support"
764	depends on VIDEO_VGA_VIA_LCD
765	default n
766	---help---
767	Say Y here if you've a board which uses opendrain drivers for the vga
768	hsync and vsync signals. Opendrain drivers cannot generate steep enough
769	positive edges for a stable video output, so on boards with opendrain
770	drivers the sync signals must always be active high.
771
772config VIDEO_VGA_EXTERNAL_DAC_EN
773	string "LCD panel power enable pin"
774	depends on VIDEO_VGA_VIA_LCD
775	default ""
776	---help---
777	Set the enable pin for the external VGA DAC. This takes a string in the
778	format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
779
780config VIDEO_COMPOSITE
781	bool "Composite video output support"
782	depends on VIDEO_SUNXI && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
783	default n
784	---help---
785	Say Y here to add support for outputting composite video.
786
787config VIDEO_LCD_MODE
788	string "LCD panel timing details"
789	depends on VIDEO_SUNXI
790	default ""
791	---help---
792	LCD panel timing details string, leave empty if there is no LCD panel.
793	This is in drivers/video/videomodes.c: video_get_params() format, e.g.
794	x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
795	Also see: http://linux-sunxi.org/LCD
796
797config VIDEO_LCD_DCLK_PHASE
798	int "LCD panel display clock phase"
799	depends on VIDEO_SUNXI || DM_VIDEO
800	default 1
801	---help---
802	Select LCD panel display clock phase shift, range 0-3.
803
804config VIDEO_LCD_POWER
805	string "LCD panel power enable pin"
806	depends on VIDEO_SUNXI
807	default ""
808	---help---
809	Set the power enable pin for the LCD panel. This takes a string in the
810	format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
811
812config VIDEO_LCD_RESET
813	string "LCD panel reset pin"
814	depends on VIDEO_SUNXI
815	default ""
816	---help---
817	Set the reset pin for the LCD panel. This takes a string in the format
818	understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
819
820config VIDEO_LCD_BL_EN
821	string "LCD panel backlight enable pin"
822	depends on VIDEO_SUNXI
823	default ""
824	---help---
825	Set the backlight enable pin for the LCD panel. This takes a string in the
826	the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
827	port H.
828
829config VIDEO_LCD_BL_PWM
830	string "LCD panel backlight pwm pin"
831	depends on VIDEO_SUNXI
832	default ""
833	---help---
834	Set the backlight pwm pin for the LCD panel. This takes a string in the
835	format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
836
837config VIDEO_LCD_BL_PWM_ACTIVE_LOW
838	bool "LCD panel backlight pwm is inverted"
839	depends on VIDEO_SUNXI
840	default y
841	---help---
842	Set this if the backlight pwm output is active low.
843
844config VIDEO_LCD_PANEL_I2C
845	bool "LCD panel needs to be configured via i2c"
846	depends on VIDEO_SUNXI
847	default n
848	select CMD_I2C
849	---help---
850	Say y here if the LCD panel needs to be configured via i2c. This
851	will add a bitbang i2c controller using gpios to talk to the LCD.
852
853config VIDEO_LCD_PANEL_I2C_SDA
854	string "LCD panel i2c interface SDA pin"
855	depends on VIDEO_LCD_PANEL_I2C
856	default "PG12"
857	---help---
858	Set the SDA pin for the LCD i2c interface. This takes a string in the
859	format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
860
861config VIDEO_LCD_PANEL_I2C_SCL
862	string "LCD panel i2c interface SCL pin"
863	depends on VIDEO_LCD_PANEL_I2C
864	default "PG10"
865	---help---
866	Set the SCL pin for the LCD i2c interface. This takes a string in the
867	format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
868
869
870# Note only one of these may be selected at a time! But hidden choices are
871# not supported by Kconfig
872config VIDEO_LCD_IF_PARALLEL
873	bool
874
875config VIDEO_LCD_IF_LVDS
876	bool
877
878config SUNXI_DE2
879	bool
880	default n
881
882config VIDEO_DE2
883	bool "Display Engine 2 video driver"
884	depends on SUNXI_DE2
885	select DM_VIDEO
886	select DISPLAY
887	imply VIDEO_DT_SIMPLEFB
888	default y
889	---help---
890	Say y here if you want to build DE2 video driver which is present on
891	newer SoCs. Currently only HDMI output is supported.
892
893
894choice
895	prompt "LCD panel support"
896	depends on VIDEO_SUNXI
897	---help---
898	Select which type of LCD panel to support.
899
900config VIDEO_LCD_PANEL_PARALLEL
901	bool "Generic parallel interface LCD panel"
902	select VIDEO_LCD_IF_PARALLEL
903
904config VIDEO_LCD_PANEL_LVDS
905	bool "Generic lvds interface LCD panel"
906	select VIDEO_LCD_IF_LVDS
907
908config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
909	bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
910	select VIDEO_LCD_SSD2828
911	select VIDEO_LCD_IF_PARALLEL
912	---help---
913	7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
914
915config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
916	bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip"
917	select VIDEO_LCD_ANX9804
918	select VIDEO_LCD_IF_PARALLEL
919	select VIDEO_LCD_PANEL_I2C
920	---help---
921	Select this for eDP LCD panels with 4 lanes running at 1.62G,
922	connected via an ANX9804 bridge chip.
923
924config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
925	bool "Hitachi tx18d42vm LCD panel"
926	select VIDEO_LCD_HITACHI_TX18D42VM
927	select VIDEO_LCD_IF_LVDS
928	---help---
929	7.85" 1024x768 Hitachi tx18d42vm LCD panel support
930
931config VIDEO_LCD_TL059WV5C0
932	bool "tl059wv5c0 LCD panel"
933	select VIDEO_LCD_PANEL_I2C
934	select VIDEO_LCD_IF_PARALLEL
935	---help---
936	6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and
937	Aigo M60/M608/M606 tablets.
938
939endchoice
940
941config SATAPWR
942	string "SATA power pin"
943	default ""
944	help
945	  Set the pins used to power the SATA. This takes a string in the
946	  format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
947	  port H.
948
949config GMAC_TX_DELAY
950	int "GMAC Transmit Clock Delay Chain"
951	default 0
952	---help---
953	Set the GMAC Transmit Clock Delay Chain value.
954
955config SPL_STACK_R_ADDR
956	default 0x4fe00000 if MACH_SUN4I
957	default 0x4fe00000 if MACH_SUN5I
958	default 0x4fe00000 if MACH_SUN6I
959	default 0x4fe00000 if MACH_SUN7I
960	default 0x4fe00000 if MACH_SUN8I
961	default 0x2fe00000 if MACH_SUN9I
962	default 0x4fe00000 if MACH_SUN50I
963	default 0x4fe00000 if MACH_SUN50I_H6
964
965config SPL_SPI_SUNXI
966	bool "Support for SPI Flash on Allwinner SoCs in SPL"
967	depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I
968	help
969	  Enable support for SPI Flash. This option allows SPL to read from
970	  sunxi SPI Flash. It uses the same method as the boot ROM, so does
971	  not need any extra configuration.
972
973endif
974