xref: /openbmc/u-boot/arch/arm/mach-sunxi/Kconfig (revision d754254f)
1if ARCH_SUNXI
2
3config IDENT_STRING
4	default " Allwinner Technology"
5
6config SUNXI_HIGH_SRAM
7	bool
8	default n
9	---help---
10	Older Allwinner SoCs have their mask boot ROM mapped just below 4GB,
11	with the first SRAM region being located at address 0.
12	Some newer SoCs map the boot ROM at address 0 instead and move the
13	SRAM to 64KB, just behind the mask ROM.
14	Chips using the latter setup are supposed to select this option to
15	adjust the addresses accordingly.
16
17# Note only one of these may be selected at a time! But hidden choices are
18# not supported by Kconfig
19config SUNXI_GEN_SUN4I
20	bool
21	---help---
22	Select this for sunxi SoCs which have resets and clocks set up
23	as the original A10 (mach-sun4i).
24
25config SUNXI_GEN_SUN6I
26	bool
27	---help---
28	Select this for sunxi SoCs which have sun6i like periphery, like
29	separate ahb reset control registers, custom pmic bus, new style
30	watchdog, etc.
31
32config SUNXI_DRAM_DW
33	bool
34	---help---
35	Select this for sunxi SoCs which uses a DRAM controller like the
36	DesignWare controller used in H3, mainly SoCs after H3, which do
37	not have official open-source DRAM initialization code, but can
38	use modified H3 DRAM initialization code.
39
40if SUNXI_DRAM_DW
41config SUNXI_DRAM_DW_16BIT
42	bool
43	---help---
44	Select this for sunxi SoCs with DesignWare DRAM controller and
45	have only 16-bit memory buswidth.
46
47config SUNXI_DRAM_DW_32BIT
48	bool
49	---help---
50	Select this for sunxi SoCs with DesignWare DRAM controller with
51	32-bit memory buswidth.
52endif
53
54config MACH_SUNXI_H3_H5
55	bool
56	select DM_I2C
57	select SUNXI_DE2
58	select SUNXI_DRAM_DW
59	select SUNXI_DRAM_DW_32BIT
60	select SUNXI_GEN_SUN6I
61	select SUPPORT_SPL
62
63choice
64	prompt "Sunxi SoC Variant"
65	optional
66
67config MACH_SUN4I
68	bool "sun4i (Allwinner A10)"
69	select CPU_V7
70	select ARM_CORTEX_CPU_IS_UP
71	select SUNXI_GEN_SUN4I
72	select SUPPORT_SPL
73
74config MACH_SUN5I
75	bool "sun5i (Allwinner A13)"
76	select CPU_V7
77	select ARM_CORTEX_CPU_IS_UP
78	select SUNXI_GEN_SUN4I
79	select SUPPORT_SPL
80
81config MACH_SUN6I
82	bool "sun6i (Allwinner A31)"
83	select CPU_V7
84	select CPU_V7_HAS_NONSEC
85	select CPU_V7_HAS_VIRT
86	select ARCH_SUPPORT_PSCI
87	select SUNXI_GEN_SUN6I
88	select SUPPORT_SPL
89	select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
90
91config MACH_SUN7I
92	bool "sun7i (Allwinner A20)"
93	select CPU_V7
94	select CPU_V7_HAS_NONSEC
95	select CPU_V7_HAS_VIRT
96	select ARCH_SUPPORT_PSCI
97	select SUNXI_GEN_SUN4I
98	select SUPPORT_SPL
99	select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
100
101config MACH_SUN8I_A23
102	bool "sun8i (Allwinner A23)"
103	select CPU_V7
104	select CPU_V7_HAS_NONSEC
105	select CPU_V7_HAS_VIRT
106	select ARCH_SUPPORT_PSCI
107	select SUNXI_GEN_SUN6I
108	select SUPPORT_SPL
109	select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
110
111config MACH_SUN8I_A33
112	bool "sun8i (Allwinner A33)"
113	select CPU_V7
114	select CPU_V7_HAS_NONSEC
115	select CPU_V7_HAS_VIRT
116	select ARCH_SUPPORT_PSCI
117	select SUNXI_GEN_SUN6I
118	select SUPPORT_SPL
119	select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
120
121config MACH_SUN8I_A83T
122	bool "sun8i (Allwinner A83T)"
123	select CPU_V7
124	select SUNXI_GEN_SUN6I
125	select SUPPORT_SPL
126
127config MACH_SUN8I_H3
128	bool "sun8i (Allwinner H3)"
129	select CPU_V7
130	select CPU_V7_HAS_NONSEC
131	select CPU_V7_HAS_VIRT
132	select ARCH_SUPPORT_PSCI
133	select MACH_SUNXI_H3_H5
134	select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
135
136config MACH_SUN8I_R40
137	bool "sun8i (Allwinner R40)"
138	select CPU_V7
139	select CPU_V7_HAS_NONSEC
140	select CPU_V7_HAS_VIRT
141	select ARCH_SUPPORT_PSCI
142	select SUNXI_GEN_SUN6I
143	select SUPPORT_SPL
144	select SUNXI_DRAM_DW
145	select SUNXI_DRAM_DW_32BIT
146
147config MACH_SUN8I_V3S
148	bool "sun8i (Allwinner V3s)"
149	select CPU_V7
150	select CPU_V7_HAS_NONSEC
151	select CPU_V7_HAS_VIRT
152	select ARCH_SUPPORT_PSCI
153	select SUNXI_GEN_SUN6I
154	select SUNXI_DRAM_DW
155	select SUNXI_DRAM_DW_16BIT
156	select SUPPORT_SPL
157	select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
158
159config MACH_SUN9I
160	bool "sun9i (Allwinner A80)"
161	select CPU_V7
162	select SUNXI_HIGH_SRAM
163	select SUNXI_GEN_SUN6I
164	select SUPPORT_SPL
165
166config MACH_SUN50I
167	bool "sun50i (Allwinner A64)"
168	select ARM64
169	select DM_I2C
170	select SUNXI_DE2
171	select SUNXI_GEN_SUN6I
172	select SUNXI_HIGH_SRAM
173	select SUPPORT_SPL
174	select SUNXI_DRAM_DW
175	select SUNXI_DRAM_DW_32BIT
176	select FIT
177	select SPL_LOAD_FIT
178
179config MACH_SUN50I_H5
180	bool "sun50i (Allwinner H5)"
181	select ARM64
182	select MACH_SUNXI_H3_H5
183	select SUNXI_HIGH_SRAM
184	select FIT
185	select SPL_LOAD_FIT
186
187endchoice
188
189# The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
190config MACH_SUN8I
191	bool
192	default y if MACH_SUN8I_A23
193	default y if MACH_SUN8I_A33
194	default y if MACH_SUN8I_A83T
195	default y if MACH_SUNXI_H3_H5
196	default y if MACH_SUN8I_R40
197	default y if MACH_SUN8I_V3S
198
199config RESERVE_ALLWINNER_BOOT0_HEADER
200	bool "reserve space for Allwinner boot0 header"
201	select ENABLE_ARM_SOC_BOOT0_HOOK
202	---help---
203	Prepend a 1536 byte (empty) header to the U-Boot image file, to be
204	filled with magic values post build. The Allwinner provided boot0
205	blob relies on this information to load and execute U-Boot.
206	Only needed on 64-bit Allwinner boards so far when using boot0.
207
208config ARM_BOOT_HOOK_RMR
209	bool
210	depends on ARM64
211	default y
212	select ENABLE_ARM_SOC_BOOT0_HOOK
213	---help---
214	Insert some ARM32 code at the very beginning of the U-Boot binary
215	which uses an RMR register write to bring the core into AArch64 mode.
216	The very first instruction acts as a switch, since it's carefully
217	chosen to be a NOP in one mode and a branch in the other, so the
218	code would only be executed if not already in AArch64.
219	This allows both the SPL and the U-Boot proper to be entered in
220	either mode and switch to AArch64 if needed.
221
222if SUNXI_DRAM_DW
223config SUNXI_DRAM_DDR3
224	bool
225
226config SUNXI_DRAM_DDR2
227	bool
228
229config SUNXI_DRAM_LPDDR3
230	bool
231
232choice
233	prompt "DRAM Type and Timing"
234	default SUNXI_DRAM_DDR3_1333 if !MACH_SUN8I_V3S
235	default SUNXI_DRAM_DDR2_V3S if MACH_SUN8I_V3S
236
237config SUNXI_DRAM_DDR3_1333
238	bool "DDR3 1333"
239	select SUNXI_DRAM_DDR3
240	depends on !MACH_SUN8I_V3S
241	---help---
242	This option is the original only supported memory type, which suits
243	many H3/H5/A64 boards available now.
244
245config SUNXI_DRAM_LPDDR3_STOCK
246	bool "LPDDR3 with Allwinner stock configuration"
247	select SUNXI_DRAM_LPDDR3
248	---help---
249	This option is the LPDDR3 timing used by the stock boot0 by
250	Allwinner.
251
252config SUNXI_DRAM_DDR2_V3S
253	bool "DDR2 found in V3s chip"
254	select SUNXI_DRAM_DDR2
255	depends on MACH_SUN8I_V3S
256	---help---
257	This option is only for the DDR2 memory chip which is co-packaged in
258	Allwinner V3s SoC.
259
260endchoice
261endif
262
263config DRAM_TYPE
264	int "sunxi dram type"
265	depends on MACH_SUN8I_A83T
266	default 3
267	---help---
268	Set the dram type, 3: DDR3, 7: LPDDR3
269
270config DRAM_CLK
271	int "sunxi dram clock speed"
272	default 792 if MACH_SUN9I
273	default 648 if MACH_SUN8I_R40
274	default 312 if MACH_SUN6I || MACH_SUN8I
275	default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || \
276		       MACH_SUN8I_V3S
277	default 672 if MACH_SUN50I
278	---help---
279	Set the dram clock speed, valid range 240 - 480 (prior to sun9i),
280	must be a multiple of 24. For the sun9i (A80), the tested values
281	(for DDR3-1600) are 312 to 792.
282
283if MACH_SUN5I || MACH_SUN7I
284config DRAM_MBUS_CLK
285	int "sunxi mbus clock speed"
286	default 300
287	---help---
288	Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
289
290endif
291
292config DRAM_ZQ
293	int "sunxi dram zq value"
294	default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
295	default 127 if MACH_SUN7I
296	default 14779 if MACH_SUN8I_V3S
297	default 3881979 if MACH_SUN8I_R40
298	default 4145117 if MACH_SUN9I
299	default 3881915 if MACH_SUN50I
300	---help---
301	Set the dram zq value.
302
303config DRAM_ODT_EN
304	bool "sunxi dram odt enable"
305	default n if !MACH_SUN8I_A23
306	default y if MACH_SUN8I_A23
307	default y if MACH_SUN8I_R40
308	default y if MACH_SUN50I
309	---help---
310	Select this to enable dram odt (on die termination).
311
312if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
313config DRAM_EMR1
314	int "sunxi dram emr1 value"
315	default 0 if MACH_SUN4I
316	default 4 if MACH_SUN5I || MACH_SUN7I
317	---help---
318	Set the dram controller emr1 value.
319
320config DRAM_TPR3
321	hex "sunxi dram tpr3 value"
322	default 0
323	---help---
324	Set the dram controller tpr3 parameter. This parameter configures
325	the delay on the command lane and also phase shifts, which are
326	applied for sampling incoming read data. The default value 0
327	means that no phase/delay adjustments are necessary. Properly
328	configuring this parameter increases reliability at high DRAM
329	clock speeds.
330
331config DRAM_DQS_GATING_DELAY
332	hex "sunxi dram dqs_gating_delay value"
333	default 0
334	---help---
335	Set the dram controller dqs_gating_delay parmeter. Each byte
336	encodes the DQS gating delay for each byte lane. The delay
337	granularity is 1/4 cycle. For example, the value 0x05060606
338	means that the delay is 5 quarter-cycles for one lane (1.25
339	cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
340	The default value 0 means autodetection. The results of hardware
341	autodetection are not very reliable and depend on the chip
342	temperature (sometimes producing different results on cold start
343	and warm reboot). But the accuracy of hardware autodetection
344	is usually good enough, unless running at really high DRAM
345	clocks speeds (up to 600MHz). If unsure, keep as 0.
346
347choice
348	prompt "sunxi dram timings"
349	default DRAM_TIMINGS_VENDOR_MAGIC
350	---help---
351	Select the timings of the DDR3 chips.
352
353config DRAM_TIMINGS_VENDOR_MAGIC
354	bool "Magic vendor timings from Android"
355	---help---
356	The same DRAM timings as in the Allwinner boot0 bootloader.
357
358config DRAM_TIMINGS_DDR3_1066F_1333H
359	bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
360	---help---
361	Use the timings of the standard JEDEC DDR3-1066F speed bin for
362	DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
363	for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
364	used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
365	or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
366	that down binning to DDR3-1066F is supported (because DDR3-1066F
367	uses a bit faster timings than DDR3-1333H).
368
369config DRAM_TIMINGS_DDR3_800E_1066G_1333J
370	bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
371	---help---
372	Use the timings of the slowest possible JEDEC speed bin for the
373	selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
374	DDR3-800E, DDR3-1066G or DDR3-1333J.
375
376endchoice
377
378endif
379
380if MACH_SUN8I_A23
381config DRAM_ODT_CORRECTION
382	int "sunxi dram odt correction value"
383	default 0
384	---help---
385	Set the dram odt correction value (range -255 - 255). In allwinner
386	fex files, this option is found in bits 8-15 of the u32 odt_en variable
387	in the [dram] section. When bit 31 of the odt_en variable is set
388	then the correction is negative. Usually the value for this is 0.
389endif
390
391config SYS_CLK_FREQ
392	default 1008000000 if MACH_SUN4I
393	default 1008000000 if MACH_SUN5I
394	default 1008000000 if MACH_SUN6I
395	default 912000000 if MACH_SUN7I
396	default 1008000000 if MACH_SUN8I
397	default 1008000000 if MACH_SUN9I
398	default 816000000 if MACH_SUN50I
399
400config SYS_CONFIG_NAME
401	default "sun4i" if MACH_SUN4I
402	default "sun5i" if MACH_SUN5I
403	default "sun6i" if MACH_SUN6I
404	default "sun7i" if MACH_SUN7I
405	default "sun8i" if MACH_SUN8I
406	default "sun9i" if MACH_SUN9I
407	default "sun50i" if MACH_SUN50I
408
409config SYS_BOARD
410	default "sunxi"
411
412config SYS_SOC
413	default "sunxi"
414
415config UART0_PORT_F
416	bool "UART0 on MicroSD breakout board"
417	default n
418	---help---
419	Repurpose the SD card slot for getting access to the UART0 serial
420	console. Primarily useful only for low level u-boot debugging on
421	tablets, where normal UART0 is difficult to access and requires
422	device disassembly and/or soldering. As the SD card can't be used
423	at the same time, the system can be only booted in the FEL mode.
424	Only enable this if you really know what you are doing.
425
426config OLD_SUNXI_KERNEL_COMPAT
427	bool "Enable workarounds for booting old kernels"
428	default n
429	---help---
430	Set this to enable various workarounds for old kernels, this results in
431	sub-optimal settings for newer kernels, only enable if needed.
432
433config MACPWR
434	string "MAC power pin"
435	default ""
436	help
437	  Set the pin used to power the MAC. This takes a string in the format
438	  understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
439
440config MMC0_CD_PIN
441	string "Card detect pin for mmc0"
442	default "PF6" if MACH_SUN8I_A83T || MACH_SUNXI_H3_H5 || MACH_SUN50I
443	default ""
444	---help---
445	Set the card detect pin for mmc0, leave empty to not use cd. This
446	takes a string in the format understood by sunxi_name_to_gpio, e.g.
447	PH1 for pin 1 of port H.
448
449config MMC1_CD_PIN
450	string "Card detect pin for mmc1"
451	default ""
452	---help---
453	See MMC0_CD_PIN help text.
454
455config MMC2_CD_PIN
456	string "Card detect pin for mmc2"
457	default ""
458	---help---
459	See MMC0_CD_PIN help text.
460
461config MMC3_CD_PIN
462	string "Card detect pin for mmc3"
463	default ""
464	---help---
465	See MMC0_CD_PIN help text.
466
467config MMC1_PINS
468	string "Pins for mmc1"
469	default ""
470	---help---
471	Set the pins used for mmc1, when applicable. This takes a string in the
472	format understood by sunxi_name_to_gpio_bank, e.g. PH for port H.
473
474config MMC2_PINS
475	string "Pins for mmc2"
476	default ""
477	---help---
478	See MMC1_PINS help text.
479
480config MMC3_PINS
481	string "Pins for mmc3"
482	default ""
483	---help---
484	See MMC1_PINS help text.
485
486config MMC_SUNXI_SLOT_EXTRA
487	int "mmc extra slot number"
488	default -1
489	---help---
490	sunxi builds always enable mmc0, some boards also have a second sdcard
491	slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
492	support for this.
493
494config INITIAL_USB_SCAN_DELAY
495	int "delay initial usb scan by x ms to allow builtin devices to init"
496	default 0
497	---help---
498	Some boards have on board usb devices which need longer than the
499	USB spec's 1 second to connect from board powerup. Set this config
500	option to a non 0 value to add an extra delay before the first usb
501	bus scan.
502
503config USB0_VBUS_PIN
504	string "Vbus enable pin for usb0 (otg)"
505	default ""
506	---help---
507	Set the Vbus enable pin for usb0 (otg). This takes a string in the
508	format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
509
510config USB0_VBUS_DET
511	string "Vbus detect pin for usb0 (otg)"
512	default ""
513	---help---
514	Set the Vbus detect pin for usb0 (otg). This takes a string in the
515	format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
516
517config USB0_ID_DET
518	string "ID detect pin for usb0 (otg)"
519	default ""
520	---help---
521	Set the ID detect pin for usb0 (otg). This takes a string in the
522	format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
523
524config USB1_VBUS_PIN
525	string "Vbus enable pin for usb1 (ehci0)"
526	default "PH6" if MACH_SUN4I || MACH_SUN7I
527	default "PH27" if MACH_SUN6I
528	---help---
529	Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
530	a string in the format understood by sunxi_name_to_gpio, e.g.
531	PH1 for pin 1 of port H.
532
533config USB2_VBUS_PIN
534	string "Vbus enable pin for usb2 (ehci1)"
535	default "PH3" if MACH_SUN4I || MACH_SUN7I
536	default "PH24" if MACH_SUN6I
537	---help---
538	See USB1_VBUS_PIN help text.
539
540config USB3_VBUS_PIN
541	string "Vbus enable pin for usb3 (ehci2)"
542	default ""
543	---help---
544	See USB1_VBUS_PIN help text.
545
546config I2C0_ENABLE
547	bool "Enable I2C/TWI controller 0"
548	default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_R40
549	default n if MACH_SUN6I || MACH_SUN8I
550	select CMD_I2C
551	---help---
552	This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
553	its clock and setting up the bus. This is especially useful on devices
554	with slaves connected to the bus or with pins exposed through e.g. an
555	expansion port/header.
556
557config I2C1_ENABLE
558	bool "Enable I2C/TWI controller 1"
559	default n
560	select CMD_I2C
561	---help---
562	See I2C0_ENABLE help text.
563
564config I2C2_ENABLE
565	bool "Enable I2C/TWI controller 2"
566	default n
567	select CMD_I2C
568	---help---
569	See I2C0_ENABLE help text.
570
571if MACH_SUN6I || MACH_SUN7I
572config I2C3_ENABLE
573	bool "Enable I2C/TWI controller 3"
574	default n
575	select CMD_I2C
576	---help---
577	See I2C0_ENABLE help text.
578endif
579
580if SUNXI_GEN_SUN6I
581config R_I2C_ENABLE
582	bool "Enable the PRCM I2C/TWI controller"
583	# This is used for the pmic on H3
584	default y if SY8106A_POWER
585	select CMD_I2C
586	---help---
587	Set this to y to enable the I2C controller which is part of the PRCM.
588endif
589
590if MACH_SUN7I
591config I2C4_ENABLE
592	bool "Enable I2C/TWI controller 4"
593	default n
594	select CMD_I2C
595	---help---
596	See I2C0_ENABLE help text.
597endif
598
599config AXP_GPIO
600	bool "Enable support for gpio-s on axp PMICs"
601	default n
602	---help---
603	Say Y here to enable support for the gpio pins of the axp PMIC ICs.
604
605config VIDEO
606	bool "Enable graphical uboot console on HDMI, LCD or VGA"
607	depends on !MACH_SUN8I_A83T
608	depends on !MACH_SUNXI_H3_H5
609	depends on !MACH_SUN8I_R40
610	depends on !MACH_SUN8I_V3S
611	depends on !MACH_SUN9I
612	depends on !MACH_SUN50I
613	default y
614	---help---
615	Say Y here to add support for using a cfb console on the HDMI, LCD
616	or VGA output found on most sunxi devices. See doc/README.video for
617	info on how to select the video output and mode.
618
619config VIDEO_HDMI
620	bool "HDMI output support"
621	depends on VIDEO && !MACH_SUN8I
622	default y
623	---help---
624	Say Y here to add support for outputting video over HDMI.
625
626config VIDEO_VGA
627	bool "VGA output support"
628	depends on VIDEO && (MACH_SUN4I || MACH_SUN7I)
629	default n
630	---help---
631	Say Y here to add support for outputting video over VGA.
632
633config VIDEO_VGA_VIA_LCD
634	bool "VGA via LCD controller support"
635	depends on VIDEO && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
636	default n
637	---help---
638	Say Y here to add support for external DACs connected to the parallel
639	LCD interface driving a VGA connector, such as found on the
640	Olimex A13 boards.
641
642config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
643	bool "Force sync active high for VGA via LCD controller support"
644	depends on VIDEO_VGA_VIA_LCD
645	default n
646	---help---
647	Say Y here if you've a board which uses opendrain drivers for the vga
648	hsync and vsync signals. Opendrain drivers cannot generate steep enough
649	positive edges for a stable video output, so on boards with opendrain
650	drivers the sync signals must always be active high.
651
652config VIDEO_VGA_EXTERNAL_DAC_EN
653	string "LCD panel power enable pin"
654	depends on VIDEO_VGA_VIA_LCD
655	default ""
656	---help---
657	Set the enable pin for the external VGA DAC. This takes a string in the
658	format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
659
660config VIDEO_COMPOSITE
661	bool "Composite video output support"
662	depends on VIDEO && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
663	default n
664	---help---
665	Say Y here to add support for outputting composite video.
666
667config VIDEO_LCD_MODE
668	string "LCD panel timing details"
669	depends on VIDEO
670	default ""
671	---help---
672	LCD panel timing details string, leave empty if there is no LCD panel.
673	This is in drivers/video/videomodes.c: video_get_params() format, e.g.
674	x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
675	Also see: http://linux-sunxi.org/LCD
676
677config VIDEO_LCD_DCLK_PHASE
678	int "LCD panel display clock phase"
679	depends on VIDEO
680	default 1
681	---help---
682	Select LCD panel display clock phase shift, range 0-3.
683
684config VIDEO_LCD_POWER
685	string "LCD panel power enable pin"
686	depends on VIDEO
687	default ""
688	---help---
689	Set the power enable pin for the LCD panel. This takes a string in the
690	format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
691
692config VIDEO_LCD_RESET
693	string "LCD panel reset pin"
694	depends on VIDEO
695	default ""
696	---help---
697	Set the reset pin for the LCD panel. This takes a string in the format
698	understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
699
700config VIDEO_LCD_BL_EN
701	string "LCD panel backlight enable pin"
702	depends on VIDEO
703	default ""
704	---help---
705	Set the backlight enable pin for the LCD panel. This takes a string in the
706	the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
707	port H.
708
709config VIDEO_LCD_BL_PWM
710	string "LCD panel backlight pwm pin"
711	depends on VIDEO
712	default ""
713	---help---
714	Set the backlight pwm pin for the LCD panel. This takes a string in the
715	format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
716
717config VIDEO_LCD_BL_PWM_ACTIVE_LOW
718	bool "LCD panel backlight pwm is inverted"
719	depends on VIDEO
720	default y
721	---help---
722	Set this if the backlight pwm output is active low.
723
724config VIDEO_LCD_PANEL_I2C
725	bool "LCD panel needs to be configured via i2c"
726	depends on VIDEO
727	default n
728	select CMD_I2C
729	---help---
730	Say y here if the LCD panel needs to be configured via i2c. This
731	will add a bitbang i2c controller using gpios to talk to the LCD.
732
733config VIDEO_LCD_PANEL_I2C_SDA
734	string "LCD panel i2c interface SDA pin"
735	depends on VIDEO_LCD_PANEL_I2C
736	default "PG12"
737	---help---
738	Set the SDA pin for the LCD i2c interface. This takes a string in the
739	format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
740
741config VIDEO_LCD_PANEL_I2C_SCL
742	string "LCD panel i2c interface SCL pin"
743	depends on VIDEO_LCD_PANEL_I2C
744	default "PG10"
745	---help---
746	Set the SCL pin for the LCD i2c interface. This takes a string in the
747	format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
748
749
750# Note only one of these may be selected at a time! But hidden choices are
751# not supported by Kconfig
752config VIDEO_LCD_IF_PARALLEL
753	bool
754
755config VIDEO_LCD_IF_LVDS
756	bool
757
758config SUNXI_DE2
759	bool
760	default n
761
762config VIDEO_DE2
763	bool "Display Engine 2 video driver"
764	depends on SUNXI_DE2
765	select DM_VIDEO
766	select DISPLAY
767	default y
768	---help---
769	Say y here if you want to build DE2 video driver which is present on
770	newer SoCs. Currently only HDMI output is supported.
771
772
773choice
774	prompt "LCD panel support"
775	depends on VIDEO
776	---help---
777	Select which type of LCD panel to support.
778
779config VIDEO_LCD_PANEL_PARALLEL
780	bool "Generic parallel interface LCD panel"
781	select VIDEO_LCD_IF_PARALLEL
782
783config VIDEO_LCD_PANEL_LVDS
784	bool "Generic lvds interface LCD panel"
785	select VIDEO_LCD_IF_LVDS
786
787config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
788	bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
789	select VIDEO_LCD_SSD2828
790	select VIDEO_LCD_IF_PARALLEL
791	---help---
792	7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
793
794config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
795	bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip"
796	select VIDEO_LCD_ANX9804
797	select VIDEO_LCD_IF_PARALLEL
798	select VIDEO_LCD_PANEL_I2C
799	---help---
800	Select this for eDP LCD panels with 4 lanes running at 1.62G,
801	connected via an ANX9804 bridge chip.
802
803config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
804	bool "Hitachi tx18d42vm LCD panel"
805	select VIDEO_LCD_HITACHI_TX18D42VM
806	select VIDEO_LCD_IF_LVDS
807	---help---
808	7.85" 1024x768 Hitachi tx18d42vm LCD panel support
809
810config VIDEO_LCD_TL059WV5C0
811	bool "tl059wv5c0 LCD panel"
812	select VIDEO_LCD_PANEL_I2C
813	select VIDEO_LCD_IF_PARALLEL
814	---help---
815	6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and
816	Aigo M60/M608/M606 tablets.
817
818endchoice
819
820config SATAPWR
821	string "SATA power pin"
822	default ""
823	help
824	  Set the pins used to power the SATA. This takes a string in the
825	  format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
826	  port H.
827
828config GMAC_TX_DELAY
829	int "GMAC Transmit Clock Delay Chain"
830	default 0
831	---help---
832	Set the GMAC Transmit Clock Delay Chain value.
833
834config SPL_STACK_R_ADDR
835	default 0x4fe00000 if MACH_SUN4I
836	default 0x4fe00000 if MACH_SUN5I
837	default 0x4fe00000 if MACH_SUN6I
838	default 0x4fe00000 if MACH_SUN7I
839	default 0x4fe00000 if MACH_SUN8I
840	default 0x2fe00000 if MACH_SUN9I
841	default 0x4fe00000 if MACH_SUN50I
842
843endif
844