xref: /openbmc/u-boot/arch/arm/mach-sunxi/Kconfig (revision b3820ba9)
1if ARCH_SUNXI
2
3config SPL_LDSCRIPT
4	default "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" if !ARM64
5
6config IDENT_STRING
7	default " Allwinner Technology"
8
9config DRAM_SUN4I
10	bool
11	help
12	  Select this dram controller driver for Sun4/5/7i platforms,
13	  like A10/A13/A20.
14
15config DRAM_SUN6I
16	bool
17	help
18	  Select this dram controller driver for Sun6i platforms,
19	  like A31/A31s.
20
21config DRAM_SUN8I_A23
22	bool
23	help
24	  Select this dram controller driver for Sun8i platforms,
25	  for A23 SOC.
26
27config DRAM_SUN8I_A33
28	bool
29	help
30	  Select this dram controller driver for Sun8i platforms,
31	  for A33 SOC.
32
33config DRAM_SUN8I_A83T
34	bool
35	help
36	  Select this dram controller driver for Sun8i platforms,
37	  for A83T SOC.
38
39config DRAM_SUN9I
40	bool
41	help
42	  Select this dram controller driver for Sun9i platforms,
43	  like A80.
44
45config DRAM_SUN50I_H6
46	bool
47	help
48	  Select this dram controller driver for some sun50i platforms,
49	  like H6.
50
51config SUN6I_P2WI
52	bool "Allwinner sun6i internal P2WI controller"
53	help
54	  If you say yes to this option, support will be included for the
55	  P2WI (Push/Pull 2 Wire Interface) controller embedded in some sunxi
56	  SOCs.
57	  The P2WI looks like an SMBus controller (which supports only byte
58	  accesses), except that it only supports one slave device.
59	  This interface is used to connect to specific PMIC devices (like the
60	  AXP221).
61
62config SUN6I_PRCM
63	bool
64	help
65	  Support for the PRCM (Power/Reset/Clock Management) unit available
66	  in A31 SoC.
67
68config AXP_PMIC_BUS
69	bool "Sunxi AXP PMIC bus access helpers"
70	help
71	  Select this PMIC bus access helpers for Sunxi platform PRCM or other
72	  AXP family PMIC devices.
73
74config SUN8I_RSB
75	bool "Allwinner sunXi Reduced Serial Bus Driver"
76	help
77	  Say y here to enable support for Allwinner's Reduced Serial Bus
78	  (RSB) support. This controller is responsible for communicating
79	  with various RSB based devices, such as AXP223, AXP8XX PMICs,
80	  and AC100/AC200 ICs.
81
82config SUNXI_SRAM_ADDRESS
83	hex
84	default 0x10000 if MACH_SUN9I || MACH_SUN50I || MACH_SUN50I_H5
85	default 0x20000 if MACH_SUN50I_H6
86	default 0x0
87	---help---
88	Older Allwinner SoCs have their mask boot ROM mapped just below 4GB,
89	with the first SRAM region being located at address 0.
90	Some newer SoCs map the boot ROM at address 0 instead and move the
91	SRAM to a different address.
92
93config SUNXI_A64_TIMER_ERRATUM
94	bool
95
96# Note only one of these may be selected at a time! But hidden choices are
97# not supported by Kconfig
98config SUNXI_GEN_SUN4I
99	bool
100	---help---
101	Select this for sunxi SoCs which have resets and clocks set up
102	as the original A10 (mach-sun4i).
103
104config SUNXI_GEN_SUN6I
105	bool
106	---help---
107	Select this for sunxi SoCs which have sun6i like periphery, like
108	separate ahb reset control registers, custom pmic bus, new style
109	watchdog, etc.
110
111config SUNXI_DRAM_DW
112	bool
113	---help---
114	Select this for sunxi SoCs which uses a DRAM controller like the
115	DesignWare controller used in H3, mainly SoCs after H3, which do
116	not have official open-source DRAM initialization code, but can
117	use modified H3 DRAM initialization code.
118
119if SUNXI_DRAM_DW
120config SUNXI_DRAM_DW_16BIT
121	bool
122	---help---
123	Select this for sunxi SoCs with DesignWare DRAM controller and
124	have only 16-bit memory buswidth.
125
126config SUNXI_DRAM_DW_32BIT
127	bool
128	---help---
129	Select this for sunxi SoCs with DesignWare DRAM controller with
130	32-bit memory buswidth.
131endif
132
133config MACH_SUNXI_H3_H5
134	bool
135	select DM_I2C
136	select PHY_SUN4I_USB
137	select SUNXI_DE2
138	select SUNXI_DRAM_DW
139	select SUNXI_DRAM_DW_32BIT
140	select SUNXI_GEN_SUN6I
141	select SUPPORT_SPL
142
143# TODO: try out A80's 8GiB DRAM space
144config SUNXI_DRAM_MAX_SIZE
145	hex
146	default 0xC0000000 if MACH_SUN50I || MACH_SUN50I_H5 || MACH_SUN50I_H6
147	default 0x80000000
148
149choice
150	prompt "Sunxi SoC Variant"
151	optional
152
153config MACH_SUN4I
154	bool "sun4i (Allwinner A10)"
155	select CPU_V7A
156	select ARM_CORTEX_CPU_IS_UP
157	select DM_SCSI if SCSI
158	select PHY_SUN4I_USB
159	select DRAM_SUN4I
160	select SUNXI_GEN_SUN4I
161	select SUPPORT_SPL
162
163config MACH_SUN5I
164	bool "sun5i (Allwinner A13)"
165	select CPU_V7A
166	select ARM_CORTEX_CPU_IS_UP
167	select DRAM_SUN4I
168	select PHY_SUN4I_USB
169	select SUNXI_GEN_SUN4I
170	select SUPPORT_SPL
171	imply CONS_INDEX_2 if !DM_SERIAL
172
173config MACH_SUN6I
174	bool "sun6i (Allwinner A31)"
175	select CPU_V7A
176	select CPU_V7_HAS_NONSEC
177	select CPU_V7_HAS_VIRT
178	select ARCH_SUPPORT_PSCI
179	select DRAM_SUN6I
180	select PHY_SUN4I_USB
181	select SUN6I_P2WI
182	select SUN6I_PRCM
183	select SUNXI_GEN_SUN6I
184	select SUPPORT_SPL
185	select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
186
187config MACH_SUN7I
188	bool "sun7i (Allwinner A20)"
189	select CPU_V7A
190	select CPU_V7_HAS_NONSEC
191	select CPU_V7_HAS_VIRT
192	select ARCH_SUPPORT_PSCI
193	select DRAM_SUN4I
194	select PHY_SUN4I_USB
195	select SUNXI_GEN_SUN4I
196	select SUPPORT_SPL
197	select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
198
199config MACH_SUN8I_A23
200	bool "sun8i (Allwinner A23)"
201	select CPU_V7A
202	select CPU_V7_HAS_NONSEC
203	select CPU_V7_HAS_VIRT
204	select ARCH_SUPPORT_PSCI
205	select DRAM_SUN8I_A23
206	select PHY_SUN4I_USB
207	select SUNXI_GEN_SUN6I
208	select SUPPORT_SPL
209	select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
210	imply CONS_INDEX_5 if !DM_SERIAL
211
212config MACH_SUN8I_A33
213	bool "sun8i (Allwinner A33)"
214	select CPU_V7A
215	select CPU_V7_HAS_NONSEC
216	select CPU_V7_HAS_VIRT
217	select ARCH_SUPPORT_PSCI
218	select DRAM_SUN8I_A33
219	select PHY_SUN4I_USB
220	select SUNXI_GEN_SUN6I
221	select SUPPORT_SPL
222	select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
223	imply CONS_INDEX_5 if !DM_SERIAL
224
225config MACH_SUN8I_A83T
226	bool "sun8i (Allwinner A83T)"
227	select CPU_V7A
228	select DRAM_SUN8I_A83T
229	select PHY_SUN4I_USB
230	select SUNXI_GEN_SUN6I
231	select MMC_SUNXI_HAS_NEW_MODE
232	select MMC_SUNXI_HAS_MODE_SWITCH
233	select SUPPORT_SPL
234
235config MACH_SUN8I_H3
236	bool "sun8i (Allwinner H3)"
237	select CPU_V7A
238	select CPU_V7_HAS_NONSEC
239	select CPU_V7_HAS_VIRT
240	select ARCH_SUPPORT_PSCI
241	select MACH_SUNXI_H3_H5
242	select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
243
244config MACH_SUN8I_R40
245	bool "sun8i (Allwinner R40)"
246	select CPU_V7A
247	select CPU_V7_HAS_NONSEC
248	select CPU_V7_HAS_VIRT
249	select ARCH_SUPPORT_PSCI
250	select SUNXI_GEN_SUN6I
251	select SUPPORT_SPL
252	select SUNXI_DRAM_DW
253	select SUNXI_DRAM_DW_32BIT
254
255config MACH_SUN8I_V3S
256	bool "sun8i (Allwinner V3s)"
257	select CPU_V7A
258	select CPU_V7_HAS_NONSEC
259	select CPU_V7_HAS_VIRT
260	select ARCH_SUPPORT_PSCI
261	select SUNXI_GEN_SUN6I
262	select SUNXI_DRAM_DW
263	select SUNXI_DRAM_DW_16BIT
264	select SUPPORT_SPL
265	select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
266
267config MACH_SUN9I
268	bool "sun9i (Allwinner A80)"
269	select CPU_V7A
270	select DRAM_SUN9I
271	select SUN6I_PRCM
272	select SUNXI_GEN_SUN6I
273	select SUN8I_RSB
274	select SUPPORT_SPL
275
276config MACH_SUN50I
277	bool "sun50i (Allwinner A64)"
278	select ARM64
279	select DM_I2C
280	select PHY_SUN4I_USB
281	select SUN6I_PRCM
282	select SUNXI_DE2
283	select SUNXI_GEN_SUN6I
284	select MMC_SUNXI_HAS_NEW_MODE
285	select SUPPORT_SPL
286	select SUNXI_DRAM_DW
287	select SUNXI_DRAM_DW_32BIT
288	select FIT
289	select SPL_LOAD_FIT
290	select SUNXI_A64_TIMER_ERRATUM
291
292config MACH_SUN50I_H5
293	bool "sun50i (Allwinner H5)"
294	select ARM64
295	select MACH_SUNXI_H3_H5
296	select FIT
297	select SPL_LOAD_FIT
298
299config MACH_SUN50I_H6
300	bool "sun50i (Allwinner H6)"
301	select ARM64
302	select SUPPORT_SPL
303	select FIT
304	select SPL_LOAD_FIT
305	select DRAM_SUN50I_H6
306
307endchoice
308
309# The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
310config MACH_SUN8I
311	bool
312	select SUN8I_RSB
313	select SUN6I_PRCM
314	default y if MACH_SUN8I_A23
315	default y if MACH_SUN8I_A33
316	default y if MACH_SUN8I_A83T
317	default y if MACH_SUNXI_H3_H5
318	default y if MACH_SUN8I_R40
319	default y if MACH_SUN8I_V3S
320
321config RESERVE_ALLWINNER_BOOT0_HEADER
322	bool "reserve space for Allwinner boot0 header"
323	select ENABLE_ARM_SOC_BOOT0_HOOK
324	---help---
325	Prepend a 1536 byte (empty) header to the U-Boot image file, to be
326	filled with magic values post build. The Allwinner provided boot0
327	blob relies on this information to load and execute U-Boot.
328	Only needed on 64-bit Allwinner boards so far when using boot0.
329
330config ARM_BOOT_HOOK_RMR
331	bool
332	depends on ARM64
333	default y
334	select ENABLE_ARM_SOC_BOOT0_HOOK
335	---help---
336	Insert some ARM32 code at the very beginning of the U-Boot binary
337	which uses an RMR register write to bring the core into AArch64 mode.
338	The very first instruction acts as a switch, since it's carefully
339	chosen to be a NOP in one mode and a branch in the other, so the
340	code would only be executed if not already in AArch64.
341	This allows both the SPL and the U-Boot proper to be entered in
342	either mode and switch to AArch64 if needed.
343
344if SUNXI_DRAM_DW
345config SUNXI_DRAM_DDR3
346	bool
347
348config SUNXI_DRAM_DDR2
349	bool
350
351config SUNXI_DRAM_LPDDR3
352	bool
353
354choice
355	prompt "DRAM Type and Timing"
356	default SUNXI_DRAM_DDR3_1333 if !MACH_SUN8I_V3S
357	default SUNXI_DRAM_DDR2_V3S if MACH_SUN8I_V3S
358
359config SUNXI_DRAM_DDR3_1333
360	bool "DDR3 1333"
361	select SUNXI_DRAM_DDR3
362	depends on !MACH_SUN8I_V3S
363	---help---
364	This option is the original only supported memory type, which suits
365	many H3/H5/A64 boards available now.
366
367config SUNXI_DRAM_LPDDR3_STOCK
368	bool "LPDDR3 with Allwinner stock configuration"
369	select SUNXI_DRAM_LPDDR3
370	---help---
371	This option is the LPDDR3 timing used by the stock boot0 by
372	Allwinner.
373
374config SUNXI_DRAM_DDR2_V3S
375	bool "DDR2 found in V3s chip"
376	select SUNXI_DRAM_DDR2
377	depends on MACH_SUN8I_V3S
378	---help---
379	This option is only for the DDR2 memory chip which is co-packaged in
380	Allwinner V3s SoC.
381
382endchoice
383endif
384
385config DRAM_TYPE
386	int "sunxi dram type"
387	depends on MACH_SUN8I_A83T
388	default 3
389	---help---
390	Set the dram type, 3: DDR3, 7: LPDDR3
391
392config DRAM_CLK
393	int "sunxi dram clock speed"
394	default 792 if MACH_SUN9I
395	default 648 if MACH_SUN8I_R40
396	default 312 if MACH_SUN6I || MACH_SUN8I
397	default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || \
398		       MACH_SUN8I_V3S
399	default 672 if MACH_SUN50I
400	default 744 if MACH_SUN50I_H6
401	---help---
402	Set the dram clock speed, valid range 240 - 480 (prior to sun9i),
403	must be a multiple of 24. For the sun9i (A80), the tested values
404	(for DDR3-1600) are 312 to 792.
405
406if MACH_SUN5I || MACH_SUN7I
407config DRAM_MBUS_CLK
408	int "sunxi mbus clock speed"
409	default 300
410	---help---
411	Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
412
413endif
414
415config DRAM_ZQ
416	int "sunxi dram zq value"
417	default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
418	default 127 if MACH_SUN7I
419	default 14779 if MACH_SUN8I_V3S
420	default 3881979 if MACH_SUN8I_R40 || MACH_SUN50I_H6
421	default 4145117 if MACH_SUN9I
422	default 3881915 if MACH_SUN50I
423	---help---
424	Set the dram zq value.
425
426config DRAM_ODT_EN
427	bool "sunxi dram odt enable"
428	default y if MACH_SUN8I_A23
429	default y if MACH_SUN8I_R40
430	default y if MACH_SUN50I
431	default y if MACH_SUN50I_H6
432	---help---
433	Select this to enable dram odt (on die termination).
434
435if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
436config DRAM_EMR1
437	int "sunxi dram emr1 value"
438	default 0 if MACH_SUN4I
439	default 4 if MACH_SUN5I || MACH_SUN7I
440	---help---
441	Set the dram controller emr1 value.
442
443config DRAM_TPR3
444	hex "sunxi dram tpr3 value"
445	default 0
446	---help---
447	Set the dram controller tpr3 parameter. This parameter configures
448	the delay on the command lane and also phase shifts, which are
449	applied for sampling incoming read data. The default value 0
450	means that no phase/delay adjustments are necessary. Properly
451	configuring this parameter increases reliability at high DRAM
452	clock speeds.
453
454config DRAM_DQS_GATING_DELAY
455	hex "sunxi dram dqs_gating_delay value"
456	default 0
457	---help---
458	Set the dram controller dqs_gating_delay parmeter. Each byte
459	encodes the DQS gating delay for each byte lane. The delay
460	granularity is 1/4 cycle. For example, the value 0x05060606
461	means that the delay is 5 quarter-cycles for one lane (1.25
462	cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
463	The default value 0 means autodetection. The results of hardware
464	autodetection are not very reliable and depend on the chip
465	temperature (sometimes producing different results on cold start
466	and warm reboot). But the accuracy of hardware autodetection
467	is usually good enough, unless running at really high DRAM
468	clocks speeds (up to 600MHz). If unsure, keep as 0.
469
470choice
471	prompt "sunxi dram timings"
472	default DRAM_TIMINGS_VENDOR_MAGIC
473	---help---
474	Select the timings of the DDR3 chips.
475
476config DRAM_TIMINGS_VENDOR_MAGIC
477	bool "Magic vendor timings from Android"
478	---help---
479	The same DRAM timings as in the Allwinner boot0 bootloader.
480
481config DRAM_TIMINGS_DDR3_1066F_1333H
482	bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
483	---help---
484	Use the timings of the standard JEDEC DDR3-1066F speed bin for
485	DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
486	for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
487	used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
488	or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
489	that down binning to DDR3-1066F is supported (because DDR3-1066F
490	uses a bit faster timings than DDR3-1333H).
491
492config DRAM_TIMINGS_DDR3_800E_1066G_1333J
493	bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
494	---help---
495	Use the timings of the slowest possible JEDEC speed bin for the
496	selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
497	DDR3-800E, DDR3-1066G or DDR3-1333J.
498
499endchoice
500
501endif
502
503if MACH_SUN8I_A23
504config DRAM_ODT_CORRECTION
505	int "sunxi dram odt correction value"
506	default 0
507	---help---
508	Set the dram odt correction value (range -255 - 255). In allwinner
509	fex files, this option is found in bits 8-15 of the u32 odt_en variable
510	in the [dram] section. When bit 31 of the odt_en variable is set
511	then the correction is negative. Usually the value for this is 0.
512endif
513
514config SYS_CLK_FREQ
515	default 1008000000 if MACH_SUN4I
516	default 1008000000 if MACH_SUN5I
517	default 1008000000 if MACH_SUN6I
518	default 912000000 if MACH_SUN7I
519	default 816000000 if MACH_SUN50I || MACH_SUN50I_H5
520	default 1008000000 if MACH_SUN8I
521	default 1008000000 if MACH_SUN9I
522	default 888000000 if MACH_SUN50I_H6
523
524config SYS_CONFIG_NAME
525	default "sun4i" if MACH_SUN4I
526	default "sun5i" if MACH_SUN5I
527	default "sun6i" if MACH_SUN6I
528	default "sun7i" if MACH_SUN7I
529	default "sun8i" if MACH_SUN8I
530	default "sun9i" if MACH_SUN9I
531	default "sun50i" if MACH_SUN50I
532	default "sun50i" if MACH_SUN50I_H6
533
534config SYS_BOARD
535	default "sunxi"
536
537config SYS_SOC
538	default "sunxi"
539
540config UART0_PORT_F
541	bool "UART0 on MicroSD breakout board"
542	default n
543	---help---
544	Repurpose the SD card slot for getting access to the UART0 serial
545	console. Primarily useful only for low level u-boot debugging on
546	tablets, where normal UART0 is difficult to access and requires
547	device disassembly and/or soldering. As the SD card can't be used
548	at the same time, the system can be only booted in the FEL mode.
549	Only enable this if you really know what you are doing.
550
551config OLD_SUNXI_KERNEL_COMPAT
552	bool "Enable workarounds for booting old kernels"
553	default n
554	---help---
555	Set this to enable various workarounds for old kernels, this results in
556	sub-optimal settings for newer kernels, only enable if needed.
557
558config MACPWR
559	string "MAC power pin"
560	default ""
561	help
562	  Set the pin used to power the MAC. This takes a string in the format
563	  understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
564
565config MMC0_CD_PIN
566	string "Card detect pin for mmc0"
567	default "PF6" if MACH_SUN8I_A83T || MACH_SUNXI_H3_H5 || MACH_SUN50I
568	default ""
569	---help---
570	Set the card detect pin for mmc0, leave empty to not use cd. This
571	takes a string in the format understood by sunxi_name_to_gpio, e.g.
572	PH1 for pin 1 of port H.
573
574config MMC1_CD_PIN
575	string "Card detect pin for mmc1"
576	default ""
577	---help---
578	See MMC0_CD_PIN help text.
579
580config MMC2_CD_PIN
581	string "Card detect pin for mmc2"
582	default ""
583	---help---
584	See MMC0_CD_PIN help text.
585
586config MMC3_CD_PIN
587	string "Card detect pin for mmc3"
588	default ""
589	---help---
590	See MMC0_CD_PIN help text.
591
592config MMC1_PINS
593	string "Pins for mmc1"
594	default ""
595	---help---
596	Set the pins used for mmc1, when applicable. This takes a string in the
597	format understood by sunxi_name_to_gpio_bank, e.g. PH for port H.
598
599config MMC2_PINS
600	string "Pins for mmc2"
601	default ""
602	---help---
603	See MMC1_PINS help text.
604
605config MMC3_PINS
606	string "Pins for mmc3"
607	default ""
608	---help---
609	See MMC1_PINS help text.
610
611config MMC_SUNXI_SLOT_EXTRA
612	int "mmc extra slot number"
613	default -1
614	---help---
615	sunxi builds always enable mmc0, some boards also have a second sdcard
616	slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
617	support for this.
618
619config INITIAL_USB_SCAN_DELAY
620	int "delay initial usb scan by x ms to allow builtin devices to init"
621	default 0
622	---help---
623	Some boards have on board usb devices which need longer than the
624	USB spec's 1 second to connect from board powerup. Set this config
625	option to a non 0 value to add an extra delay before the first usb
626	bus scan.
627
628config USB0_VBUS_PIN
629	string "Vbus enable pin for usb0 (otg)"
630	default ""
631	---help---
632	Set the Vbus enable pin for usb0 (otg). This takes a string in the
633	format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
634
635config USB0_VBUS_DET
636	string "Vbus detect pin for usb0 (otg)"
637	default ""
638	---help---
639	Set the Vbus detect pin for usb0 (otg). This takes a string in the
640	format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
641
642config USB0_ID_DET
643	string "ID detect pin for usb0 (otg)"
644	default ""
645	---help---
646	Set the ID detect pin for usb0 (otg). This takes a string in the
647	format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
648
649config USB1_VBUS_PIN
650	string "Vbus enable pin for usb1 (ehci0)"
651	default "PH6" if MACH_SUN4I || MACH_SUN7I
652	default "PH27" if MACH_SUN6I
653	---help---
654	Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
655	a string in the format understood by sunxi_name_to_gpio, e.g.
656	PH1 for pin 1 of port H.
657
658config USB2_VBUS_PIN
659	string "Vbus enable pin for usb2 (ehci1)"
660	default "PH3" if MACH_SUN4I || MACH_SUN7I
661	default "PH24" if MACH_SUN6I
662	---help---
663	See USB1_VBUS_PIN help text.
664
665config USB3_VBUS_PIN
666	string "Vbus enable pin for usb3 (ehci2)"
667	default ""
668	---help---
669	See USB1_VBUS_PIN help text.
670
671config I2C0_ENABLE
672	bool "Enable I2C/TWI controller 0"
673	default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_R40
674	default n if MACH_SUN6I || MACH_SUN8I
675	select CMD_I2C
676	---help---
677	This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
678	its clock and setting up the bus. This is especially useful on devices
679	with slaves connected to the bus or with pins exposed through e.g. an
680	expansion port/header.
681
682config I2C1_ENABLE
683	bool "Enable I2C/TWI controller 1"
684	default n
685	select CMD_I2C
686	---help---
687	See I2C0_ENABLE help text.
688
689config I2C2_ENABLE
690	bool "Enable I2C/TWI controller 2"
691	default n
692	select CMD_I2C
693	---help---
694	See I2C0_ENABLE help text.
695
696if MACH_SUN6I || MACH_SUN7I
697config I2C3_ENABLE
698	bool "Enable I2C/TWI controller 3"
699	default n
700	select CMD_I2C
701	---help---
702	See I2C0_ENABLE help text.
703endif
704
705if SUNXI_GEN_SUN6I
706config R_I2C_ENABLE
707	bool "Enable the PRCM I2C/TWI controller"
708	# This is used for the pmic on H3
709	default y if SY8106A_POWER
710	select CMD_I2C
711	---help---
712	Set this to y to enable the I2C controller which is part of the PRCM.
713endif
714
715if MACH_SUN7I
716config I2C4_ENABLE
717	bool "Enable I2C/TWI controller 4"
718	default n
719	select CMD_I2C
720	---help---
721	See I2C0_ENABLE help text.
722endif
723
724config AXP_GPIO
725	bool "Enable support for gpio-s on axp PMICs"
726	default n
727	---help---
728	Say Y here to enable support for the gpio pins of the axp PMIC ICs.
729
730config VIDEO_SUNXI
731	bool "Enable graphical uboot console on HDMI, LCD or VGA"
732	depends on !MACH_SUN8I_A83T
733	depends on !MACH_SUNXI_H3_H5
734	depends on !MACH_SUN8I_R40
735	depends on !MACH_SUN8I_V3S
736	depends on !MACH_SUN9I
737	depends on !MACH_SUN50I
738	depends on !MACH_SUN50I_H6
739	select VIDEO
740	imply VIDEO_DT_SIMPLEFB
741	default y
742	---help---
743	Say Y here to add support for using a cfb console on the HDMI, LCD
744	or VGA output found on most sunxi devices. See doc/README.video for
745	info on how to select the video output and mode.
746
747config VIDEO_HDMI
748	bool "HDMI output support"
749	depends on VIDEO_SUNXI && !MACH_SUN8I
750	default y
751	---help---
752	Say Y here to add support for outputting video over HDMI.
753
754config VIDEO_VGA
755	bool "VGA output support"
756	depends on VIDEO_SUNXI && (MACH_SUN4I || MACH_SUN7I)
757	default n
758	---help---
759	Say Y here to add support for outputting video over VGA.
760
761config VIDEO_VGA_VIA_LCD
762	bool "VGA via LCD controller support"
763	depends on VIDEO_SUNXI && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
764	default n
765	---help---
766	Say Y here to add support for external DACs connected to the parallel
767	LCD interface driving a VGA connector, such as found on the
768	Olimex A13 boards.
769
770config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
771	bool "Force sync active high for VGA via LCD controller support"
772	depends on VIDEO_VGA_VIA_LCD
773	default n
774	---help---
775	Say Y here if you've a board which uses opendrain drivers for the vga
776	hsync and vsync signals. Opendrain drivers cannot generate steep enough
777	positive edges for a stable video output, so on boards with opendrain
778	drivers the sync signals must always be active high.
779
780config VIDEO_VGA_EXTERNAL_DAC_EN
781	string "LCD panel power enable pin"
782	depends on VIDEO_VGA_VIA_LCD
783	default ""
784	---help---
785	Set the enable pin for the external VGA DAC. This takes a string in the
786	format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
787
788config VIDEO_COMPOSITE
789	bool "Composite video output support"
790	depends on VIDEO_SUNXI && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
791	default n
792	---help---
793	Say Y here to add support for outputting composite video.
794
795config VIDEO_LCD_MODE
796	string "LCD panel timing details"
797	depends on VIDEO_SUNXI
798	default ""
799	---help---
800	LCD panel timing details string, leave empty if there is no LCD panel.
801	This is in drivers/video/videomodes.c: video_get_params() format, e.g.
802	x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
803	Also see: http://linux-sunxi.org/LCD
804
805config VIDEO_LCD_DCLK_PHASE
806	int "LCD panel display clock phase"
807	depends on VIDEO_SUNXI || DM_VIDEO
808	default 1
809	---help---
810	Select LCD panel display clock phase shift, range 0-3.
811
812config VIDEO_LCD_POWER
813	string "LCD panel power enable pin"
814	depends on VIDEO_SUNXI
815	default ""
816	---help---
817	Set the power enable pin for the LCD panel. This takes a string in the
818	format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
819
820config VIDEO_LCD_RESET
821	string "LCD panel reset pin"
822	depends on VIDEO_SUNXI
823	default ""
824	---help---
825	Set the reset pin for the LCD panel. This takes a string in the format
826	understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
827
828config VIDEO_LCD_BL_EN
829	string "LCD panel backlight enable pin"
830	depends on VIDEO_SUNXI
831	default ""
832	---help---
833	Set the backlight enable pin for the LCD panel. This takes a string in the
834	the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
835	port H.
836
837config VIDEO_LCD_BL_PWM
838	string "LCD panel backlight pwm pin"
839	depends on VIDEO_SUNXI
840	default ""
841	---help---
842	Set the backlight pwm pin for the LCD panel. This takes a string in the
843	format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
844
845config VIDEO_LCD_BL_PWM_ACTIVE_LOW
846	bool "LCD panel backlight pwm is inverted"
847	depends on VIDEO_SUNXI
848	default y
849	---help---
850	Set this if the backlight pwm output is active low.
851
852config VIDEO_LCD_PANEL_I2C
853	bool "LCD panel needs to be configured via i2c"
854	depends on VIDEO_SUNXI
855	default n
856	select CMD_I2C
857	---help---
858	Say y here if the LCD panel needs to be configured via i2c. This
859	will add a bitbang i2c controller using gpios to talk to the LCD.
860
861config VIDEO_LCD_PANEL_I2C_SDA
862	string "LCD panel i2c interface SDA pin"
863	depends on VIDEO_LCD_PANEL_I2C
864	default "PG12"
865	---help---
866	Set the SDA pin for the LCD i2c interface. This takes a string in the
867	format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
868
869config VIDEO_LCD_PANEL_I2C_SCL
870	string "LCD panel i2c interface SCL pin"
871	depends on VIDEO_LCD_PANEL_I2C
872	default "PG10"
873	---help---
874	Set the SCL pin for the LCD i2c interface. This takes a string in the
875	format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
876
877
878# Note only one of these may be selected at a time! But hidden choices are
879# not supported by Kconfig
880config VIDEO_LCD_IF_PARALLEL
881	bool
882
883config VIDEO_LCD_IF_LVDS
884	bool
885
886config SUNXI_DE2
887	bool
888	default n
889
890config VIDEO_DE2
891	bool "Display Engine 2 video driver"
892	depends on SUNXI_DE2
893	select DM_VIDEO
894	select DISPLAY
895	imply VIDEO_DT_SIMPLEFB
896	default y
897	---help---
898	Say y here if you want to build DE2 video driver which is present on
899	newer SoCs. Currently only HDMI output is supported.
900
901
902choice
903	prompt "LCD panel support"
904	depends on VIDEO_SUNXI
905	---help---
906	Select which type of LCD panel to support.
907
908config VIDEO_LCD_PANEL_PARALLEL
909	bool "Generic parallel interface LCD panel"
910	select VIDEO_LCD_IF_PARALLEL
911
912config VIDEO_LCD_PANEL_LVDS
913	bool "Generic lvds interface LCD panel"
914	select VIDEO_LCD_IF_LVDS
915
916config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
917	bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
918	select VIDEO_LCD_SSD2828
919	select VIDEO_LCD_IF_PARALLEL
920	---help---
921	7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
922
923config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
924	bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip"
925	select VIDEO_LCD_ANX9804
926	select VIDEO_LCD_IF_PARALLEL
927	select VIDEO_LCD_PANEL_I2C
928	---help---
929	Select this for eDP LCD panels with 4 lanes running at 1.62G,
930	connected via an ANX9804 bridge chip.
931
932config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
933	bool "Hitachi tx18d42vm LCD panel"
934	select VIDEO_LCD_HITACHI_TX18D42VM
935	select VIDEO_LCD_IF_LVDS
936	---help---
937	7.85" 1024x768 Hitachi tx18d42vm LCD panel support
938
939config VIDEO_LCD_TL059WV5C0
940	bool "tl059wv5c0 LCD panel"
941	select VIDEO_LCD_PANEL_I2C
942	select VIDEO_LCD_IF_PARALLEL
943	---help---
944	6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and
945	Aigo M60/M608/M606 tablets.
946
947endchoice
948
949config SATAPWR
950	string "SATA power pin"
951	default ""
952	help
953	  Set the pins used to power the SATA. This takes a string in the
954	  format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
955	  port H.
956
957config GMAC_TX_DELAY
958	int "GMAC Transmit Clock Delay Chain"
959	default 0
960	---help---
961	Set the GMAC Transmit Clock Delay Chain value.
962
963config SPL_STACK_R_ADDR
964	default 0x4fe00000 if MACH_SUN4I
965	default 0x4fe00000 if MACH_SUN5I
966	default 0x4fe00000 if MACH_SUN6I
967	default 0x4fe00000 if MACH_SUN7I
968	default 0x4fe00000 if MACH_SUN8I
969	default 0x2fe00000 if MACH_SUN9I
970	default 0x4fe00000 if MACH_SUN50I
971	default 0x4fe00000 if MACH_SUN50I_H6
972
973config SPL_SPI_SUNXI
974	bool "Support for SPI Flash on Allwinner SoCs in SPL"
975	depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I
976	help
977	  Enable support for SPI Flash. This option allows SPL to read from
978	  sunxi SPI Flash. It uses the same method as the boot ROM, so does
979	  not need any extra configuration.
980
981config PINE64_DT_SELECTION
982	bool "Enable Pine64 device tree selection code"
983	depends on MACH_SUN50I
984	help
985	  The original Pine A64 and Pine A64+ are similar but different
986	  boards and can be differed by the DRAM size. Pine A64 has
987	  512MiB DRAM, and Pine A64+ has 1GiB or 2GiB. By selecting this
988	  option, the device tree selection code specific to Pine64 which
989	  utilizes the DRAM size will be enabled.
990
991endif
992