1if ARCH_SUNXI 2 3config IDENT_STRING 4 default " Allwinner Technology" 5 6config SUNXI_HIGH_SRAM 7 bool 8 default n 9 ---help--- 10 Older Allwinner SoCs have their mask boot ROM mapped just below 4GB, 11 with the first SRAM region being located at address 0. 12 Some newer SoCs map the boot ROM at address 0 instead and move the 13 SRAM to 64KB, just behind the mask ROM. 14 Chips using the latter setup are supposed to select this option to 15 adjust the addresses accordingly. 16 17# Note only one of these may be selected at a time! But hidden choices are 18# not supported by Kconfig 19config SUNXI_GEN_SUN4I 20 bool 21 ---help--- 22 Select this for sunxi SoCs which have resets and clocks set up 23 as the original A10 (mach-sun4i). 24 25config SUNXI_GEN_SUN6I 26 bool 27 ---help--- 28 Select this for sunxi SoCs which have sun6i like periphery, like 29 separate ahb reset control registers, custom pmic bus, new style 30 watchdog, etc. 31 32config SUNXI_DRAM_DW 33 bool 34 ---help--- 35 Select this for sunxi SoCs which uses a DRAM controller like the 36 DesignWare controller used in H3, mainly SoCs after H3, which do 37 not have official open-source DRAM initialization code, but can 38 use modified H3 DRAM initialization code. 39 40config MACH_SUNXI_H3_H5 41 bool 42 select DM_I2C 43 select SUNXI_DE2 44 select SUNXI_DRAM_DW 45 select SUNXI_GEN_SUN6I 46 select SUPPORT_SPL 47 48choice 49 prompt "Sunxi SoC Variant" 50 optional 51 52config MACH_SUN4I 53 bool "sun4i (Allwinner A10)" 54 select CPU_V7 55 select ARM_CORTEX_CPU_IS_UP 56 select SUNXI_GEN_SUN4I 57 select SUPPORT_SPL 58 59config MACH_SUN5I 60 bool "sun5i (Allwinner A13)" 61 select CPU_V7 62 select ARM_CORTEX_CPU_IS_UP 63 select SUNXI_GEN_SUN4I 64 select SUPPORT_SPL 65 66config MACH_SUN6I 67 bool "sun6i (Allwinner A31)" 68 select CPU_V7 69 select CPU_V7_HAS_NONSEC 70 select CPU_V7_HAS_VIRT 71 select ARCH_SUPPORT_PSCI 72 select SUNXI_GEN_SUN6I 73 select SUPPORT_SPL 74 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT 75 76config MACH_SUN7I 77 bool "sun7i (Allwinner A20)" 78 select CPU_V7 79 select CPU_V7_HAS_NONSEC 80 select CPU_V7_HAS_VIRT 81 select ARCH_SUPPORT_PSCI 82 select SUNXI_GEN_SUN4I 83 select SUPPORT_SPL 84 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT 85 86config MACH_SUN8I_A23 87 bool "sun8i (Allwinner A23)" 88 select CPU_V7 89 select CPU_V7_HAS_NONSEC 90 select CPU_V7_HAS_VIRT 91 select ARCH_SUPPORT_PSCI 92 select SUNXI_GEN_SUN6I 93 select SUPPORT_SPL 94 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT 95 96config MACH_SUN8I_A33 97 bool "sun8i (Allwinner A33)" 98 select CPU_V7 99 select CPU_V7_HAS_NONSEC 100 select CPU_V7_HAS_VIRT 101 select ARCH_SUPPORT_PSCI 102 select SUNXI_GEN_SUN6I 103 select SUPPORT_SPL 104 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT 105 106config MACH_SUN8I_A83T 107 bool "sun8i (Allwinner A83T)" 108 select CPU_V7 109 select SUNXI_GEN_SUN6I 110 select SUPPORT_SPL 111 112config MACH_SUN8I_H3 113 bool "sun8i (Allwinner H3)" 114 select CPU_V7 115 select CPU_V7_HAS_NONSEC 116 select CPU_V7_HAS_VIRT 117 select ARCH_SUPPORT_PSCI 118 select MACH_SUNXI_H3_H5 119 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT 120 121config MACH_SUN8I_R40 122 bool "sun8i (Allwinner R40)" 123 select CPU_V7 124 select CPU_V7_HAS_NONSEC 125 select CPU_V7_HAS_VIRT 126 select ARCH_SUPPORT_PSCI 127 select SUNXI_GEN_SUN6I 128 select SUPPORT_SPL 129 select SUNXI_DRAM_DW 130 131config MACH_SUN8I_V3S 132 bool "sun8i (Allwinner V3s)" 133 select CPU_V7 134 select CPU_V7_HAS_NONSEC 135 select CPU_V7_HAS_VIRT 136 select ARCH_SUPPORT_PSCI 137 select SUNXI_GEN_SUN6I 138 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT 139 140config MACH_SUN9I 141 bool "sun9i (Allwinner A80)" 142 select CPU_V7 143 select SUNXI_HIGH_SRAM 144 select SUNXI_GEN_SUN6I 145 select SUPPORT_SPL 146 147config MACH_SUN50I 148 bool "sun50i (Allwinner A64)" 149 select ARM64 150 select DM_I2C 151 select SUNXI_DE2 152 select SUNXI_GEN_SUN6I 153 select SUNXI_HIGH_SRAM 154 select SUPPORT_SPL 155 select SUNXI_DRAM_DW 156 select FIT 157 select SPL_LOAD_FIT 158 159config MACH_SUN50I_H5 160 bool "sun50i (Allwinner H5)" 161 select ARM64 162 select MACH_SUNXI_H3_H5 163 select SUNXI_HIGH_SRAM 164 select FIT 165 select SPL_LOAD_FIT 166 167endchoice 168 169# The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33" 170config MACH_SUN8I 171 bool 172 default y if MACH_SUN8I_A23 173 default y if MACH_SUN8I_A33 174 default y if MACH_SUN8I_A83T 175 default y if MACH_SUNXI_H3_H5 176 default y if MACH_SUN8I_R40 177 default y if MACH_SUN8I_V3S 178 179config RESERVE_ALLWINNER_BOOT0_HEADER 180 bool "reserve space for Allwinner boot0 header" 181 select ENABLE_ARM_SOC_BOOT0_HOOK 182 ---help--- 183 Prepend a 1536 byte (empty) header to the U-Boot image file, to be 184 filled with magic values post build. The Allwinner provided boot0 185 blob relies on this information to load and execute U-Boot. 186 Only needed on 64-bit Allwinner boards so far when using boot0. 187 188config ARM_BOOT_HOOK_RMR 189 bool 190 depends on ARM64 191 default y 192 select ENABLE_ARM_SOC_BOOT0_HOOK 193 ---help--- 194 Insert some ARM32 code at the very beginning of the U-Boot binary 195 which uses an RMR register write to bring the core into AArch64 mode. 196 The very first instruction acts as a switch, since it's carefully 197 chosen to be a NOP in one mode and a branch in the other, so the 198 code would only be executed if not already in AArch64. 199 This allows both the SPL and the U-Boot proper to be entered in 200 either mode and switch to AArch64 if needed. 201 202config DRAM_TYPE 203 int "sunxi dram type" 204 depends on MACH_SUN8I_A83T 205 default 3 206 ---help--- 207 Set the dram type, 3: DDR3, 7: LPDDR3 208 209config DRAM_CLK 210 int "sunxi dram clock speed" 211 default 792 if MACH_SUN9I 212 default 648 if MACH_SUN8I_R40 213 default 312 if MACH_SUN6I || MACH_SUN8I 214 default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I 215 default 672 if MACH_SUN50I 216 ---help--- 217 Set the dram clock speed, valid range 240 - 480 (prior to sun9i), 218 must be a multiple of 24. For the sun9i (A80), the tested values 219 (for DDR3-1600) are 312 to 792. 220 221if MACH_SUN5I || MACH_SUN7I 222config DRAM_MBUS_CLK 223 int "sunxi mbus clock speed" 224 default 300 225 ---help--- 226 Set the mbus clock speed. The maximum on sun5i hardware is 300MHz. 227 228endif 229 230config DRAM_ZQ 231 int "sunxi dram zq value" 232 default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I 233 default 127 if MACH_SUN7I 234 default 3881979 if MACH_SUN8I_R40 235 default 4145117 if MACH_SUN9I 236 default 3881915 if MACH_SUN50I 237 ---help--- 238 Set the dram zq value. 239 240config DRAM_ODT_EN 241 bool "sunxi dram odt enable" 242 default n if !MACH_SUN8I_A23 243 default y if MACH_SUN8I_A23 244 default y if MACH_SUN8I_R40 245 default y if MACH_SUN50I 246 ---help--- 247 Select this to enable dram odt (on die termination). 248 249if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I 250config DRAM_EMR1 251 int "sunxi dram emr1 value" 252 default 0 if MACH_SUN4I 253 default 4 if MACH_SUN5I || MACH_SUN7I 254 ---help--- 255 Set the dram controller emr1 value. 256 257config DRAM_TPR3 258 hex "sunxi dram tpr3 value" 259 default 0 260 ---help--- 261 Set the dram controller tpr3 parameter. This parameter configures 262 the delay on the command lane and also phase shifts, which are 263 applied for sampling incoming read data. The default value 0 264 means that no phase/delay adjustments are necessary. Properly 265 configuring this parameter increases reliability at high DRAM 266 clock speeds. 267 268config DRAM_DQS_GATING_DELAY 269 hex "sunxi dram dqs_gating_delay value" 270 default 0 271 ---help--- 272 Set the dram controller dqs_gating_delay parmeter. Each byte 273 encodes the DQS gating delay for each byte lane. The delay 274 granularity is 1/4 cycle. For example, the value 0x05060606 275 means that the delay is 5 quarter-cycles for one lane (1.25 276 cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes. 277 The default value 0 means autodetection. The results of hardware 278 autodetection are not very reliable and depend on the chip 279 temperature (sometimes producing different results on cold start 280 and warm reboot). But the accuracy of hardware autodetection 281 is usually good enough, unless running at really high DRAM 282 clocks speeds (up to 600MHz). If unsure, keep as 0. 283 284choice 285 prompt "sunxi dram timings" 286 default DRAM_TIMINGS_VENDOR_MAGIC 287 ---help--- 288 Select the timings of the DDR3 chips. 289 290config DRAM_TIMINGS_VENDOR_MAGIC 291 bool "Magic vendor timings from Android" 292 ---help--- 293 The same DRAM timings as in the Allwinner boot0 bootloader. 294 295config DRAM_TIMINGS_DDR3_1066F_1333H 296 bool "JEDEC DDR3-1333H with down binning to DDR3-1066F" 297 ---help--- 298 Use the timings of the standard JEDEC DDR3-1066F speed bin for 299 DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin 300 for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips 301 used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333 302 or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm 303 that down binning to DDR3-1066F is supported (because DDR3-1066F 304 uses a bit faster timings than DDR3-1333H). 305 306config DRAM_TIMINGS_DDR3_800E_1066G_1333J 307 bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J" 308 ---help--- 309 Use the timings of the slowest possible JEDEC speed bin for the 310 selected DRAM_CLK. Depending on the DRAM_CLK value, it may be 311 DDR3-800E, DDR3-1066G or DDR3-1333J. 312 313endchoice 314 315endif 316 317if MACH_SUN8I_A23 318config DRAM_ODT_CORRECTION 319 int "sunxi dram odt correction value" 320 default 0 321 ---help--- 322 Set the dram odt correction value (range -255 - 255). In allwinner 323 fex files, this option is found in bits 8-15 of the u32 odt_en variable 324 in the [dram] section. When bit 31 of the odt_en variable is set 325 then the correction is negative. Usually the value for this is 0. 326endif 327 328config SYS_CLK_FREQ 329 default 1008000000 if MACH_SUN4I 330 default 1008000000 if MACH_SUN5I 331 default 1008000000 if MACH_SUN6I 332 default 912000000 if MACH_SUN7I 333 default 1008000000 if MACH_SUN8I 334 default 1008000000 if MACH_SUN9I 335 default 816000000 if MACH_SUN50I 336 337config SYS_CONFIG_NAME 338 default "sun4i" if MACH_SUN4I 339 default "sun5i" if MACH_SUN5I 340 default "sun6i" if MACH_SUN6I 341 default "sun7i" if MACH_SUN7I 342 default "sun8i" if MACH_SUN8I 343 default "sun9i" if MACH_SUN9I 344 default "sun50i" if MACH_SUN50I 345 346config SYS_BOARD 347 default "sunxi" 348 349config SYS_SOC 350 default "sunxi" 351 352config UART0_PORT_F 353 bool "UART0 on MicroSD breakout board" 354 default n 355 ---help--- 356 Repurpose the SD card slot for getting access to the UART0 serial 357 console. Primarily useful only for low level u-boot debugging on 358 tablets, where normal UART0 is difficult to access and requires 359 device disassembly and/or soldering. As the SD card can't be used 360 at the same time, the system can be only booted in the FEL mode. 361 Only enable this if you really know what you are doing. 362 363config OLD_SUNXI_KERNEL_COMPAT 364 bool "Enable workarounds for booting old kernels" 365 default n 366 ---help--- 367 Set this to enable various workarounds for old kernels, this results in 368 sub-optimal settings for newer kernels, only enable if needed. 369 370config MACPWR 371 string "MAC power pin" 372 default "" 373 help 374 Set the pin used to power the MAC. This takes a string in the format 375 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. 376 377config MMC0_CD_PIN 378 string "Card detect pin for mmc0" 379 default "PF6" if MACH_SUN8I_A83T || MACH_SUNXI_H3_H5 || MACH_SUN50I 380 default "" 381 ---help--- 382 Set the card detect pin for mmc0, leave empty to not use cd. This 383 takes a string in the format understood by sunxi_name_to_gpio, e.g. 384 PH1 for pin 1 of port H. 385 386config MMC1_CD_PIN 387 string "Card detect pin for mmc1" 388 default "" 389 ---help--- 390 See MMC0_CD_PIN help text. 391 392config MMC2_CD_PIN 393 string "Card detect pin for mmc2" 394 default "" 395 ---help--- 396 See MMC0_CD_PIN help text. 397 398config MMC3_CD_PIN 399 string "Card detect pin for mmc3" 400 default "" 401 ---help--- 402 See MMC0_CD_PIN help text. 403 404config MMC1_PINS 405 string "Pins for mmc1" 406 default "" 407 ---help--- 408 Set the pins used for mmc1, when applicable. This takes a string in the 409 format understood by sunxi_name_to_gpio_bank, e.g. PH for port H. 410 411config MMC2_PINS 412 string "Pins for mmc2" 413 default "" 414 ---help--- 415 See MMC1_PINS help text. 416 417config MMC3_PINS 418 string "Pins for mmc3" 419 default "" 420 ---help--- 421 See MMC1_PINS help text. 422 423config MMC_SUNXI_SLOT_EXTRA 424 int "mmc extra slot number" 425 default -1 426 ---help--- 427 sunxi builds always enable mmc0, some boards also have a second sdcard 428 slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable 429 support for this. 430 431config INITIAL_USB_SCAN_DELAY 432 int "delay initial usb scan by x ms to allow builtin devices to init" 433 default 0 434 ---help--- 435 Some boards have on board usb devices which need longer than the 436 USB spec's 1 second to connect from board powerup. Set this config 437 option to a non 0 value to add an extra delay before the first usb 438 bus scan. 439 440config USB0_VBUS_PIN 441 string "Vbus enable pin for usb0 (otg)" 442 default "" 443 ---help--- 444 Set the Vbus enable pin for usb0 (otg). This takes a string in the 445 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. 446 447config USB0_VBUS_DET 448 string "Vbus detect pin for usb0 (otg)" 449 default "" 450 ---help--- 451 Set the Vbus detect pin for usb0 (otg). This takes a string in the 452 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. 453 454config USB0_ID_DET 455 string "ID detect pin for usb0 (otg)" 456 default "" 457 ---help--- 458 Set the ID detect pin for usb0 (otg). This takes a string in the 459 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. 460 461config USB1_VBUS_PIN 462 string "Vbus enable pin for usb1 (ehci0)" 463 default "PH6" if MACH_SUN4I || MACH_SUN7I 464 default "PH27" if MACH_SUN6I 465 ---help--- 466 Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes 467 a string in the format understood by sunxi_name_to_gpio, e.g. 468 PH1 for pin 1 of port H. 469 470config USB2_VBUS_PIN 471 string "Vbus enable pin for usb2 (ehci1)" 472 default "PH3" if MACH_SUN4I || MACH_SUN7I 473 default "PH24" if MACH_SUN6I 474 ---help--- 475 See USB1_VBUS_PIN help text. 476 477config USB3_VBUS_PIN 478 string "Vbus enable pin for usb3 (ehci2)" 479 default "" 480 ---help--- 481 See USB1_VBUS_PIN help text. 482 483config I2C0_ENABLE 484 bool "Enable I2C/TWI controller 0" 485 default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_R40 486 default n if MACH_SUN6I || MACH_SUN8I 487 select CMD_I2C 488 ---help--- 489 This allows enabling I2C/TWI controller 0 by muxing its pins, enabling 490 its clock and setting up the bus. This is especially useful on devices 491 with slaves connected to the bus or with pins exposed through e.g. an 492 expansion port/header. 493 494config I2C1_ENABLE 495 bool "Enable I2C/TWI controller 1" 496 default n 497 select CMD_I2C 498 ---help--- 499 See I2C0_ENABLE help text. 500 501config I2C2_ENABLE 502 bool "Enable I2C/TWI controller 2" 503 default n 504 select CMD_I2C 505 ---help--- 506 See I2C0_ENABLE help text. 507 508if MACH_SUN6I || MACH_SUN7I 509config I2C3_ENABLE 510 bool "Enable I2C/TWI controller 3" 511 default n 512 select CMD_I2C 513 ---help--- 514 See I2C0_ENABLE help text. 515endif 516 517if SUNXI_GEN_SUN6I 518config R_I2C_ENABLE 519 bool "Enable the PRCM I2C/TWI controller" 520 # This is used for the pmic on H3 521 default y if SY8106A_POWER 522 select CMD_I2C 523 ---help--- 524 Set this to y to enable the I2C controller which is part of the PRCM. 525endif 526 527if MACH_SUN7I 528config I2C4_ENABLE 529 bool "Enable I2C/TWI controller 4" 530 default n 531 select CMD_I2C 532 ---help--- 533 See I2C0_ENABLE help text. 534endif 535 536config AXP_GPIO 537 bool "Enable support for gpio-s on axp PMICs" 538 default n 539 ---help--- 540 Say Y here to enable support for the gpio pins of the axp PMIC ICs. 541 542config VIDEO 543 bool "Enable graphical uboot console on HDMI, LCD or VGA" 544 depends on !MACH_SUN8I_A83T 545 depends on !MACH_SUNXI_H3_H5 546 depends on !MACH_SUN8I_R40 547 depends on !MACH_SUN8I_V3S 548 depends on !MACH_SUN9I 549 depends on !MACH_SUN50I 550 default y 551 ---help--- 552 Say Y here to add support for using a cfb console on the HDMI, LCD 553 or VGA output found on most sunxi devices. See doc/README.video for 554 info on how to select the video output and mode. 555 556config VIDEO_HDMI 557 bool "HDMI output support" 558 depends on VIDEO && !MACH_SUN8I 559 default y 560 ---help--- 561 Say Y here to add support for outputting video over HDMI. 562 563config VIDEO_VGA 564 bool "VGA output support" 565 depends on VIDEO && (MACH_SUN4I || MACH_SUN7I) 566 default n 567 ---help--- 568 Say Y here to add support for outputting video over VGA. 569 570config VIDEO_VGA_VIA_LCD 571 bool "VGA via LCD controller support" 572 depends on VIDEO && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I) 573 default n 574 ---help--- 575 Say Y here to add support for external DACs connected to the parallel 576 LCD interface driving a VGA connector, such as found on the 577 Olimex A13 boards. 578 579config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH 580 bool "Force sync active high for VGA via LCD controller support" 581 depends on VIDEO_VGA_VIA_LCD 582 default n 583 ---help--- 584 Say Y here if you've a board which uses opendrain drivers for the vga 585 hsync and vsync signals. Opendrain drivers cannot generate steep enough 586 positive edges for a stable video output, so on boards with opendrain 587 drivers the sync signals must always be active high. 588 589config VIDEO_VGA_EXTERNAL_DAC_EN 590 string "LCD panel power enable pin" 591 depends on VIDEO_VGA_VIA_LCD 592 default "" 593 ---help--- 594 Set the enable pin for the external VGA DAC. This takes a string in the 595 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. 596 597config VIDEO_COMPOSITE 598 bool "Composite video output support" 599 depends on VIDEO && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I) 600 default n 601 ---help--- 602 Say Y here to add support for outputting composite video. 603 604config VIDEO_LCD_MODE 605 string "LCD panel timing details" 606 depends on VIDEO 607 default "" 608 ---help--- 609 LCD panel timing details string, leave empty if there is no LCD panel. 610 This is in drivers/video/videomodes.c: video_get_params() format, e.g. 611 x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0 612 Also see: http://linux-sunxi.org/LCD 613 614config VIDEO_LCD_DCLK_PHASE 615 int "LCD panel display clock phase" 616 depends on VIDEO 617 default 1 618 ---help--- 619 Select LCD panel display clock phase shift, range 0-3. 620 621config VIDEO_LCD_POWER 622 string "LCD panel power enable pin" 623 depends on VIDEO 624 default "" 625 ---help--- 626 Set the power enable pin for the LCD panel. This takes a string in the 627 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. 628 629config VIDEO_LCD_RESET 630 string "LCD panel reset pin" 631 depends on VIDEO 632 default "" 633 ---help--- 634 Set the reset pin for the LCD panel. This takes a string in the format 635 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. 636 637config VIDEO_LCD_BL_EN 638 string "LCD panel backlight enable pin" 639 depends on VIDEO 640 default "" 641 ---help--- 642 Set the backlight enable pin for the LCD panel. This takes a string in the 643 the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of 644 port H. 645 646config VIDEO_LCD_BL_PWM 647 string "LCD panel backlight pwm pin" 648 depends on VIDEO 649 default "" 650 ---help--- 651 Set the backlight pwm pin for the LCD panel. This takes a string in the 652 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. 653 654config VIDEO_LCD_BL_PWM_ACTIVE_LOW 655 bool "LCD panel backlight pwm is inverted" 656 depends on VIDEO 657 default y 658 ---help--- 659 Set this if the backlight pwm output is active low. 660 661config VIDEO_LCD_PANEL_I2C 662 bool "LCD panel needs to be configured via i2c" 663 depends on VIDEO 664 default n 665 select CMD_I2C 666 ---help--- 667 Say y here if the LCD panel needs to be configured via i2c. This 668 will add a bitbang i2c controller using gpios to talk to the LCD. 669 670config VIDEO_LCD_PANEL_I2C_SDA 671 string "LCD panel i2c interface SDA pin" 672 depends on VIDEO_LCD_PANEL_I2C 673 default "PG12" 674 ---help--- 675 Set the SDA pin for the LCD i2c interface. This takes a string in the 676 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. 677 678config VIDEO_LCD_PANEL_I2C_SCL 679 string "LCD panel i2c interface SCL pin" 680 depends on VIDEO_LCD_PANEL_I2C 681 default "PG10" 682 ---help--- 683 Set the SCL pin for the LCD i2c interface. This takes a string in the 684 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. 685 686 687# Note only one of these may be selected at a time! But hidden choices are 688# not supported by Kconfig 689config VIDEO_LCD_IF_PARALLEL 690 bool 691 692config VIDEO_LCD_IF_LVDS 693 bool 694 695config SUNXI_DE2 696 bool 697 default n 698 699config VIDEO_DE2 700 bool "Display Engine 2 video driver" 701 depends on SUNXI_DE2 702 select DM_VIDEO 703 select DISPLAY 704 default y 705 ---help--- 706 Say y here if you want to build DE2 video driver which is present on 707 newer SoCs. Currently only HDMI output is supported. 708 709 710choice 711 prompt "LCD panel support" 712 depends on VIDEO 713 ---help--- 714 Select which type of LCD panel to support. 715 716config VIDEO_LCD_PANEL_PARALLEL 717 bool "Generic parallel interface LCD panel" 718 select VIDEO_LCD_IF_PARALLEL 719 720config VIDEO_LCD_PANEL_LVDS 721 bool "Generic lvds interface LCD panel" 722 select VIDEO_LCD_IF_LVDS 723 724config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828 725 bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip" 726 select VIDEO_LCD_SSD2828 727 select VIDEO_LCD_IF_PARALLEL 728 ---help--- 729 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0 730 731config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804 732 bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip" 733 select VIDEO_LCD_ANX9804 734 select VIDEO_LCD_IF_PARALLEL 735 select VIDEO_LCD_PANEL_I2C 736 ---help--- 737 Select this for eDP LCD panels with 4 lanes running at 1.62G, 738 connected via an ANX9804 bridge chip. 739 740config VIDEO_LCD_PANEL_HITACHI_TX18D42VM 741 bool "Hitachi tx18d42vm LCD panel" 742 select VIDEO_LCD_HITACHI_TX18D42VM 743 select VIDEO_LCD_IF_LVDS 744 ---help--- 745 7.85" 1024x768 Hitachi tx18d42vm LCD panel support 746 747config VIDEO_LCD_TL059WV5C0 748 bool "tl059wv5c0 LCD panel" 749 select VIDEO_LCD_PANEL_I2C 750 select VIDEO_LCD_IF_PARALLEL 751 ---help--- 752 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and 753 Aigo M60/M608/M606 tablets. 754 755endchoice 756 757config SATAPWR 758 string "SATA power pin" 759 default "" 760 help 761 Set the pins used to power the SATA. This takes a string in the 762 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of 763 port H. 764 765config GMAC_TX_DELAY 766 int "GMAC Transmit Clock Delay Chain" 767 default 0 768 ---help--- 769 Set the GMAC Transmit Clock Delay Chain value. 770 771config SPL_STACK_R_ADDR 772 default 0x4fe00000 if MACH_SUN4I 773 default 0x4fe00000 if MACH_SUN5I 774 default 0x4fe00000 if MACH_SUN6I 775 default 0x4fe00000 if MACH_SUN7I 776 default 0x4fe00000 if MACH_SUN8I 777 default 0x2fe00000 if MACH_SUN9I 778 default 0x4fe00000 if MACH_SUN50I 779 780endif 781