xref: /openbmc/u-boot/arch/arm/mach-sunxi/Kconfig (revision 8eef803a)
1if ARCH_SUNXI
2
3config SPL_LDSCRIPT
4	default "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" if !ARM64
5
6config IDENT_STRING
7	default " Allwinner Technology"
8
9config DRAM_SUN4I
10	bool
11	help
12	  Select this dram controller driver for Sun4/5/7i platforms,
13	  like A10/A13/A20.
14
15config DRAM_SUN6I
16	bool
17	help
18	  Select this dram controller driver for Sun6i platforms,
19	  like A31/A31s.
20
21config DRAM_SUN8I_A23
22	bool
23	help
24	  Select this dram controller driver for Sun8i platforms,
25	  for A23 SOC.
26
27config DRAM_SUN8I_A33
28	bool
29	help
30	  Select this dram controller driver for Sun8i platforms,
31	  for A33 SOC.
32
33config DRAM_SUN8I_A83T
34	bool
35	help
36	  Select this dram controller driver for Sun8i platforms,
37	  for A83T SOC.
38
39config DRAM_SUN9I
40	bool
41	help
42	  Select this dram controller driver for Sun9i platforms,
43	  like A80.
44
45config DRAM_SUN50I_H6
46	bool
47	help
48	  Select this dram controller driver for some sun50i platforms,
49	  like H6.
50
51config SUN6I_P2WI
52	bool "Allwinner sun6i internal P2WI controller"
53	help
54	  If you say yes to this option, support will be included for the
55	  P2WI (Push/Pull 2 Wire Interface) controller embedded in some sunxi
56	  SOCs.
57	  The P2WI looks like an SMBus controller (which supports only byte
58	  accesses), except that it only supports one slave device.
59	  This interface is used to connect to specific PMIC devices (like the
60	  AXP221).
61
62config SUN6I_PRCM
63	bool
64	help
65	  Support for the PRCM (Power/Reset/Clock Management) unit available
66	  in A31 SoC.
67
68config AXP_PMIC_BUS
69	bool "Sunxi AXP PMIC bus access helpers"
70	help
71	  Select this PMIC bus access helpers for Sunxi platform PRCM or other
72	  AXP family PMIC devices.
73
74config SUN8I_RSB
75	bool "Allwinner sunXi Reduced Serial Bus Driver"
76	help
77	  Say y here to enable support for Allwinner's Reduced Serial Bus
78	  (RSB) support. This controller is responsible for communicating
79	  with various RSB based devices, such as AXP223, AXP8XX PMICs,
80	  and AC100/AC200 ICs.
81
82config SUNXI_SRAM_ADDRESS
83	hex
84	default 0x10000 if MACH_SUN9I || MACH_SUN50I || MACH_SUN50I_H5
85	default 0x20000 if MACH_SUN50I_H6
86	default 0x0
87	---help---
88	Older Allwinner SoCs have their mask boot ROM mapped just below 4GB,
89	with the first SRAM region being located at address 0.
90	Some newer SoCs map the boot ROM at address 0 instead and move the
91	SRAM to a different address.
92
93config SUNXI_A64_TIMER_ERRATUM
94	bool
95
96# Note only one of these may be selected at a time! But hidden choices are
97# not supported by Kconfig
98config SUNXI_GEN_SUN4I
99	bool
100	---help---
101	Select this for sunxi SoCs which have resets and clocks set up
102	as the original A10 (mach-sun4i).
103
104config SUNXI_GEN_SUN6I
105	bool
106	---help---
107	Select this for sunxi SoCs which have sun6i like periphery, like
108	separate ahb reset control registers, custom pmic bus, new style
109	watchdog, etc.
110
111config SUNXI_DRAM_DW
112	bool
113	---help---
114	Select this for sunxi SoCs which uses a DRAM controller like the
115	DesignWare controller used in H3, mainly SoCs after H3, which do
116	not have official open-source DRAM initialization code, but can
117	use modified H3 DRAM initialization code.
118
119if SUNXI_DRAM_DW
120config SUNXI_DRAM_DW_16BIT
121	bool
122	---help---
123	Select this for sunxi SoCs with DesignWare DRAM controller and
124	have only 16-bit memory buswidth.
125
126config SUNXI_DRAM_DW_32BIT
127	bool
128	---help---
129	Select this for sunxi SoCs with DesignWare DRAM controller with
130	32-bit memory buswidth.
131endif
132
133config MACH_SUNXI_H3_H5
134	bool
135	select DM_I2C
136	select PHY_SUN4I_USB
137	select SUNXI_DE2
138	select SUNXI_DRAM_DW
139	select SUNXI_DRAM_DW_32BIT
140	select SUNXI_GEN_SUN6I
141	select SUPPORT_SPL
142
143# TODO: try out A80's 8GiB DRAM space
144config SUNXI_DRAM_MAX_SIZE
145	hex
146	default 0xC0000000 if MACH_SUN50I || MACH_SUN50I_H5 || MACH_SUN50I_H6
147	default 0x80000000
148
149choice
150	prompt "Sunxi SoC Variant"
151	optional
152
153config MACH_SUN4I
154	bool "sun4i (Allwinner A10)"
155	select CPU_V7A
156	select ARM_CORTEX_CPU_IS_UP
157	select DM_MMC if MMC
158	select DM_SCSI if SCSI
159	select PHY_SUN4I_USB
160	select DRAM_SUN4I
161	select SUNXI_GEN_SUN4I
162	select SUPPORT_SPL
163
164config MACH_SUN5I
165	bool "sun5i (Allwinner A13)"
166	select CPU_V7A
167	select ARM_CORTEX_CPU_IS_UP
168	select DRAM_SUN4I
169	select PHY_SUN4I_USB
170	select SUNXI_GEN_SUN4I
171	select SUPPORT_SPL
172	imply CONS_INDEX_2 if !DM_SERIAL
173
174config MACH_SUN6I
175	bool "sun6i (Allwinner A31)"
176	select CPU_V7A
177	select CPU_V7_HAS_NONSEC
178	select CPU_V7_HAS_VIRT
179	select ARCH_SUPPORT_PSCI
180	select DRAM_SUN6I
181	select PHY_SUN4I_USB
182	select SUN6I_P2WI
183	select SUN6I_PRCM
184	select SUNXI_GEN_SUN6I
185	select SUPPORT_SPL
186	select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
187
188config MACH_SUN7I
189	bool "sun7i (Allwinner A20)"
190	select CPU_V7A
191	select CPU_V7_HAS_NONSEC
192	select CPU_V7_HAS_VIRT
193	select ARCH_SUPPORT_PSCI
194	select DRAM_SUN4I
195	select PHY_SUN4I_USB
196	select SUNXI_GEN_SUN4I
197	select SUPPORT_SPL
198	select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
199
200config MACH_SUN8I_A23
201	bool "sun8i (Allwinner A23)"
202	select CPU_V7A
203	select CPU_V7_HAS_NONSEC
204	select CPU_V7_HAS_VIRT
205	select ARCH_SUPPORT_PSCI
206	select DRAM_SUN8I_A23
207	select PHY_SUN4I_USB
208	select SUNXI_GEN_SUN6I
209	select SUPPORT_SPL
210	select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
211	imply CONS_INDEX_5 if !DM_SERIAL
212
213config MACH_SUN8I_A33
214	bool "sun8i (Allwinner A33)"
215	select CPU_V7A
216	select CPU_V7_HAS_NONSEC
217	select CPU_V7_HAS_VIRT
218	select ARCH_SUPPORT_PSCI
219	select DRAM_SUN8I_A33
220	select PHY_SUN4I_USB
221	select SUNXI_GEN_SUN6I
222	select SUPPORT_SPL
223	select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
224	imply CONS_INDEX_5 if !DM_SERIAL
225
226config MACH_SUN8I_A83T
227	bool "sun8i (Allwinner A83T)"
228	select CPU_V7A
229	select DRAM_SUN8I_A83T
230	select PHY_SUN4I_USB
231	select SUNXI_GEN_SUN6I
232	select MMC_SUNXI_HAS_NEW_MODE
233	select MMC_SUNXI_HAS_MODE_SWITCH
234	select SUPPORT_SPL
235
236config MACH_SUN8I_H3
237	bool "sun8i (Allwinner H3)"
238	select CPU_V7A
239	select CPU_V7_HAS_NONSEC
240	select CPU_V7_HAS_VIRT
241	select ARCH_SUPPORT_PSCI
242	select MACH_SUNXI_H3_H5
243	select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
244
245config MACH_SUN8I_R40
246	bool "sun8i (Allwinner R40)"
247	select CPU_V7A
248	select CPU_V7_HAS_NONSEC
249	select CPU_V7_HAS_VIRT
250	select ARCH_SUPPORT_PSCI
251	select SUNXI_GEN_SUN6I
252	select SUPPORT_SPL
253	select SUNXI_DRAM_DW
254	select SUNXI_DRAM_DW_32BIT
255
256config MACH_SUN8I_V3S
257	bool "sun8i (Allwinner V3s)"
258	select CPU_V7A
259	select CPU_V7_HAS_NONSEC
260	select CPU_V7_HAS_VIRT
261	select ARCH_SUPPORT_PSCI
262	select SUNXI_GEN_SUN6I
263	select SUNXI_DRAM_DW
264	select SUNXI_DRAM_DW_16BIT
265	select SUPPORT_SPL
266	select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
267
268config MACH_SUN9I
269	bool "sun9i (Allwinner A80)"
270	select CPU_V7A
271	select DRAM_SUN9I
272	select SUN6I_PRCM
273	select SUNXI_GEN_SUN6I
274	select SUN8I_RSB
275	select SUPPORT_SPL
276
277config MACH_SUN50I
278	bool "sun50i (Allwinner A64)"
279	select ARM64
280	select DM_I2C
281	select PHY_SUN4I_USB
282	select SUN6I_PRCM
283	select SUNXI_DE2
284	select SUNXI_GEN_SUN6I
285	select MMC_SUNXI_HAS_NEW_MODE
286	select SUPPORT_SPL
287	select SUNXI_DRAM_DW
288	select SUNXI_DRAM_DW_32BIT
289	select FIT
290	select SPL_LOAD_FIT
291	select SUNXI_A64_TIMER_ERRATUM
292
293config MACH_SUN50I_H5
294	bool "sun50i (Allwinner H5)"
295	select ARM64
296	select MACH_SUNXI_H3_H5
297	select FIT
298	select SPL_LOAD_FIT
299
300config MACH_SUN50I_H6
301	bool "sun50i (Allwinner H6)"
302	select ARM64
303	select SUPPORT_SPL
304	select FIT
305	select SPL_LOAD_FIT
306	select DRAM_SUN50I_H6
307
308endchoice
309
310# The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
311config MACH_SUN8I
312	bool
313	select SUN8I_RSB
314	select SUN6I_PRCM
315	default y if MACH_SUN8I_A23
316	default y if MACH_SUN8I_A33
317	default y if MACH_SUN8I_A83T
318	default y if MACH_SUNXI_H3_H5
319	default y if MACH_SUN8I_R40
320	default y if MACH_SUN8I_V3S
321
322config RESERVE_ALLWINNER_BOOT0_HEADER
323	bool "reserve space for Allwinner boot0 header"
324	select ENABLE_ARM_SOC_BOOT0_HOOK
325	---help---
326	Prepend a 1536 byte (empty) header to the U-Boot image file, to be
327	filled with magic values post build. The Allwinner provided boot0
328	blob relies on this information to load and execute U-Boot.
329	Only needed on 64-bit Allwinner boards so far when using boot0.
330
331config ARM_BOOT_HOOK_RMR
332	bool
333	depends on ARM64
334	default y
335	select ENABLE_ARM_SOC_BOOT0_HOOK
336	---help---
337	Insert some ARM32 code at the very beginning of the U-Boot binary
338	which uses an RMR register write to bring the core into AArch64 mode.
339	The very first instruction acts as a switch, since it's carefully
340	chosen to be a NOP in one mode and a branch in the other, so the
341	code would only be executed if not already in AArch64.
342	This allows both the SPL and the U-Boot proper to be entered in
343	either mode and switch to AArch64 if needed.
344
345if SUNXI_DRAM_DW
346config SUNXI_DRAM_DDR3
347	bool
348
349config SUNXI_DRAM_DDR2
350	bool
351
352config SUNXI_DRAM_LPDDR3
353	bool
354
355choice
356	prompt "DRAM Type and Timing"
357	default SUNXI_DRAM_DDR3_1333 if !MACH_SUN8I_V3S
358	default SUNXI_DRAM_DDR2_V3S if MACH_SUN8I_V3S
359
360config SUNXI_DRAM_DDR3_1333
361	bool "DDR3 1333"
362	select SUNXI_DRAM_DDR3
363	depends on !MACH_SUN8I_V3S
364	---help---
365	This option is the original only supported memory type, which suits
366	many H3/H5/A64 boards available now.
367
368config SUNXI_DRAM_LPDDR3_STOCK
369	bool "LPDDR3 with Allwinner stock configuration"
370	select SUNXI_DRAM_LPDDR3
371	---help---
372	This option is the LPDDR3 timing used by the stock boot0 by
373	Allwinner.
374
375config SUNXI_DRAM_DDR2_V3S
376	bool "DDR2 found in V3s chip"
377	select SUNXI_DRAM_DDR2
378	depends on MACH_SUN8I_V3S
379	---help---
380	This option is only for the DDR2 memory chip which is co-packaged in
381	Allwinner V3s SoC.
382
383endchoice
384endif
385
386config DRAM_TYPE
387	int "sunxi dram type"
388	depends on MACH_SUN8I_A83T
389	default 3
390	---help---
391	Set the dram type, 3: DDR3, 7: LPDDR3
392
393config DRAM_CLK
394	int "sunxi dram clock speed"
395	default 792 if MACH_SUN9I
396	default 648 if MACH_SUN8I_R40
397	default 312 if MACH_SUN6I || MACH_SUN8I
398	default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || \
399		       MACH_SUN8I_V3S
400	default 672 if MACH_SUN50I
401	default 744 if MACH_SUN50I_H6
402	---help---
403	Set the dram clock speed, valid range 240 - 480 (prior to sun9i),
404	must be a multiple of 24. For the sun9i (A80), the tested values
405	(for DDR3-1600) are 312 to 792.
406
407if MACH_SUN5I || MACH_SUN7I
408config DRAM_MBUS_CLK
409	int "sunxi mbus clock speed"
410	default 300
411	---help---
412	Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
413
414endif
415
416config DRAM_ZQ
417	int "sunxi dram zq value"
418	default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
419	default 127 if MACH_SUN7I
420	default 14779 if MACH_SUN8I_V3S
421	default 3881979 if MACH_SUN8I_R40 || MACH_SUN50I_H6
422	default 4145117 if MACH_SUN9I
423	default 3881915 if MACH_SUN50I
424	---help---
425	Set the dram zq value.
426
427config DRAM_ODT_EN
428	bool "sunxi dram odt enable"
429	default y if MACH_SUN8I_A23
430	default y if MACH_SUN8I_R40
431	default y if MACH_SUN50I
432	default y if MACH_SUN50I_H6
433	---help---
434	Select this to enable dram odt (on die termination).
435
436if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
437config DRAM_EMR1
438	int "sunxi dram emr1 value"
439	default 0 if MACH_SUN4I
440	default 4 if MACH_SUN5I || MACH_SUN7I
441	---help---
442	Set the dram controller emr1 value.
443
444config DRAM_TPR3
445	hex "sunxi dram tpr3 value"
446	default 0
447	---help---
448	Set the dram controller tpr3 parameter. This parameter configures
449	the delay on the command lane and also phase shifts, which are
450	applied for sampling incoming read data. The default value 0
451	means that no phase/delay adjustments are necessary. Properly
452	configuring this parameter increases reliability at high DRAM
453	clock speeds.
454
455config DRAM_DQS_GATING_DELAY
456	hex "sunxi dram dqs_gating_delay value"
457	default 0
458	---help---
459	Set the dram controller dqs_gating_delay parmeter. Each byte
460	encodes the DQS gating delay for each byte lane. The delay
461	granularity is 1/4 cycle. For example, the value 0x05060606
462	means that the delay is 5 quarter-cycles for one lane (1.25
463	cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
464	The default value 0 means autodetection. The results of hardware
465	autodetection are not very reliable and depend on the chip
466	temperature (sometimes producing different results on cold start
467	and warm reboot). But the accuracy of hardware autodetection
468	is usually good enough, unless running at really high DRAM
469	clocks speeds (up to 600MHz). If unsure, keep as 0.
470
471choice
472	prompt "sunxi dram timings"
473	default DRAM_TIMINGS_VENDOR_MAGIC
474	---help---
475	Select the timings of the DDR3 chips.
476
477config DRAM_TIMINGS_VENDOR_MAGIC
478	bool "Magic vendor timings from Android"
479	---help---
480	The same DRAM timings as in the Allwinner boot0 bootloader.
481
482config DRAM_TIMINGS_DDR3_1066F_1333H
483	bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
484	---help---
485	Use the timings of the standard JEDEC DDR3-1066F speed bin for
486	DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
487	for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
488	used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
489	or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
490	that down binning to DDR3-1066F is supported (because DDR3-1066F
491	uses a bit faster timings than DDR3-1333H).
492
493config DRAM_TIMINGS_DDR3_800E_1066G_1333J
494	bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
495	---help---
496	Use the timings of the slowest possible JEDEC speed bin for the
497	selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
498	DDR3-800E, DDR3-1066G or DDR3-1333J.
499
500endchoice
501
502endif
503
504if MACH_SUN8I_A23
505config DRAM_ODT_CORRECTION
506	int "sunxi dram odt correction value"
507	default 0
508	---help---
509	Set the dram odt correction value (range -255 - 255). In allwinner
510	fex files, this option is found in bits 8-15 of the u32 odt_en variable
511	in the [dram] section. When bit 31 of the odt_en variable is set
512	then the correction is negative. Usually the value for this is 0.
513endif
514
515config SYS_CLK_FREQ
516	default 1008000000 if MACH_SUN4I
517	default 1008000000 if MACH_SUN5I
518	default 1008000000 if MACH_SUN6I
519	default 912000000 if MACH_SUN7I
520	default 816000000 if MACH_SUN50I || MACH_SUN50I_H5
521	default 1008000000 if MACH_SUN8I
522	default 1008000000 if MACH_SUN9I
523	default 888000000 if MACH_SUN50I_H6
524
525config SYS_CONFIG_NAME
526	default "sun4i" if MACH_SUN4I
527	default "sun5i" if MACH_SUN5I
528	default "sun6i" if MACH_SUN6I
529	default "sun7i" if MACH_SUN7I
530	default "sun8i" if MACH_SUN8I
531	default "sun9i" if MACH_SUN9I
532	default "sun50i" if MACH_SUN50I
533	default "sun50i" if MACH_SUN50I_H6
534
535config SYS_BOARD
536	default "sunxi"
537
538config SYS_SOC
539	default "sunxi"
540
541config UART0_PORT_F
542	bool "UART0 on MicroSD breakout board"
543	default n
544	---help---
545	Repurpose the SD card slot for getting access to the UART0 serial
546	console. Primarily useful only for low level u-boot debugging on
547	tablets, where normal UART0 is difficult to access and requires
548	device disassembly and/or soldering. As the SD card can't be used
549	at the same time, the system can be only booted in the FEL mode.
550	Only enable this if you really know what you are doing.
551
552config OLD_SUNXI_KERNEL_COMPAT
553	bool "Enable workarounds for booting old kernels"
554	default n
555	---help---
556	Set this to enable various workarounds for old kernels, this results in
557	sub-optimal settings for newer kernels, only enable if needed.
558
559config MACPWR
560	string "MAC power pin"
561	default ""
562	help
563	  Set the pin used to power the MAC. This takes a string in the format
564	  understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
565
566config MMC0_CD_PIN
567	string "Card detect pin for mmc0"
568	default "PF6" if MACH_SUN8I_A83T || MACH_SUNXI_H3_H5 || MACH_SUN50I
569	default ""
570	---help---
571	Set the card detect pin for mmc0, leave empty to not use cd. This
572	takes a string in the format understood by sunxi_name_to_gpio, e.g.
573	PH1 for pin 1 of port H.
574
575config MMC1_CD_PIN
576	string "Card detect pin for mmc1"
577	default ""
578	---help---
579	See MMC0_CD_PIN help text.
580
581config MMC2_CD_PIN
582	string "Card detect pin for mmc2"
583	default ""
584	---help---
585	See MMC0_CD_PIN help text.
586
587config MMC3_CD_PIN
588	string "Card detect pin for mmc3"
589	default ""
590	---help---
591	See MMC0_CD_PIN help text.
592
593config MMC1_PINS
594	string "Pins for mmc1"
595	default ""
596	---help---
597	Set the pins used for mmc1, when applicable. This takes a string in the
598	format understood by sunxi_name_to_gpio_bank, e.g. PH for port H.
599
600config MMC2_PINS
601	string "Pins for mmc2"
602	default ""
603	---help---
604	See MMC1_PINS help text.
605
606config MMC3_PINS
607	string "Pins for mmc3"
608	default ""
609	---help---
610	See MMC1_PINS help text.
611
612config MMC_SUNXI_SLOT_EXTRA
613	int "mmc extra slot number"
614	default -1
615	---help---
616	sunxi builds always enable mmc0, some boards also have a second sdcard
617	slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
618	support for this.
619
620config INITIAL_USB_SCAN_DELAY
621	int "delay initial usb scan by x ms to allow builtin devices to init"
622	default 0
623	---help---
624	Some boards have on board usb devices which need longer than the
625	USB spec's 1 second to connect from board powerup. Set this config
626	option to a non 0 value to add an extra delay before the first usb
627	bus scan.
628
629config USB0_VBUS_PIN
630	string "Vbus enable pin for usb0 (otg)"
631	default ""
632	---help---
633	Set the Vbus enable pin for usb0 (otg). This takes a string in the
634	format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
635
636config USB0_VBUS_DET
637	string "Vbus detect pin for usb0 (otg)"
638	default ""
639	---help---
640	Set the Vbus detect pin for usb0 (otg). This takes a string in the
641	format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
642
643config USB0_ID_DET
644	string "ID detect pin for usb0 (otg)"
645	default ""
646	---help---
647	Set the ID detect pin for usb0 (otg). This takes a string in the
648	format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
649
650config USB1_VBUS_PIN
651	string "Vbus enable pin for usb1 (ehci0)"
652	default "PH6" if MACH_SUN4I || MACH_SUN7I
653	default "PH27" if MACH_SUN6I
654	---help---
655	Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
656	a string in the format understood by sunxi_name_to_gpio, e.g.
657	PH1 for pin 1 of port H.
658
659config USB2_VBUS_PIN
660	string "Vbus enable pin for usb2 (ehci1)"
661	default "PH3" if MACH_SUN4I || MACH_SUN7I
662	default "PH24" if MACH_SUN6I
663	---help---
664	See USB1_VBUS_PIN help text.
665
666config USB3_VBUS_PIN
667	string "Vbus enable pin for usb3 (ehci2)"
668	default ""
669	---help---
670	See USB1_VBUS_PIN help text.
671
672config I2C0_ENABLE
673	bool "Enable I2C/TWI controller 0"
674	default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_R40
675	default n if MACH_SUN6I || MACH_SUN8I
676	select CMD_I2C
677	---help---
678	This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
679	its clock and setting up the bus. This is especially useful on devices
680	with slaves connected to the bus or with pins exposed through e.g. an
681	expansion port/header.
682
683config I2C1_ENABLE
684	bool "Enable I2C/TWI controller 1"
685	default n
686	select CMD_I2C
687	---help---
688	See I2C0_ENABLE help text.
689
690config I2C2_ENABLE
691	bool "Enable I2C/TWI controller 2"
692	default n
693	select CMD_I2C
694	---help---
695	See I2C0_ENABLE help text.
696
697if MACH_SUN6I || MACH_SUN7I
698config I2C3_ENABLE
699	bool "Enable I2C/TWI controller 3"
700	default n
701	select CMD_I2C
702	---help---
703	See I2C0_ENABLE help text.
704endif
705
706if SUNXI_GEN_SUN6I
707config R_I2C_ENABLE
708	bool "Enable the PRCM I2C/TWI controller"
709	# This is used for the pmic on H3
710	default y if SY8106A_POWER
711	select CMD_I2C
712	---help---
713	Set this to y to enable the I2C controller which is part of the PRCM.
714endif
715
716if MACH_SUN7I
717config I2C4_ENABLE
718	bool "Enable I2C/TWI controller 4"
719	default n
720	select CMD_I2C
721	---help---
722	See I2C0_ENABLE help text.
723endif
724
725config AXP_GPIO
726	bool "Enable support for gpio-s on axp PMICs"
727	default n
728	---help---
729	Say Y here to enable support for the gpio pins of the axp PMIC ICs.
730
731config VIDEO_SUNXI
732	bool "Enable graphical uboot console on HDMI, LCD or VGA"
733	depends on !MACH_SUN8I_A83T
734	depends on !MACH_SUNXI_H3_H5
735	depends on !MACH_SUN8I_R40
736	depends on !MACH_SUN8I_V3S
737	depends on !MACH_SUN9I
738	depends on !MACH_SUN50I
739	depends on !MACH_SUN50I_H6
740	select VIDEO
741	imply VIDEO_DT_SIMPLEFB
742	default y
743	---help---
744	Say Y here to add support for using a cfb console on the HDMI, LCD
745	or VGA output found on most sunxi devices. See doc/README.video for
746	info on how to select the video output and mode.
747
748config VIDEO_HDMI
749	bool "HDMI output support"
750	depends on VIDEO_SUNXI && !MACH_SUN8I
751	default y
752	---help---
753	Say Y here to add support for outputting video over HDMI.
754
755config VIDEO_VGA
756	bool "VGA output support"
757	depends on VIDEO_SUNXI && (MACH_SUN4I || MACH_SUN7I)
758	default n
759	---help---
760	Say Y here to add support for outputting video over VGA.
761
762config VIDEO_VGA_VIA_LCD
763	bool "VGA via LCD controller support"
764	depends on VIDEO_SUNXI && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
765	default n
766	---help---
767	Say Y here to add support for external DACs connected to the parallel
768	LCD interface driving a VGA connector, such as found on the
769	Olimex A13 boards.
770
771config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
772	bool "Force sync active high for VGA via LCD controller support"
773	depends on VIDEO_VGA_VIA_LCD
774	default n
775	---help---
776	Say Y here if you've a board which uses opendrain drivers for the vga
777	hsync and vsync signals. Opendrain drivers cannot generate steep enough
778	positive edges for a stable video output, so on boards with opendrain
779	drivers the sync signals must always be active high.
780
781config VIDEO_VGA_EXTERNAL_DAC_EN
782	string "LCD panel power enable pin"
783	depends on VIDEO_VGA_VIA_LCD
784	default ""
785	---help---
786	Set the enable pin for the external VGA DAC. This takes a string in the
787	format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
788
789config VIDEO_COMPOSITE
790	bool "Composite video output support"
791	depends on VIDEO_SUNXI && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
792	default n
793	---help---
794	Say Y here to add support for outputting composite video.
795
796config VIDEO_LCD_MODE
797	string "LCD panel timing details"
798	depends on VIDEO_SUNXI
799	default ""
800	---help---
801	LCD panel timing details string, leave empty if there is no LCD panel.
802	This is in drivers/video/videomodes.c: video_get_params() format, e.g.
803	x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
804	Also see: http://linux-sunxi.org/LCD
805
806config VIDEO_LCD_DCLK_PHASE
807	int "LCD panel display clock phase"
808	depends on VIDEO_SUNXI || DM_VIDEO
809	default 1
810	---help---
811	Select LCD panel display clock phase shift, range 0-3.
812
813config VIDEO_LCD_POWER
814	string "LCD panel power enable pin"
815	depends on VIDEO_SUNXI
816	default ""
817	---help---
818	Set the power enable pin for the LCD panel. This takes a string in the
819	format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
820
821config VIDEO_LCD_RESET
822	string "LCD panel reset pin"
823	depends on VIDEO_SUNXI
824	default ""
825	---help---
826	Set the reset pin for the LCD panel. This takes a string in the format
827	understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
828
829config VIDEO_LCD_BL_EN
830	string "LCD panel backlight enable pin"
831	depends on VIDEO_SUNXI
832	default ""
833	---help---
834	Set the backlight enable pin for the LCD panel. This takes a string in the
835	the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
836	port H.
837
838config VIDEO_LCD_BL_PWM
839	string "LCD panel backlight pwm pin"
840	depends on VIDEO_SUNXI
841	default ""
842	---help---
843	Set the backlight pwm pin for the LCD panel. This takes a string in the
844	format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
845
846config VIDEO_LCD_BL_PWM_ACTIVE_LOW
847	bool "LCD panel backlight pwm is inverted"
848	depends on VIDEO_SUNXI
849	default y
850	---help---
851	Set this if the backlight pwm output is active low.
852
853config VIDEO_LCD_PANEL_I2C
854	bool "LCD panel needs to be configured via i2c"
855	depends on VIDEO_SUNXI
856	default n
857	select CMD_I2C
858	---help---
859	Say y here if the LCD panel needs to be configured via i2c. This
860	will add a bitbang i2c controller using gpios to talk to the LCD.
861
862config VIDEO_LCD_PANEL_I2C_SDA
863	string "LCD panel i2c interface SDA pin"
864	depends on VIDEO_LCD_PANEL_I2C
865	default "PG12"
866	---help---
867	Set the SDA pin for the LCD i2c interface. This takes a string in the
868	format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
869
870config VIDEO_LCD_PANEL_I2C_SCL
871	string "LCD panel i2c interface SCL pin"
872	depends on VIDEO_LCD_PANEL_I2C
873	default "PG10"
874	---help---
875	Set the SCL pin for the LCD i2c interface. This takes a string in the
876	format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
877
878
879# Note only one of these may be selected at a time! But hidden choices are
880# not supported by Kconfig
881config VIDEO_LCD_IF_PARALLEL
882	bool
883
884config VIDEO_LCD_IF_LVDS
885	bool
886
887config SUNXI_DE2
888	bool
889	default n
890
891config VIDEO_DE2
892	bool "Display Engine 2 video driver"
893	depends on SUNXI_DE2
894	select DM_VIDEO
895	select DISPLAY
896	imply VIDEO_DT_SIMPLEFB
897	default y
898	---help---
899	Say y here if you want to build DE2 video driver which is present on
900	newer SoCs. Currently only HDMI output is supported.
901
902
903choice
904	prompt "LCD panel support"
905	depends on VIDEO_SUNXI
906	---help---
907	Select which type of LCD panel to support.
908
909config VIDEO_LCD_PANEL_PARALLEL
910	bool "Generic parallel interface LCD panel"
911	select VIDEO_LCD_IF_PARALLEL
912
913config VIDEO_LCD_PANEL_LVDS
914	bool "Generic lvds interface LCD panel"
915	select VIDEO_LCD_IF_LVDS
916
917config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
918	bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
919	select VIDEO_LCD_SSD2828
920	select VIDEO_LCD_IF_PARALLEL
921	---help---
922	7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
923
924config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
925	bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip"
926	select VIDEO_LCD_ANX9804
927	select VIDEO_LCD_IF_PARALLEL
928	select VIDEO_LCD_PANEL_I2C
929	---help---
930	Select this for eDP LCD panels with 4 lanes running at 1.62G,
931	connected via an ANX9804 bridge chip.
932
933config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
934	bool "Hitachi tx18d42vm LCD panel"
935	select VIDEO_LCD_HITACHI_TX18D42VM
936	select VIDEO_LCD_IF_LVDS
937	---help---
938	7.85" 1024x768 Hitachi tx18d42vm LCD panel support
939
940config VIDEO_LCD_TL059WV5C0
941	bool "tl059wv5c0 LCD panel"
942	select VIDEO_LCD_PANEL_I2C
943	select VIDEO_LCD_IF_PARALLEL
944	---help---
945	6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and
946	Aigo M60/M608/M606 tablets.
947
948endchoice
949
950config SATAPWR
951	string "SATA power pin"
952	default ""
953	help
954	  Set the pins used to power the SATA. This takes a string in the
955	  format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
956	  port H.
957
958config GMAC_TX_DELAY
959	int "GMAC Transmit Clock Delay Chain"
960	default 0
961	---help---
962	Set the GMAC Transmit Clock Delay Chain value.
963
964config SPL_STACK_R_ADDR
965	default 0x4fe00000 if MACH_SUN4I
966	default 0x4fe00000 if MACH_SUN5I
967	default 0x4fe00000 if MACH_SUN6I
968	default 0x4fe00000 if MACH_SUN7I
969	default 0x4fe00000 if MACH_SUN8I
970	default 0x2fe00000 if MACH_SUN9I
971	default 0x4fe00000 if MACH_SUN50I
972	default 0x4fe00000 if MACH_SUN50I_H6
973
974config SPL_SPI_SUNXI
975	bool "Support for SPI Flash on Allwinner SoCs in SPL"
976	depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I
977	help
978	  Enable support for SPI Flash. This option allows SPL to read from
979	  sunxi SPI Flash. It uses the same method as the boot ROM, so does
980	  not need any extra configuration.
981
982config PINE64_DT_SELECTION
983	bool "Enable Pine64 device tree selection code"
984	depends on MACH_SUN50I
985	help
986	  The original Pine A64 and Pine A64+ are similar but different
987	  boards and can be differed by the DRAM size. Pine A64 has
988	  512MiB DRAM, and Pine A64+ has 1GiB or 2GiB. By selecting this
989	  option, the device tree selection code specific to Pine64 which
990	  utilizes the DRAM size will be enabled.
991
992endif
993