1if ARCH_SUNXI 2 3config IDENT_STRING 4 default " Allwinner Technology" 5 6config SUNXI_HIGH_SRAM 7 bool 8 default n 9 ---help--- 10 Older Allwinner SoCs have their mask boot ROM mapped just below 4GB, 11 with the first SRAM region being located at address 0. 12 Some newer SoCs map the boot ROM at address 0 instead and move the 13 SRAM to 64KB, just behind the mask ROM. 14 Chips using the latter setup are supposed to select this option to 15 adjust the addresses accordingly. 16 17# Note only one of these may be selected at a time! But hidden choices are 18# not supported by Kconfig 19config SUNXI_GEN_SUN4I 20 bool 21 ---help--- 22 Select this for sunxi SoCs which have resets and clocks set up 23 as the original A10 (mach-sun4i). 24 25config SUNXI_GEN_SUN6I 26 bool 27 ---help--- 28 Select this for sunxi SoCs which have sun6i like periphery, like 29 separate ahb reset control registers, custom pmic bus, new style 30 watchdog, etc. 31 32config SUNXI_DRAM_DW 33 bool 34 ---help--- 35 Select this for sunxi SoCs which uses a DRAM controller like the 36 DesignWare controller used in H3, mainly SoCs after H3, which do 37 not have official open-source DRAM initialization code, but can 38 use modified H3 DRAM initialization code. 39 40if SUNXI_DRAM_DW 41config SUNXI_DRAM_DW_16BIT 42 bool 43 ---help--- 44 Select this for sunxi SoCs with DesignWare DRAM controller and 45 have only 16-bit memory buswidth. 46 47config SUNXI_DRAM_DW_32BIT 48 bool 49 ---help--- 50 Select this for sunxi SoCs with DesignWare DRAM controller with 51 32-bit memory buswidth. 52endif 53 54config MACH_SUNXI_H3_H5 55 bool 56 select DM_I2C 57 select SUNXI_DE2 58 select SUNXI_DRAM_DW 59 select SUNXI_DRAM_DW_32BIT 60 select SUNXI_GEN_SUN6I 61 select SUPPORT_SPL 62 63choice 64 prompt "Sunxi SoC Variant" 65 optional 66 67config MACH_SUN4I 68 bool "sun4i (Allwinner A10)" 69 select CPU_V7 70 select ARM_CORTEX_CPU_IS_UP 71 select SUNXI_GEN_SUN4I 72 select SUPPORT_SPL 73 74config MACH_SUN5I 75 bool "sun5i (Allwinner A13)" 76 select CPU_V7 77 select ARM_CORTEX_CPU_IS_UP 78 select SUNXI_GEN_SUN4I 79 select SUPPORT_SPL 80 81config MACH_SUN6I 82 bool "sun6i (Allwinner A31)" 83 select CPU_V7 84 select CPU_V7_HAS_NONSEC 85 select CPU_V7_HAS_VIRT 86 select ARCH_SUPPORT_PSCI 87 select SUNXI_GEN_SUN6I 88 select SUPPORT_SPL 89 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT 90 91config MACH_SUN7I 92 bool "sun7i (Allwinner A20)" 93 select CPU_V7 94 select CPU_V7_HAS_NONSEC 95 select CPU_V7_HAS_VIRT 96 select ARCH_SUPPORT_PSCI 97 select SUNXI_GEN_SUN4I 98 select SUPPORT_SPL 99 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT 100 101config MACH_SUN8I_A23 102 bool "sun8i (Allwinner A23)" 103 select CPU_V7 104 select CPU_V7_HAS_NONSEC 105 select CPU_V7_HAS_VIRT 106 select ARCH_SUPPORT_PSCI 107 select SUNXI_GEN_SUN6I 108 select SUPPORT_SPL 109 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT 110 111config MACH_SUN8I_A33 112 bool "sun8i (Allwinner A33)" 113 select CPU_V7 114 select CPU_V7_HAS_NONSEC 115 select CPU_V7_HAS_VIRT 116 select ARCH_SUPPORT_PSCI 117 select SUNXI_GEN_SUN6I 118 select SUPPORT_SPL 119 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT 120 121config MACH_SUN8I_A83T 122 bool "sun8i (Allwinner A83T)" 123 select CPU_V7 124 select SUNXI_GEN_SUN6I 125 select SUPPORT_SPL 126 127config MACH_SUN8I_H3 128 bool "sun8i (Allwinner H3)" 129 select CPU_V7 130 select CPU_V7_HAS_NONSEC 131 select CPU_V7_HAS_VIRT 132 select ARCH_SUPPORT_PSCI 133 select MACH_SUNXI_H3_H5 134 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT 135 136config MACH_SUN8I_R40 137 bool "sun8i (Allwinner R40)" 138 select CPU_V7 139 select CPU_V7_HAS_NONSEC 140 select CPU_V7_HAS_VIRT 141 select ARCH_SUPPORT_PSCI 142 select SUNXI_GEN_SUN6I 143 select SUPPORT_SPL 144 select SUNXI_DRAM_DW 145 select SUNXI_DRAM_DW_32BIT 146 147config MACH_SUN8I_V3S 148 bool "sun8i (Allwinner V3s)" 149 select CPU_V7 150 select CPU_V7_HAS_NONSEC 151 select CPU_V7_HAS_VIRT 152 select ARCH_SUPPORT_PSCI 153 select SUNXI_GEN_SUN6I 154 select SUNXI_DRAM_DW 155 select SUNXI_DRAM_DW_16BIT 156 select SUPPORT_SPL 157 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT 158 159config MACH_SUN9I 160 bool "sun9i (Allwinner A80)" 161 select CPU_V7 162 select SUNXI_HIGH_SRAM 163 select SUNXI_GEN_SUN6I 164 select SUPPORT_SPL 165 166config MACH_SUN50I 167 bool "sun50i (Allwinner A64)" 168 select ARM64 169 select DM_I2C 170 select SUNXI_DE2 171 select SUNXI_GEN_SUN6I 172 select SUNXI_HIGH_SRAM 173 select SUPPORT_SPL 174 select SUNXI_DRAM_DW 175 select SUNXI_DRAM_DW_32BIT 176 select FIT 177 select SPL_LOAD_FIT 178 179config MACH_SUN50I_H5 180 bool "sun50i (Allwinner H5)" 181 select ARM64 182 select MACH_SUNXI_H3_H5 183 select SUNXI_HIGH_SRAM 184 select FIT 185 select SPL_LOAD_FIT 186 187endchoice 188 189# The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33" 190config MACH_SUN8I 191 bool 192 default y if MACH_SUN8I_A23 193 default y if MACH_SUN8I_A33 194 default y if MACH_SUN8I_A83T 195 default y if MACH_SUNXI_H3_H5 196 default y if MACH_SUN8I_R40 197 default y if MACH_SUN8I_V3S 198 199config RESERVE_ALLWINNER_BOOT0_HEADER 200 bool "reserve space for Allwinner boot0 header" 201 select ENABLE_ARM_SOC_BOOT0_HOOK 202 ---help--- 203 Prepend a 1536 byte (empty) header to the U-Boot image file, to be 204 filled with magic values post build. The Allwinner provided boot0 205 blob relies on this information to load and execute U-Boot. 206 Only needed on 64-bit Allwinner boards so far when using boot0. 207 208config ARM_BOOT_HOOK_RMR 209 bool 210 depends on ARM64 211 default y 212 select ENABLE_ARM_SOC_BOOT0_HOOK 213 ---help--- 214 Insert some ARM32 code at the very beginning of the U-Boot binary 215 which uses an RMR register write to bring the core into AArch64 mode. 216 The very first instruction acts as a switch, since it's carefully 217 chosen to be a NOP in one mode and a branch in the other, so the 218 code would only be executed if not already in AArch64. 219 This allows both the SPL and the U-Boot proper to be entered in 220 either mode and switch to AArch64 if needed. 221 222if SUNXI_DRAM_DW 223config SUNXI_DRAM_DDR3 224 bool 225 226config SUNXI_DRAM_DDR2 227 bool 228 229choice 230 prompt "DRAM Type and Timing" 231 default SUNXI_DRAM_DDR3_1333 if !MACH_SUN8I_V3S 232 default SUNXI_DRAM_DDR2_V3S if MACH_SUN8I_V3S 233 234config SUNXI_DRAM_DDR3_1333 235 bool "DDR3 1333" 236 select SUNXI_DRAM_DDR3 237 depends on !MACH_SUN8I_V3S 238 ---help--- 239 This option is the original only supported memory type, which suits 240 many H3/H5/A64 boards available now. 241 242config SUNXI_DRAM_DDR2_V3S 243 bool "DDR2 found in V3s chip" 244 select SUNXI_DRAM_DDR2 245 depends on MACH_SUN8I_V3S 246 ---help--- 247 This option is only for the DDR2 memory chip which is co-packaged in 248 Allwinner V3s SoC. 249 250endchoice 251endif 252 253config DRAM_TYPE 254 int "sunxi dram type" 255 depends on MACH_SUN8I_A83T 256 default 3 257 ---help--- 258 Set the dram type, 3: DDR3, 7: LPDDR3 259 260config DRAM_CLK 261 int "sunxi dram clock speed" 262 default 792 if MACH_SUN9I 263 default 648 if MACH_SUN8I_R40 264 default 312 if MACH_SUN6I || MACH_SUN8I 265 default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || \ 266 MACH_SUN8I_V3S 267 default 672 if MACH_SUN50I 268 ---help--- 269 Set the dram clock speed, valid range 240 - 480 (prior to sun9i), 270 must be a multiple of 24. For the sun9i (A80), the tested values 271 (for DDR3-1600) are 312 to 792. 272 273if MACH_SUN5I || MACH_SUN7I 274config DRAM_MBUS_CLK 275 int "sunxi mbus clock speed" 276 default 300 277 ---help--- 278 Set the mbus clock speed. The maximum on sun5i hardware is 300MHz. 279 280endif 281 282config DRAM_ZQ 283 int "sunxi dram zq value" 284 default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I 285 default 127 if MACH_SUN7I 286 default 14779 if MACH_SUN8I_V3S 287 default 3881979 if MACH_SUN8I_R40 288 default 4145117 if MACH_SUN9I 289 default 3881915 if MACH_SUN50I 290 ---help--- 291 Set the dram zq value. 292 293config DRAM_ODT_EN 294 bool "sunxi dram odt enable" 295 default n if !MACH_SUN8I_A23 296 default y if MACH_SUN8I_A23 297 default y if MACH_SUN8I_R40 298 default y if MACH_SUN50I 299 ---help--- 300 Select this to enable dram odt (on die termination). 301 302if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I 303config DRAM_EMR1 304 int "sunxi dram emr1 value" 305 default 0 if MACH_SUN4I 306 default 4 if MACH_SUN5I || MACH_SUN7I 307 ---help--- 308 Set the dram controller emr1 value. 309 310config DRAM_TPR3 311 hex "sunxi dram tpr3 value" 312 default 0 313 ---help--- 314 Set the dram controller tpr3 parameter. This parameter configures 315 the delay on the command lane and also phase shifts, which are 316 applied for sampling incoming read data. The default value 0 317 means that no phase/delay adjustments are necessary. Properly 318 configuring this parameter increases reliability at high DRAM 319 clock speeds. 320 321config DRAM_DQS_GATING_DELAY 322 hex "sunxi dram dqs_gating_delay value" 323 default 0 324 ---help--- 325 Set the dram controller dqs_gating_delay parmeter. Each byte 326 encodes the DQS gating delay for each byte lane. The delay 327 granularity is 1/4 cycle. For example, the value 0x05060606 328 means that the delay is 5 quarter-cycles for one lane (1.25 329 cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes. 330 The default value 0 means autodetection. The results of hardware 331 autodetection are not very reliable and depend on the chip 332 temperature (sometimes producing different results on cold start 333 and warm reboot). But the accuracy of hardware autodetection 334 is usually good enough, unless running at really high DRAM 335 clocks speeds (up to 600MHz). If unsure, keep as 0. 336 337choice 338 prompt "sunxi dram timings" 339 default DRAM_TIMINGS_VENDOR_MAGIC 340 ---help--- 341 Select the timings of the DDR3 chips. 342 343config DRAM_TIMINGS_VENDOR_MAGIC 344 bool "Magic vendor timings from Android" 345 ---help--- 346 The same DRAM timings as in the Allwinner boot0 bootloader. 347 348config DRAM_TIMINGS_DDR3_1066F_1333H 349 bool "JEDEC DDR3-1333H with down binning to DDR3-1066F" 350 ---help--- 351 Use the timings of the standard JEDEC DDR3-1066F speed bin for 352 DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin 353 for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips 354 used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333 355 or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm 356 that down binning to DDR3-1066F is supported (because DDR3-1066F 357 uses a bit faster timings than DDR3-1333H). 358 359config DRAM_TIMINGS_DDR3_800E_1066G_1333J 360 bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J" 361 ---help--- 362 Use the timings of the slowest possible JEDEC speed bin for the 363 selected DRAM_CLK. Depending on the DRAM_CLK value, it may be 364 DDR3-800E, DDR3-1066G or DDR3-1333J. 365 366endchoice 367 368endif 369 370if MACH_SUN8I_A23 371config DRAM_ODT_CORRECTION 372 int "sunxi dram odt correction value" 373 default 0 374 ---help--- 375 Set the dram odt correction value (range -255 - 255). In allwinner 376 fex files, this option is found in bits 8-15 of the u32 odt_en variable 377 in the [dram] section. When bit 31 of the odt_en variable is set 378 then the correction is negative. Usually the value for this is 0. 379endif 380 381config SYS_CLK_FREQ 382 default 1008000000 if MACH_SUN4I 383 default 1008000000 if MACH_SUN5I 384 default 1008000000 if MACH_SUN6I 385 default 912000000 if MACH_SUN7I 386 default 1008000000 if MACH_SUN8I 387 default 1008000000 if MACH_SUN9I 388 default 816000000 if MACH_SUN50I 389 390config SYS_CONFIG_NAME 391 default "sun4i" if MACH_SUN4I 392 default "sun5i" if MACH_SUN5I 393 default "sun6i" if MACH_SUN6I 394 default "sun7i" if MACH_SUN7I 395 default "sun8i" if MACH_SUN8I 396 default "sun9i" if MACH_SUN9I 397 default "sun50i" if MACH_SUN50I 398 399config SYS_BOARD 400 default "sunxi" 401 402config SYS_SOC 403 default "sunxi" 404 405config UART0_PORT_F 406 bool "UART0 on MicroSD breakout board" 407 default n 408 ---help--- 409 Repurpose the SD card slot for getting access to the UART0 serial 410 console. Primarily useful only for low level u-boot debugging on 411 tablets, where normal UART0 is difficult to access and requires 412 device disassembly and/or soldering. As the SD card can't be used 413 at the same time, the system can be only booted in the FEL mode. 414 Only enable this if you really know what you are doing. 415 416config OLD_SUNXI_KERNEL_COMPAT 417 bool "Enable workarounds for booting old kernels" 418 default n 419 ---help--- 420 Set this to enable various workarounds for old kernels, this results in 421 sub-optimal settings for newer kernels, only enable if needed. 422 423config MACPWR 424 string "MAC power pin" 425 default "" 426 help 427 Set the pin used to power the MAC. This takes a string in the format 428 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. 429 430config MMC0_CD_PIN 431 string "Card detect pin for mmc0" 432 default "PF6" if MACH_SUN8I_A83T || MACH_SUNXI_H3_H5 || MACH_SUN50I 433 default "" 434 ---help--- 435 Set the card detect pin for mmc0, leave empty to not use cd. This 436 takes a string in the format understood by sunxi_name_to_gpio, e.g. 437 PH1 for pin 1 of port H. 438 439config MMC1_CD_PIN 440 string "Card detect pin for mmc1" 441 default "" 442 ---help--- 443 See MMC0_CD_PIN help text. 444 445config MMC2_CD_PIN 446 string "Card detect pin for mmc2" 447 default "" 448 ---help--- 449 See MMC0_CD_PIN help text. 450 451config MMC3_CD_PIN 452 string "Card detect pin for mmc3" 453 default "" 454 ---help--- 455 See MMC0_CD_PIN help text. 456 457config MMC1_PINS 458 string "Pins for mmc1" 459 default "" 460 ---help--- 461 Set the pins used for mmc1, when applicable. This takes a string in the 462 format understood by sunxi_name_to_gpio_bank, e.g. PH for port H. 463 464config MMC2_PINS 465 string "Pins for mmc2" 466 default "" 467 ---help--- 468 See MMC1_PINS help text. 469 470config MMC3_PINS 471 string "Pins for mmc3" 472 default "" 473 ---help--- 474 See MMC1_PINS help text. 475 476config MMC_SUNXI_SLOT_EXTRA 477 int "mmc extra slot number" 478 default -1 479 ---help--- 480 sunxi builds always enable mmc0, some boards also have a second sdcard 481 slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable 482 support for this. 483 484config INITIAL_USB_SCAN_DELAY 485 int "delay initial usb scan by x ms to allow builtin devices to init" 486 default 0 487 ---help--- 488 Some boards have on board usb devices which need longer than the 489 USB spec's 1 second to connect from board powerup. Set this config 490 option to a non 0 value to add an extra delay before the first usb 491 bus scan. 492 493config USB0_VBUS_PIN 494 string "Vbus enable pin for usb0 (otg)" 495 default "" 496 ---help--- 497 Set the Vbus enable pin for usb0 (otg). This takes a string in the 498 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. 499 500config USB0_VBUS_DET 501 string "Vbus detect pin for usb0 (otg)" 502 default "" 503 ---help--- 504 Set the Vbus detect pin for usb0 (otg). This takes a string in the 505 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. 506 507config USB0_ID_DET 508 string "ID detect pin for usb0 (otg)" 509 default "" 510 ---help--- 511 Set the ID detect pin for usb0 (otg). This takes a string in the 512 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. 513 514config USB1_VBUS_PIN 515 string "Vbus enable pin for usb1 (ehci0)" 516 default "PH6" if MACH_SUN4I || MACH_SUN7I 517 default "PH27" if MACH_SUN6I 518 ---help--- 519 Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes 520 a string in the format understood by sunxi_name_to_gpio, e.g. 521 PH1 for pin 1 of port H. 522 523config USB2_VBUS_PIN 524 string "Vbus enable pin for usb2 (ehci1)" 525 default "PH3" if MACH_SUN4I || MACH_SUN7I 526 default "PH24" if MACH_SUN6I 527 ---help--- 528 See USB1_VBUS_PIN help text. 529 530config USB3_VBUS_PIN 531 string "Vbus enable pin for usb3 (ehci2)" 532 default "" 533 ---help--- 534 See USB1_VBUS_PIN help text. 535 536config I2C0_ENABLE 537 bool "Enable I2C/TWI controller 0" 538 default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_R40 539 default n if MACH_SUN6I || MACH_SUN8I 540 select CMD_I2C 541 ---help--- 542 This allows enabling I2C/TWI controller 0 by muxing its pins, enabling 543 its clock and setting up the bus. This is especially useful on devices 544 with slaves connected to the bus or with pins exposed through e.g. an 545 expansion port/header. 546 547config I2C1_ENABLE 548 bool "Enable I2C/TWI controller 1" 549 default n 550 select CMD_I2C 551 ---help--- 552 See I2C0_ENABLE help text. 553 554config I2C2_ENABLE 555 bool "Enable I2C/TWI controller 2" 556 default n 557 select CMD_I2C 558 ---help--- 559 See I2C0_ENABLE help text. 560 561if MACH_SUN6I || MACH_SUN7I 562config I2C3_ENABLE 563 bool "Enable I2C/TWI controller 3" 564 default n 565 select CMD_I2C 566 ---help--- 567 See I2C0_ENABLE help text. 568endif 569 570if SUNXI_GEN_SUN6I 571config R_I2C_ENABLE 572 bool "Enable the PRCM I2C/TWI controller" 573 # This is used for the pmic on H3 574 default y if SY8106A_POWER 575 select CMD_I2C 576 ---help--- 577 Set this to y to enable the I2C controller which is part of the PRCM. 578endif 579 580if MACH_SUN7I 581config I2C4_ENABLE 582 bool "Enable I2C/TWI controller 4" 583 default n 584 select CMD_I2C 585 ---help--- 586 See I2C0_ENABLE help text. 587endif 588 589config AXP_GPIO 590 bool "Enable support for gpio-s on axp PMICs" 591 default n 592 ---help--- 593 Say Y here to enable support for the gpio pins of the axp PMIC ICs. 594 595config VIDEO 596 bool "Enable graphical uboot console on HDMI, LCD or VGA" 597 depends on !MACH_SUN8I_A83T 598 depends on !MACH_SUNXI_H3_H5 599 depends on !MACH_SUN8I_R40 600 depends on !MACH_SUN8I_V3S 601 depends on !MACH_SUN9I 602 depends on !MACH_SUN50I 603 default y 604 ---help--- 605 Say Y here to add support for using a cfb console on the HDMI, LCD 606 or VGA output found on most sunxi devices. See doc/README.video for 607 info on how to select the video output and mode. 608 609config VIDEO_HDMI 610 bool "HDMI output support" 611 depends on VIDEO && !MACH_SUN8I 612 default y 613 ---help--- 614 Say Y here to add support for outputting video over HDMI. 615 616config VIDEO_VGA 617 bool "VGA output support" 618 depends on VIDEO && (MACH_SUN4I || MACH_SUN7I) 619 default n 620 ---help--- 621 Say Y here to add support for outputting video over VGA. 622 623config VIDEO_VGA_VIA_LCD 624 bool "VGA via LCD controller support" 625 depends on VIDEO && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I) 626 default n 627 ---help--- 628 Say Y here to add support for external DACs connected to the parallel 629 LCD interface driving a VGA connector, such as found on the 630 Olimex A13 boards. 631 632config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH 633 bool "Force sync active high for VGA via LCD controller support" 634 depends on VIDEO_VGA_VIA_LCD 635 default n 636 ---help--- 637 Say Y here if you've a board which uses opendrain drivers for the vga 638 hsync and vsync signals. Opendrain drivers cannot generate steep enough 639 positive edges for a stable video output, so on boards with opendrain 640 drivers the sync signals must always be active high. 641 642config VIDEO_VGA_EXTERNAL_DAC_EN 643 string "LCD panel power enable pin" 644 depends on VIDEO_VGA_VIA_LCD 645 default "" 646 ---help--- 647 Set the enable pin for the external VGA DAC. This takes a string in the 648 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. 649 650config VIDEO_COMPOSITE 651 bool "Composite video output support" 652 depends on VIDEO && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I) 653 default n 654 ---help--- 655 Say Y here to add support for outputting composite video. 656 657config VIDEO_LCD_MODE 658 string "LCD panel timing details" 659 depends on VIDEO 660 default "" 661 ---help--- 662 LCD panel timing details string, leave empty if there is no LCD panel. 663 This is in drivers/video/videomodes.c: video_get_params() format, e.g. 664 x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0 665 Also see: http://linux-sunxi.org/LCD 666 667config VIDEO_LCD_DCLK_PHASE 668 int "LCD panel display clock phase" 669 depends on VIDEO 670 default 1 671 ---help--- 672 Select LCD panel display clock phase shift, range 0-3. 673 674config VIDEO_LCD_POWER 675 string "LCD panel power enable pin" 676 depends on VIDEO 677 default "" 678 ---help--- 679 Set the power enable pin for the LCD panel. This takes a string in the 680 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. 681 682config VIDEO_LCD_RESET 683 string "LCD panel reset pin" 684 depends on VIDEO 685 default "" 686 ---help--- 687 Set the reset pin for the LCD panel. This takes a string in the format 688 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. 689 690config VIDEO_LCD_BL_EN 691 string "LCD panel backlight enable pin" 692 depends on VIDEO 693 default "" 694 ---help--- 695 Set the backlight enable pin for the LCD panel. This takes a string in the 696 the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of 697 port H. 698 699config VIDEO_LCD_BL_PWM 700 string "LCD panel backlight pwm pin" 701 depends on VIDEO 702 default "" 703 ---help--- 704 Set the backlight pwm pin for the LCD panel. This takes a string in the 705 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. 706 707config VIDEO_LCD_BL_PWM_ACTIVE_LOW 708 bool "LCD panel backlight pwm is inverted" 709 depends on VIDEO 710 default y 711 ---help--- 712 Set this if the backlight pwm output is active low. 713 714config VIDEO_LCD_PANEL_I2C 715 bool "LCD panel needs to be configured via i2c" 716 depends on VIDEO 717 default n 718 select CMD_I2C 719 ---help--- 720 Say y here if the LCD panel needs to be configured via i2c. This 721 will add a bitbang i2c controller using gpios to talk to the LCD. 722 723config VIDEO_LCD_PANEL_I2C_SDA 724 string "LCD panel i2c interface SDA pin" 725 depends on VIDEO_LCD_PANEL_I2C 726 default "PG12" 727 ---help--- 728 Set the SDA pin for the LCD i2c interface. This takes a string in the 729 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. 730 731config VIDEO_LCD_PANEL_I2C_SCL 732 string "LCD panel i2c interface SCL pin" 733 depends on VIDEO_LCD_PANEL_I2C 734 default "PG10" 735 ---help--- 736 Set the SCL pin for the LCD i2c interface. This takes a string in the 737 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. 738 739 740# Note only one of these may be selected at a time! But hidden choices are 741# not supported by Kconfig 742config VIDEO_LCD_IF_PARALLEL 743 bool 744 745config VIDEO_LCD_IF_LVDS 746 bool 747 748config SUNXI_DE2 749 bool 750 default n 751 752config VIDEO_DE2 753 bool "Display Engine 2 video driver" 754 depends on SUNXI_DE2 755 select DM_VIDEO 756 select DISPLAY 757 default y 758 ---help--- 759 Say y here if you want to build DE2 video driver which is present on 760 newer SoCs. Currently only HDMI output is supported. 761 762 763choice 764 prompt "LCD panel support" 765 depends on VIDEO 766 ---help--- 767 Select which type of LCD panel to support. 768 769config VIDEO_LCD_PANEL_PARALLEL 770 bool "Generic parallel interface LCD panel" 771 select VIDEO_LCD_IF_PARALLEL 772 773config VIDEO_LCD_PANEL_LVDS 774 bool "Generic lvds interface LCD panel" 775 select VIDEO_LCD_IF_LVDS 776 777config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828 778 bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip" 779 select VIDEO_LCD_SSD2828 780 select VIDEO_LCD_IF_PARALLEL 781 ---help--- 782 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0 783 784config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804 785 bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip" 786 select VIDEO_LCD_ANX9804 787 select VIDEO_LCD_IF_PARALLEL 788 select VIDEO_LCD_PANEL_I2C 789 ---help--- 790 Select this for eDP LCD panels with 4 lanes running at 1.62G, 791 connected via an ANX9804 bridge chip. 792 793config VIDEO_LCD_PANEL_HITACHI_TX18D42VM 794 bool "Hitachi tx18d42vm LCD panel" 795 select VIDEO_LCD_HITACHI_TX18D42VM 796 select VIDEO_LCD_IF_LVDS 797 ---help--- 798 7.85" 1024x768 Hitachi tx18d42vm LCD panel support 799 800config VIDEO_LCD_TL059WV5C0 801 bool "tl059wv5c0 LCD panel" 802 select VIDEO_LCD_PANEL_I2C 803 select VIDEO_LCD_IF_PARALLEL 804 ---help--- 805 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and 806 Aigo M60/M608/M606 tablets. 807 808endchoice 809 810config SATAPWR 811 string "SATA power pin" 812 default "" 813 help 814 Set the pins used to power the SATA. This takes a string in the 815 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of 816 port H. 817 818config GMAC_TX_DELAY 819 int "GMAC Transmit Clock Delay Chain" 820 default 0 821 ---help--- 822 Set the GMAC Transmit Clock Delay Chain value. 823 824config SPL_STACK_R_ADDR 825 default 0x4fe00000 if MACH_SUN4I 826 default 0x4fe00000 if MACH_SUN5I 827 default 0x4fe00000 if MACH_SUN6I 828 default 0x4fe00000 if MACH_SUN7I 829 default 0x4fe00000 if MACH_SUN8I 830 default 0x2fe00000 if MACH_SUN9I 831 default 0x4fe00000 if MACH_SUN50I 832 833endif 834