1if ARCH_SUNXI 2 3config IDENT_STRING 4 default " Allwinner Technology" 5 6config SUNXI_HIGH_SRAM 7 bool 8 default n 9 ---help--- 10 Older Allwinner SoCs have their mask boot ROM mapped just below 4GB, 11 with the first SRAM region being located at address 0. 12 Some newer SoCs map the boot ROM at address 0 instead and move the 13 SRAM to 64KB, just behind the mask ROM. 14 Chips using the latter setup are supposed to select this option to 15 adjust the addresses accordingly. 16 17# Note only one of these may be selected at a time! But hidden choices are 18# not supported by Kconfig 19config SUNXI_GEN_SUN4I 20 bool 21 ---help--- 22 Select this for sunxi SoCs which have resets and clocks set up 23 as the original A10 (mach-sun4i). 24 25config SUNXI_GEN_SUN6I 26 bool 27 ---help--- 28 Select this for sunxi SoCs which have sun6i like periphery, like 29 separate ahb reset control registers, custom pmic bus, new style 30 watchdog, etc. 31 32config SUNXI_DRAM_DW 33 bool 34 ---help--- 35 Select this for sunxi SoCs which uses a DRAM controller like the 36 DesignWare controller used in H3, mainly SoCs after H3, which do 37 not have official open-source DRAM initialization code, but can 38 use modified H3 DRAM initialization code. 39 40if SUNXI_DRAM_DW 41config SUNXI_DRAM_DW_16BIT 42 bool 43 ---help--- 44 Select this for sunxi SoCs with DesignWare DRAM controller and 45 have only 16-bit memory buswidth. 46 47config SUNXI_DRAM_DW_32BIT 48 bool 49 ---help--- 50 Select this for sunxi SoCs with DesignWare DRAM controller with 51 32-bit memory buswidth. 52endif 53 54config MACH_SUNXI_H3_H5 55 bool 56 select DM_I2C 57 select SUNXI_DE2 58 select SUNXI_DRAM_DW 59 select SUNXI_DRAM_DW_32BIT 60 select SUNXI_GEN_SUN6I 61 select SUPPORT_SPL 62 63choice 64 prompt "Sunxi SoC Variant" 65 optional 66 67config MACH_SUN4I 68 bool "sun4i (Allwinner A10)" 69 select CPU_V7 70 select ARM_CORTEX_CPU_IS_UP 71 select SUNXI_GEN_SUN4I 72 select SUPPORT_SPL 73 74config MACH_SUN5I 75 bool "sun5i (Allwinner A13)" 76 select CPU_V7 77 select ARM_CORTEX_CPU_IS_UP 78 select SUNXI_GEN_SUN4I 79 select SUPPORT_SPL 80 81config MACH_SUN6I 82 bool "sun6i (Allwinner A31)" 83 select CPU_V7 84 select CPU_V7_HAS_NONSEC 85 select CPU_V7_HAS_VIRT 86 select ARCH_SUPPORT_PSCI 87 select SUNXI_GEN_SUN6I 88 select SUPPORT_SPL 89 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT 90 91config MACH_SUN7I 92 bool "sun7i (Allwinner A20)" 93 select CPU_V7 94 select CPU_V7_HAS_NONSEC 95 select CPU_V7_HAS_VIRT 96 select ARCH_SUPPORT_PSCI 97 select SUNXI_GEN_SUN4I 98 select SUPPORT_SPL 99 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT 100 101config MACH_SUN8I_A23 102 bool "sun8i (Allwinner A23)" 103 select CPU_V7 104 select CPU_V7_HAS_NONSEC 105 select CPU_V7_HAS_VIRT 106 select ARCH_SUPPORT_PSCI 107 select SUNXI_GEN_SUN6I 108 select SUPPORT_SPL 109 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT 110 111config MACH_SUN8I_A33 112 bool "sun8i (Allwinner A33)" 113 select CPU_V7 114 select CPU_V7_HAS_NONSEC 115 select CPU_V7_HAS_VIRT 116 select ARCH_SUPPORT_PSCI 117 select SUNXI_GEN_SUN6I 118 select SUPPORT_SPL 119 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT 120 121config MACH_SUN8I_A83T 122 bool "sun8i (Allwinner A83T)" 123 select CPU_V7 124 select SUNXI_GEN_SUN6I 125 select SUPPORT_SPL 126 127config MACH_SUN8I_H3 128 bool "sun8i (Allwinner H3)" 129 select CPU_V7 130 select CPU_V7_HAS_NONSEC 131 select CPU_V7_HAS_VIRT 132 select ARCH_SUPPORT_PSCI 133 select MACH_SUNXI_H3_H5 134 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT 135 136config MACH_SUN8I_R40 137 bool "sun8i (Allwinner R40)" 138 select CPU_V7 139 select CPU_V7_HAS_NONSEC 140 select CPU_V7_HAS_VIRT 141 select ARCH_SUPPORT_PSCI 142 select SUNXI_GEN_SUN6I 143 select SUPPORT_SPL 144 select SUNXI_DRAM_DW 145 select SUNXI_DRAM_DW_32BIT 146 147config MACH_SUN8I_V3S 148 bool "sun8i (Allwinner V3s)" 149 select CPU_V7 150 select CPU_V7_HAS_NONSEC 151 select CPU_V7_HAS_VIRT 152 select ARCH_SUPPORT_PSCI 153 select SUNXI_GEN_SUN6I 154 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT 155 156config MACH_SUN9I 157 bool "sun9i (Allwinner A80)" 158 select CPU_V7 159 select SUNXI_HIGH_SRAM 160 select SUNXI_GEN_SUN6I 161 select SUPPORT_SPL 162 163config MACH_SUN50I 164 bool "sun50i (Allwinner A64)" 165 select ARM64 166 select DM_I2C 167 select SUNXI_DE2 168 select SUNXI_GEN_SUN6I 169 select SUNXI_HIGH_SRAM 170 select SUPPORT_SPL 171 select SUNXI_DRAM_DW 172 select SUNXI_DRAM_DW_32BIT 173 select FIT 174 select SPL_LOAD_FIT 175 176config MACH_SUN50I_H5 177 bool "sun50i (Allwinner H5)" 178 select ARM64 179 select MACH_SUNXI_H3_H5 180 select SUNXI_HIGH_SRAM 181 select FIT 182 select SPL_LOAD_FIT 183 184endchoice 185 186# The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33" 187config MACH_SUN8I 188 bool 189 default y if MACH_SUN8I_A23 190 default y if MACH_SUN8I_A33 191 default y if MACH_SUN8I_A83T 192 default y if MACH_SUNXI_H3_H5 193 default y if MACH_SUN8I_R40 194 default y if MACH_SUN8I_V3S 195 196config RESERVE_ALLWINNER_BOOT0_HEADER 197 bool "reserve space for Allwinner boot0 header" 198 select ENABLE_ARM_SOC_BOOT0_HOOK 199 ---help--- 200 Prepend a 1536 byte (empty) header to the U-Boot image file, to be 201 filled with magic values post build. The Allwinner provided boot0 202 blob relies on this information to load and execute U-Boot. 203 Only needed on 64-bit Allwinner boards so far when using boot0. 204 205config ARM_BOOT_HOOK_RMR 206 bool 207 depends on ARM64 208 default y 209 select ENABLE_ARM_SOC_BOOT0_HOOK 210 ---help--- 211 Insert some ARM32 code at the very beginning of the U-Boot binary 212 which uses an RMR register write to bring the core into AArch64 mode. 213 The very first instruction acts as a switch, since it's carefully 214 chosen to be a NOP in one mode and a branch in the other, so the 215 code would only be executed if not already in AArch64. 216 This allows both the SPL and the U-Boot proper to be entered in 217 either mode and switch to AArch64 if needed. 218 219if SUNXI_DRAM_DW 220config SUNXI_DRAM_DDR3 221 bool 222 223config SUNXI_DRAM_DDR2 224 bool 225 226choice 227 prompt "DRAM Type and Timing" 228 default SUNXI_DRAM_DDR3_1333 229 230config SUNXI_DRAM_DDR3_1333 231 bool "DDR3 1333" 232 select SUNXI_DRAM_DDR3 233 ---help--- 234 This option is the original only supported memory type, which suits 235 many H3/H5/A64 boards available now. 236 237config SUNXI_DRAM_DDR2_V3S 238 bool "DDR2 found in V3s chip" 239 select SUNXI_DRAM_DDR2 240 ---help--- 241 This option is only for the DDR2 memory chip which is co-packaged in 242 Allwinner V3s SoC. 243 244endchoice 245endif 246 247config DRAM_TYPE 248 int "sunxi dram type" 249 depends on MACH_SUN8I_A83T 250 default 3 251 ---help--- 252 Set the dram type, 3: DDR3, 7: LPDDR3 253 254config DRAM_CLK 255 int "sunxi dram clock speed" 256 default 792 if MACH_SUN9I 257 default 648 if MACH_SUN8I_R40 258 default 312 if MACH_SUN6I || MACH_SUN8I 259 default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I 260 default 672 if MACH_SUN50I 261 ---help--- 262 Set the dram clock speed, valid range 240 - 480 (prior to sun9i), 263 must be a multiple of 24. For the sun9i (A80), the tested values 264 (for DDR3-1600) are 312 to 792. 265 266if MACH_SUN5I || MACH_SUN7I 267config DRAM_MBUS_CLK 268 int "sunxi mbus clock speed" 269 default 300 270 ---help--- 271 Set the mbus clock speed. The maximum on sun5i hardware is 300MHz. 272 273endif 274 275config DRAM_ZQ 276 int "sunxi dram zq value" 277 default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I 278 default 127 if MACH_SUN7I 279 default 3881979 if MACH_SUN8I_R40 280 default 4145117 if MACH_SUN9I 281 default 3881915 if MACH_SUN50I 282 ---help--- 283 Set the dram zq value. 284 285config DRAM_ODT_EN 286 bool "sunxi dram odt enable" 287 default n if !MACH_SUN8I_A23 288 default y if MACH_SUN8I_A23 289 default y if MACH_SUN8I_R40 290 default y if MACH_SUN50I 291 ---help--- 292 Select this to enable dram odt (on die termination). 293 294if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I 295config DRAM_EMR1 296 int "sunxi dram emr1 value" 297 default 0 if MACH_SUN4I 298 default 4 if MACH_SUN5I || MACH_SUN7I 299 ---help--- 300 Set the dram controller emr1 value. 301 302config DRAM_TPR3 303 hex "sunxi dram tpr3 value" 304 default 0 305 ---help--- 306 Set the dram controller tpr3 parameter. This parameter configures 307 the delay on the command lane and also phase shifts, which are 308 applied for sampling incoming read data. The default value 0 309 means that no phase/delay adjustments are necessary. Properly 310 configuring this parameter increases reliability at high DRAM 311 clock speeds. 312 313config DRAM_DQS_GATING_DELAY 314 hex "sunxi dram dqs_gating_delay value" 315 default 0 316 ---help--- 317 Set the dram controller dqs_gating_delay parmeter. Each byte 318 encodes the DQS gating delay for each byte lane. The delay 319 granularity is 1/4 cycle. For example, the value 0x05060606 320 means that the delay is 5 quarter-cycles for one lane (1.25 321 cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes. 322 The default value 0 means autodetection. The results of hardware 323 autodetection are not very reliable and depend on the chip 324 temperature (sometimes producing different results on cold start 325 and warm reboot). But the accuracy of hardware autodetection 326 is usually good enough, unless running at really high DRAM 327 clocks speeds (up to 600MHz). If unsure, keep as 0. 328 329choice 330 prompt "sunxi dram timings" 331 default DRAM_TIMINGS_VENDOR_MAGIC 332 ---help--- 333 Select the timings of the DDR3 chips. 334 335config DRAM_TIMINGS_VENDOR_MAGIC 336 bool "Magic vendor timings from Android" 337 ---help--- 338 The same DRAM timings as in the Allwinner boot0 bootloader. 339 340config DRAM_TIMINGS_DDR3_1066F_1333H 341 bool "JEDEC DDR3-1333H with down binning to DDR3-1066F" 342 ---help--- 343 Use the timings of the standard JEDEC DDR3-1066F speed bin for 344 DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin 345 for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips 346 used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333 347 or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm 348 that down binning to DDR3-1066F is supported (because DDR3-1066F 349 uses a bit faster timings than DDR3-1333H). 350 351config DRAM_TIMINGS_DDR3_800E_1066G_1333J 352 bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J" 353 ---help--- 354 Use the timings of the slowest possible JEDEC speed bin for the 355 selected DRAM_CLK. Depending on the DRAM_CLK value, it may be 356 DDR3-800E, DDR3-1066G or DDR3-1333J. 357 358endchoice 359 360endif 361 362if MACH_SUN8I_A23 363config DRAM_ODT_CORRECTION 364 int "sunxi dram odt correction value" 365 default 0 366 ---help--- 367 Set the dram odt correction value (range -255 - 255). In allwinner 368 fex files, this option is found in bits 8-15 of the u32 odt_en variable 369 in the [dram] section. When bit 31 of the odt_en variable is set 370 then the correction is negative. Usually the value for this is 0. 371endif 372 373config SYS_CLK_FREQ 374 default 1008000000 if MACH_SUN4I 375 default 1008000000 if MACH_SUN5I 376 default 1008000000 if MACH_SUN6I 377 default 912000000 if MACH_SUN7I 378 default 1008000000 if MACH_SUN8I 379 default 1008000000 if MACH_SUN9I 380 default 816000000 if MACH_SUN50I 381 382config SYS_CONFIG_NAME 383 default "sun4i" if MACH_SUN4I 384 default "sun5i" if MACH_SUN5I 385 default "sun6i" if MACH_SUN6I 386 default "sun7i" if MACH_SUN7I 387 default "sun8i" if MACH_SUN8I 388 default "sun9i" if MACH_SUN9I 389 default "sun50i" if MACH_SUN50I 390 391config SYS_BOARD 392 default "sunxi" 393 394config SYS_SOC 395 default "sunxi" 396 397config UART0_PORT_F 398 bool "UART0 on MicroSD breakout board" 399 default n 400 ---help--- 401 Repurpose the SD card slot for getting access to the UART0 serial 402 console. Primarily useful only for low level u-boot debugging on 403 tablets, where normal UART0 is difficult to access and requires 404 device disassembly and/or soldering. As the SD card can't be used 405 at the same time, the system can be only booted in the FEL mode. 406 Only enable this if you really know what you are doing. 407 408config OLD_SUNXI_KERNEL_COMPAT 409 bool "Enable workarounds for booting old kernels" 410 default n 411 ---help--- 412 Set this to enable various workarounds for old kernels, this results in 413 sub-optimal settings for newer kernels, only enable if needed. 414 415config MACPWR 416 string "MAC power pin" 417 default "" 418 help 419 Set the pin used to power the MAC. This takes a string in the format 420 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. 421 422config MMC0_CD_PIN 423 string "Card detect pin for mmc0" 424 default "PF6" if MACH_SUN8I_A83T || MACH_SUNXI_H3_H5 || MACH_SUN50I 425 default "" 426 ---help--- 427 Set the card detect pin for mmc0, leave empty to not use cd. This 428 takes a string in the format understood by sunxi_name_to_gpio, e.g. 429 PH1 for pin 1 of port H. 430 431config MMC1_CD_PIN 432 string "Card detect pin for mmc1" 433 default "" 434 ---help--- 435 See MMC0_CD_PIN help text. 436 437config MMC2_CD_PIN 438 string "Card detect pin for mmc2" 439 default "" 440 ---help--- 441 See MMC0_CD_PIN help text. 442 443config MMC3_CD_PIN 444 string "Card detect pin for mmc3" 445 default "" 446 ---help--- 447 See MMC0_CD_PIN help text. 448 449config MMC1_PINS 450 string "Pins for mmc1" 451 default "" 452 ---help--- 453 Set the pins used for mmc1, when applicable. This takes a string in the 454 format understood by sunxi_name_to_gpio_bank, e.g. PH for port H. 455 456config MMC2_PINS 457 string "Pins for mmc2" 458 default "" 459 ---help--- 460 See MMC1_PINS help text. 461 462config MMC3_PINS 463 string "Pins for mmc3" 464 default "" 465 ---help--- 466 See MMC1_PINS help text. 467 468config MMC_SUNXI_SLOT_EXTRA 469 int "mmc extra slot number" 470 default -1 471 ---help--- 472 sunxi builds always enable mmc0, some boards also have a second sdcard 473 slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable 474 support for this. 475 476config INITIAL_USB_SCAN_DELAY 477 int "delay initial usb scan by x ms to allow builtin devices to init" 478 default 0 479 ---help--- 480 Some boards have on board usb devices which need longer than the 481 USB spec's 1 second to connect from board powerup. Set this config 482 option to a non 0 value to add an extra delay before the first usb 483 bus scan. 484 485config USB0_VBUS_PIN 486 string "Vbus enable pin for usb0 (otg)" 487 default "" 488 ---help--- 489 Set the Vbus enable pin for usb0 (otg). This takes a string in the 490 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. 491 492config USB0_VBUS_DET 493 string "Vbus detect pin for usb0 (otg)" 494 default "" 495 ---help--- 496 Set the Vbus detect pin for usb0 (otg). This takes a string in the 497 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. 498 499config USB0_ID_DET 500 string "ID detect pin for usb0 (otg)" 501 default "" 502 ---help--- 503 Set the ID detect pin for usb0 (otg). This takes a string in the 504 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. 505 506config USB1_VBUS_PIN 507 string "Vbus enable pin for usb1 (ehci0)" 508 default "PH6" if MACH_SUN4I || MACH_SUN7I 509 default "PH27" if MACH_SUN6I 510 ---help--- 511 Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes 512 a string in the format understood by sunxi_name_to_gpio, e.g. 513 PH1 for pin 1 of port H. 514 515config USB2_VBUS_PIN 516 string "Vbus enable pin for usb2 (ehci1)" 517 default "PH3" if MACH_SUN4I || MACH_SUN7I 518 default "PH24" if MACH_SUN6I 519 ---help--- 520 See USB1_VBUS_PIN help text. 521 522config USB3_VBUS_PIN 523 string "Vbus enable pin for usb3 (ehci2)" 524 default "" 525 ---help--- 526 See USB1_VBUS_PIN help text. 527 528config I2C0_ENABLE 529 bool "Enable I2C/TWI controller 0" 530 default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_R40 531 default n if MACH_SUN6I || MACH_SUN8I 532 select CMD_I2C 533 ---help--- 534 This allows enabling I2C/TWI controller 0 by muxing its pins, enabling 535 its clock and setting up the bus. This is especially useful on devices 536 with slaves connected to the bus or with pins exposed through e.g. an 537 expansion port/header. 538 539config I2C1_ENABLE 540 bool "Enable I2C/TWI controller 1" 541 default n 542 select CMD_I2C 543 ---help--- 544 See I2C0_ENABLE help text. 545 546config I2C2_ENABLE 547 bool "Enable I2C/TWI controller 2" 548 default n 549 select CMD_I2C 550 ---help--- 551 See I2C0_ENABLE help text. 552 553if MACH_SUN6I || MACH_SUN7I 554config I2C3_ENABLE 555 bool "Enable I2C/TWI controller 3" 556 default n 557 select CMD_I2C 558 ---help--- 559 See I2C0_ENABLE help text. 560endif 561 562if SUNXI_GEN_SUN6I 563config R_I2C_ENABLE 564 bool "Enable the PRCM I2C/TWI controller" 565 # This is used for the pmic on H3 566 default y if SY8106A_POWER 567 select CMD_I2C 568 ---help--- 569 Set this to y to enable the I2C controller which is part of the PRCM. 570endif 571 572if MACH_SUN7I 573config I2C4_ENABLE 574 bool "Enable I2C/TWI controller 4" 575 default n 576 select CMD_I2C 577 ---help--- 578 See I2C0_ENABLE help text. 579endif 580 581config AXP_GPIO 582 bool "Enable support for gpio-s on axp PMICs" 583 default n 584 ---help--- 585 Say Y here to enable support for the gpio pins of the axp PMIC ICs. 586 587config VIDEO 588 bool "Enable graphical uboot console on HDMI, LCD or VGA" 589 depends on !MACH_SUN8I_A83T 590 depends on !MACH_SUNXI_H3_H5 591 depends on !MACH_SUN8I_R40 592 depends on !MACH_SUN8I_V3S 593 depends on !MACH_SUN9I 594 depends on !MACH_SUN50I 595 default y 596 ---help--- 597 Say Y here to add support for using a cfb console on the HDMI, LCD 598 or VGA output found on most sunxi devices. See doc/README.video for 599 info on how to select the video output and mode. 600 601config VIDEO_HDMI 602 bool "HDMI output support" 603 depends on VIDEO && !MACH_SUN8I 604 default y 605 ---help--- 606 Say Y here to add support for outputting video over HDMI. 607 608config VIDEO_VGA 609 bool "VGA output support" 610 depends on VIDEO && (MACH_SUN4I || MACH_SUN7I) 611 default n 612 ---help--- 613 Say Y here to add support for outputting video over VGA. 614 615config VIDEO_VGA_VIA_LCD 616 bool "VGA via LCD controller support" 617 depends on VIDEO && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I) 618 default n 619 ---help--- 620 Say Y here to add support for external DACs connected to the parallel 621 LCD interface driving a VGA connector, such as found on the 622 Olimex A13 boards. 623 624config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH 625 bool "Force sync active high for VGA via LCD controller support" 626 depends on VIDEO_VGA_VIA_LCD 627 default n 628 ---help--- 629 Say Y here if you've a board which uses opendrain drivers for the vga 630 hsync and vsync signals. Opendrain drivers cannot generate steep enough 631 positive edges for a stable video output, so on boards with opendrain 632 drivers the sync signals must always be active high. 633 634config VIDEO_VGA_EXTERNAL_DAC_EN 635 string "LCD panel power enable pin" 636 depends on VIDEO_VGA_VIA_LCD 637 default "" 638 ---help--- 639 Set the enable pin for the external VGA DAC. This takes a string in the 640 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. 641 642config VIDEO_COMPOSITE 643 bool "Composite video output support" 644 depends on VIDEO && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I) 645 default n 646 ---help--- 647 Say Y here to add support for outputting composite video. 648 649config VIDEO_LCD_MODE 650 string "LCD panel timing details" 651 depends on VIDEO 652 default "" 653 ---help--- 654 LCD panel timing details string, leave empty if there is no LCD panel. 655 This is in drivers/video/videomodes.c: video_get_params() format, e.g. 656 x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0 657 Also see: http://linux-sunxi.org/LCD 658 659config VIDEO_LCD_DCLK_PHASE 660 int "LCD panel display clock phase" 661 depends on VIDEO 662 default 1 663 ---help--- 664 Select LCD panel display clock phase shift, range 0-3. 665 666config VIDEO_LCD_POWER 667 string "LCD panel power enable pin" 668 depends on VIDEO 669 default "" 670 ---help--- 671 Set the power enable pin for the LCD panel. This takes a string in the 672 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. 673 674config VIDEO_LCD_RESET 675 string "LCD panel reset pin" 676 depends on VIDEO 677 default "" 678 ---help--- 679 Set the reset pin for the LCD panel. This takes a string in the format 680 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. 681 682config VIDEO_LCD_BL_EN 683 string "LCD panel backlight enable pin" 684 depends on VIDEO 685 default "" 686 ---help--- 687 Set the backlight enable pin for the LCD panel. This takes a string in the 688 the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of 689 port H. 690 691config VIDEO_LCD_BL_PWM 692 string "LCD panel backlight pwm pin" 693 depends on VIDEO 694 default "" 695 ---help--- 696 Set the backlight pwm pin for the LCD panel. This takes a string in the 697 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. 698 699config VIDEO_LCD_BL_PWM_ACTIVE_LOW 700 bool "LCD panel backlight pwm is inverted" 701 depends on VIDEO 702 default y 703 ---help--- 704 Set this if the backlight pwm output is active low. 705 706config VIDEO_LCD_PANEL_I2C 707 bool "LCD panel needs to be configured via i2c" 708 depends on VIDEO 709 default n 710 select CMD_I2C 711 ---help--- 712 Say y here if the LCD panel needs to be configured via i2c. This 713 will add a bitbang i2c controller using gpios to talk to the LCD. 714 715config VIDEO_LCD_PANEL_I2C_SDA 716 string "LCD panel i2c interface SDA pin" 717 depends on VIDEO_LCD_PANEL_I2C 718 default "PG12" 719 ---help--- 720 Set the SDA pin for the LCD i2c interface. This takes a string in the 721 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. 722 723config VIDEO_LCD_PANEL_I2C_SCL 724 string "LCD panel i2c interface SCL pin" 725 depends on VIDEO_LCD_PANEL_I2C 726 default "PG10" 727 ---help--- 728 Set the SCL pin for the LCD i2c interface. This takes a string in the 729 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. 730 731 732# Note only one of these may be selected at a time! But hidden choices are 733# not supported by Kconfig 734config VIDEO_LCD_IF_PARALLEL 735 bool 736 737config VIDEO_LCD_IF_LVDS 738 bool 739 740config SUNXI_DE2 741 bool 742 default n 743 744config VIDEO_DE2 745 bool "Display Engine 2 video driver" 746 depends on SUNXI_DE2 747 select DM_VIDEO 748 select DISPLAY 749 default y 750 ---help--- 751 Say y here if you want to build DE2 video driver which is present on 752 newer SoCs. Currently only HDMI output is supported. 753 754 755choice 756 prompt "LCD panel support" 757 depends on VIDEO 758 ---help--- 759 Select which type of LCD panel to support. 760 761config VIDEO_LCD_PANEL_PARALLEL 762 bool "Generic parallel interface LCD panel" 763 select VIDEO_LCD_IF_PARALLEL 764 765config VIDEO_LCD_PANEL_LVDS 766 bool "Generic lvds interface LCD panel" 767 select VIDEO_LCD_IF_LVDS 768 769config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828 770 bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip" 771 select VIDEO_LCD_SSD2828 772 select VIDEO_LCD_IF_PARALLEL 773 ---help--- 774 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0 775 776config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804 777 bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip" 778 select VIDEO_LCD_ANX9804 779 select VIDEO_LCD_IF_PARALLEL 780 select VIDEO_LCD_PANEL_I2C 781 ---help--- 782 Select this for eDP LCD panels with 4 lanes running at 1.62G, 783 connected via an ANX9804 bridge chip. 784 785config VIDEO_LCD_PANEL_HITACHI_TX18D42VM 786 bool "Hitachi tx18d42vm LCD panel" 787 select VIDEO_LCD_HITACHI_TX18D42VM 788 select VIDEO_LCD_IF_LVDS 789 ---help--- 790 7.85" 1024x768 Hitachi tx18d42vm LCD panel support 791 792config VIDEO_LCD_TL059WV5C0 793 bool "tl059wv5c0 LCD panel" 794 select VIDEO_LCD_PANEL_I2C 795 select VIDEO_LCD_IF_PARALLEL 796 ---help--- 797 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and 798 Aigo M60/M608/M606 tablets. 799 800endchoice 801 802config SATAPWR 803 string "SATA power pin" 804 default "" 805 help 806 Set the pins used to power the SATA. This takes a string in the 807 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of 808 port H. 809 810config GMAC_TX_DELAY 811 int "GMAC Transmit Clock Delay Chain" 812 default 0 813 ---help--- 814 Set the GMAC Transmit Clock Delay Chain value. 815 816config SPL_STACK_R_ADDR 817 default 0x4fe00000 if MACH_SUN4I 818 default 0x4fe00000 if MACH_SUN5I 819 default 0x4fe00000 if MACH_SUN6I 820 default 0x4fe00000 if MACH_SUN7I 821 default 0x4fe00000 if MACH_SUN8I 822 default 0x2fe00000 if MACH_SUN9I 823 default 0x4fe00000 if MACH_SUN50I 824 825endif 826