xref: /openbmc/u-boot/arch/arm/mach-sunxi/Kconfig (revision 66dae3bb)
1if ARCH_SUNXI
2
3config SPL_LDSCRIPT
4	default "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" if !ARM64
5
6config IDENT_STRING
7	default " Allwinner Technology"
8
9config DRAM_SUN4I
10	bool
11	help
12	  Select this dram controller driver for Sun4/5/7i platforms,
13	  like A10/A13/A20.
14
15config DRAM_SUN6I
16	bool
17	help
18	  Select this dram controller driver for Sun6i platforms,
19	  like A31/A31s.
20
21config DRAM_SUN8I_A23
22	bool
23	help
24	  Select this dram controller driver for Sun8i platforms,
25	  for A23 SOC.
26
27config DRAM_SUN8I_A33
28	bool
29	help
30	  Select this dram controller driver for Sun8i platforms,
31	  for A33 SOC.
32
33config DRAM_SUN8I_A83T
34	bool
35	help
36	  Select this dram controller driver for Sun8i platforms,
37	  for A83T SOC.
38
39config DRAM_SUN9I
40	bool
41	help
42	  Select this dram controller driver for Sun9i platforms,
43	  like A80.
44
45config SUN6I_P2WI
46	bool "Allwinner sun6i internal P2WI controller"
47	help
48	  If you say yes to this option, support will be included for the
49	  P2WI (Push/Pull 2 Wire Interface) controller embedded in some sunxi
50	  SOCs.
51	  The P2WI looks like an SMBus controller (which supports only byte
52	  accesses), except that it only supports one slave device.
53	  This interface is used to connect to specific PMIC devices (like the
54	  AXP221).
55
56config SUN6I_PRCM
57	bool
58	help
59	  Support for the PRCM (Power/Reset/Clock Management) unit available
60	  in A31 SoC.
61
62config AXP_PMIC_BUS
63	bool "Sunxi AXP PMIC bus access helpers"
64	help
65	  Select this PMIC bus access helpers for Sunxi platform PRCM or other
66	  AXP family PMIC devices.
67
68config SUN8I_RSB
69	bool "Allwinner sunXi Reduced Serial Bus Driver"
70	help
71	  Say y here to enable support for Allwinner's Reduced Serial Bus
72	  (RSB) support. This controller is responsible for communicating
73	  with various RSB based devices, such as AXP223, AXP8XX PMICs,
74	  and AC100/AC200 ICs.
75
76config SUNXI_HIGH_SRAM
77	bool
78	default n
79	---help---
80	Older Allwinner SoCs have their mask boot ROM mapped just below 4GB,
81	with the first SRAM region being located at address 0.
82	Some newer SoCs map the boot ROM at address 0 instead and move the
83	SRAM to 64KB, just behind the mask ROM.
84	Chips using the latter setup are supposed to select this option to
85	adjust the addresses accordingly.
86
87config SUNXI_A64_TIMER_ERRATUM
88	bool
89
90# Note only one of these may be selected at a time! But hidden choices are
91# not supported by Kconfig
92config SUNXI_GEN_SUN4I
93	bool
94	---help---
95	Select this for sunxi SoCs which have resets and clocks set up
96	as the original A10 (mach-sun4i).
97
98config SUNXI_GEN_SUN6I
99	bool
100	---help---
101	Select this for sunxi SoCs which have sun6i like periphery, like
102	separate ahb reset control registers, custom pmic bus, new style
103	watchdog, etc.
104
105config SUNXI_DRAM_DW
106	bool
107	---help---
108	Select this for sunxi SoCs which uses a DRAM controller like the
109	DesignWare controller used in H3, mainly SoCs after H3, which do
110	not have official open-source DRAM initialization code, but can
111	use modified H3 DRAM initialization code.
112
113if SUNXI_DRAM_DW
114config SUNXI_DRAM_DW_16BIT
115	bool
116	---help---
117	Select this for sunxi SoCs with DesignWare DRAM controller and
118	have only 16-bit memory buswidth.
119
120config SUNXI_DRAM_DW_32BIT
121	bool
122	---help---
123	Select this for sunxi SoCs with DesignWare DRAM controller with
124	32-bit memory buswidth.
125endif
126
127config MACH_SUNXI_H3_H5
128	bool
129	select DM_I2C
130	select PHY_SUN4I_USB
131	select SUNXI_DE2
132	select SUNXI_DRAM_DW
133	select SUNXI_DRAM_DW_32BIT
134	select SUNXI_GEN_SUN6I
135	select SUPPORT_SPL
136
137choice
138	prompt "Sunxi SoC Variant"
139	optional
140
141config MACH_SUN4I
142	bool "sun4i (Allwinner A10)"
143	select CPU_V7A
144	select ARM_CORTEX_CPU_IS_UP
145	select DM_MMC if MMC
146	select DM_SCSI if SCSI
147	select PHY_SUN4I_USB
148	select DRAM_SUN4I
149	select SUNXI_GEN_SUN4I
150	select SUPPORT_SPL
151
152config MACH_SUN5I
153	bool "sun5i (Allwinner A13)"
154	select CPU_V7A
155	select ARM_CORTEX_CPU_IS_UP
156	select DRAM_SUN4I
157	select PHY_SUN4I_USB
158	select SUNXI_GEN_SUN4I
159	select SUPPORT_SPL
160	imply CONS_INDEX_2 if !DM_SERIAL
161
162config MACH_SUN6I
163	bool "sun6i (Allwinner A31)"
164	select CPU_V7A
165	select CPU_V7_HAS_NONSEC
166	select CPU_V7_HAS_VIRT
167	select ARCH_SUPPORT_PSCI
168	select DRAM_SUN6I
169	select PHY_SUN4I_USB
170	select SUN6I_P2WI
171	select SUN6I_PRCM
172	select SUNXI_GEN_SUN6I
173	select SUPPORT_SPL
174	select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
175
176config MACH_SUN7I
177	bool "sun7i (Allwinner A20)"
178	select CPU_V7A
179	select CPU_V7_HAS_NONSEC
180	select CPU_V7_HAS_VIRT
181	select ARCH_SUPPORT_PSCI
182	select DRAM_SUN4I
183	select PHY_SUN4I_USB
184	select SUNXI_GEN_SUN4I
185	select SUPPORT_SPL
186	select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
187
188config MACH_SUN8I_A23
189	bool "sun8i (Allwinner A23)"
190	select CPU_V7A
191	select CPU_V7_HAS_NONSEC
192	select CPU_V7_HAS_VIRT
193	select ARCH_SUPPORT_PSCI
194	select DRAM_SUN8I_A23
195	select PHY_SUN4I_USB
196	select SUNXI_GEN_SUN6I
197	select SUPPORT_SPL
198	select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
199	imply CONS_INDEX_5 if !DM_SERIAL
200
201config MACH_SUN8I_A33
202	bool "sun8i (Allwinner A33)"
203	select CPU_V7A
204	select CPU_V7_HAS_NONSEC
205	select CPU_V7_HAS_VIRT
206	select ARCH_SUPPORT_PSCI
207	select DRAM_SUN8I_A33
208	select PHY_SUN4I_USB
209	select SUNXI_GEN_SUN6I
210	select SUPPORT_SPL
211	select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
212	imply CONS_INDEX_5 if !DM_SERIAL
213
214config MACH_SUN8I_A83T
215	bool "sun8i (Allwinner A83T)"
216	select CPU_V7A
217	select DRAM_SUN8I_A83T
218	select PHY_SUN4I_USB
219	select SUNXI_GEN_SUN6I
220	select MMC_SUNXI_HAS_NEW_MODE
221	select SUPPORT_SPL
222
223config MACH_SUN8I_H3
224	bool "sun8i (Allwinner H3)"
225	select CPU_V7A
226	select CPU_V7_HAS_NONSEC
227	select CPU_V7_HAS_VIRT
228	select ARCH_SUPPORT_PSCI
229	select MACH_SUNXI_H3_H5
230	select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
231
232config MACH_SUN8I_R40
233	bool "sun8i (Allwinner R40)"
234	select CPU_V7A
235	select CPU_V7_HAS_NONSEC
236	select CPU_V7_HAS_VIRT
237	select ARCH_SUPPORT_PSCI
238	select SUNXI_GEN_SUN6I
239	select SUPPORT_SPL
240	select SUNXI_DRAM_DW
241	select SUNXI_DRAM_DW_32BIT
242
243config MACH_SUN8I_V3S
244	bool "sun8i (Allwinner V3s)"
245	select CPU_V7A
246	select CPU_V7_HAS_NONSEC
247	select CPU_V7_HAS_VIRT
248	select ARCH_SUPPORT_PSCI
249	select SUNXI_GEN_SUN6I
250	select SUNXI_DRAM_DW
251	select SUNXI_DRAM_DW_16BIT
252	select SUPPORT_SPL
253	select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
254
255config MACH_SUN9I
256	bool "sun9i (Allwinner A80)"
257	select CPU_V7A
258	select DRAM_SUN9I
259	select SUN6I_PRCM
260	select SUNXI_HIGH_SRAM
261	select SUNXI_GEN_SUN6I
262	select SUN8I_RSB
263	select SUPPORT_SPL
264
265config MACH_SUN50I
266	bool "sun50i (Allwinner A64)"
267	select ARM64
268	select DM_I2C
269	select PHY_SUN4I_USB
270	select SUNXI_DE2
271	select SUNXI_GEN_SUN6I
272	select SUNXI_HIGH_SRAM
273	select SUPPORT_SPL
274	select SUNXI_DRAM_DW
275	select SUNXI_DRAM_DW_32BIT
276	select FIT
277	select SPL_LOAD_FIT
278	select SUNXI_A64_TIMER_ERRATUM
279
280config MACH_SUN50I_H5
281	bool "sun50i (Allwinner H5)"
282	select ARM64
283	select MACH_SUNXI_H3_H5
284	select SUNXI_HIGH_SRAM
285	select FIT
286	select SPL_LOAD_FIT
287
288endchoice
289
290# The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
291config MACH_SUN8I
292	bool
293	select SUN8I_RSB
294	select SUN6I_PRCM
295	default y if MACH_SUN8I_A23
296	default y if MACH_SUN8I_A33
297	default y if MACH_SUN8I_A83T
298	default y if MACH_SUNXI_H3_H5
299	default y if MACH_SUN8I_R40
300	default y if MACH_SUN8I_V3S
301
302config RESERVE_ALLWINNER_BOOT0_HEADER
303	bool "reserve space for Allwinner boot0 header"
304	select ENABLE_ARM_SOC_BOOT0_HOOK
305	---help---
306	Prepend a 1536 byte (empty) header to the U-Boot image file, to be
307	filled with magic values post build. The Allwinner provided boot0
308	blob relies on this information to load and execute U-Boot.
309	Only needed on 64-bit Allwinner boards so far when using boot0.
310
311config ARM_BOOT_HOOK_RMR
312	bool
313	depends on ARM64
314	default y
315	select ENABLE_ARM_SOC_BOOT0_HOOK
316	---help---
317	Insert some ARM32 code at the very beginning of the U-Boot binary
318	which uses an RMR register write to bring the core into AArch64 mode.
319	The very first instruction acts as a switch, since it's carefully
320	chosen to be a NOP in one mode and a branch in the other, so the
321	code would only be executed if not already in AArch64.
322	This allows both the SPL and the U-Boot proper to be entered in
323	either mode and switch to AArch64 if needed.
324
325if SUNXI_DRAM_DW
326config SUNXI_DRAM_DDR3
327	bool
328
329config SUNXI_DRAM_DDR2
330	bool
331
332config SUNXI_DRAM_LPDDR3
333	bool
334
335choice
336	prompt "DRAM Type and Timing"
337	default SUNXI_DRAM_DDR3_1333 if !MACH_SUN8I_V3S
338	default SUNXI_DRAM_DDR2_V3S if MACH_SUN8I_V3S
339
340config SUNXI_DRAM_DDR3_1333
341	bool "DDR3 1333"
342	select SUNXI_DRAM_DDR3
343	depends on !MACH_SUN8I_V3S
344	---help---
345	This option is the original only supported memory type, which suits
346	many H3/H5/A64 boards available now.
347
348config SUNXI_DRAM_LPDDR3_STOCK
349	bool "LPDDR3 with Allwinner stock configuration"
350	select SUNXI_DRAM_LPDDR3
351	---help---
352	This option is the LPDDR3 timing used by the stock boot0 by
353	Allwinner.
354
355config SUNXI_DRAM_DDR2_V3S
356	bool "DDR2 found in V3s chip"
357	select SUNXI_DRAM_DDR2
358	depends on MACH_SUN8I_V3S
359	---help---
360	This option is only for the DDR2 memory chip which is co-packaged in
361	Allwinner V3s SoC.
362
363endchoice
364endif
365
366config DRAM_TYPE
367	int "sunxi dram type"
368	depends on MACH_SUN8I_A83T
369	default 3
370	---help---
371	Set the dram type, 3: DDR3, 7: LPDDR3
372
373config DRAM_CLK
374	int "sunxi dram clock speed"
375	default 792 if MACH_SUN9I
376	default 648 if MACH_SUN8I_R40
377	default 312 if MACH_SUN6I || MACH_SUN8I
378	default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || \
379		       MACH_SUN8I_V3S
380	default 672 if MACH_SUN50I
381	---help---
382	Set the dram clock speed, valid range 240 - 480 (prior to sun9i),
383	must be a multiple of 24. For the sun9i (A80), the tested values
384	(for DDR3-1600) are 312 to 792.
385
386if MACH_SUN5I || MACH_SUN7I
387config DRAM_MBUS_CLK
388	int "sunxi mbus clock speed"
389	default 300
390	---help---
391	Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
392
393endif
394
395config DRAM_ZQ
396	int "sunxi dram zq value"
397	default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
398	default 127 if MACH_SUN7I
399	default 14779 if MACH_SUN8I_V3S
400	default 3881979 if MACH_SUN8I_R40
401	default 4145117 if MACH_SUN9I
402	default 3881915 if MACH_SUN50I
403	---help---
404	Set the dram zq value.
405
406config DRAM_ODT_EN
407	bool "sunxi dram odt enable"
408	default n if !MACH_SUN8I_A23
409	default y if MACH_SUN8I_A23
410	default y if MACH_SUN8I_R40
411	default y if MACH_SUN50I
412	---help---
413	Select this to enable dram odt (on die termination).
414
415if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
416config DRAM_EMR1
417	int "sunxi dram emr1 value"
418	default 0 if MACH_SUN4I
419	default 4 if MACH_SUN5I || MACH_SUN7I
420	---help---
421	Set the dram controller emr1 value.
422
423config DRAM_TPR3
424	hex "sunxi dram tpr3 value"
425	default 0
426	---help---
427	Set the dram controller tpr3 parameter. This parameter configures
428	the delay on the command lane and also phase shifts, which are
429	applied for sampling incoming read data. The default value 0
430	means that no phase/delay adjustments are necessary. Properly
431	configuring this parameter increases reliability at high DRAM
432	clock speeds.
433
434config DRAM_DQS_GATING_DELAY
435	hex "sunxi dram dqs_gating_delay value"
436	default 0
437	---help---
438	Set the dram controller dqs_gating_delay parmeter. Each byte
439	encodes the DQS gating delay for each byte lane. The delay
440	granularity is 1/4 cycle. For example, the value 0x05060606
441	means that the delay is 5 quarter-cycles for one lane (1.25
442	cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
443	The default value 0 means autodetection. The results of hardware
444	autodetection are not very reliable and depend on the chip
445	temperature (sometimes producing different results on cold start
446	and warm reboot). But the accuracy of hardware autodetection
447	is usually good enough, unless running at really high DRAM
448	clocks speeds (up to 600MHz). If unsure, keep as 0.
449
450choice
451	prompt "sunxi dram timings"
452	default DRAM_TIMINGS_VENDOR_MAGIC
453	---help---
454	Select the timings of the DDR3 chips.
455
456config DRAM_TIMINGS_VENDOR_MAGIC
457	bool "Magic vendor timings from Android"
458	---help---
459	The same DRAM timings as in the Allwinner boot0 bootloader.
460
461config DRAM_TIMINGS_DDR3_1066F_1333H
462	bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
463	---help---
464	Use the timings of the standard JEDEC DDR3-1066F speed bin for
465	DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
466	for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
467	used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
468	or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
469	that down binning to DDR3-1066F is supported (because DDR3-1066F
470	uses a bit faster timings than DDR3-1333H).
471
472config DRAM_TIMINGS_DDR3_800E_1066G_1333J
473	bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
474	---help---
475	Use the timings of the slowest possible JEDEC speed bin for the
476	selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
477	DDR3-800E, DDR3-1066G or DDR3-1333J.
478
479endchoice
480
481endif
482
483if MACH_SUN8I_A23
484config DRAM_ODT_CORRECTION
485	int "sunxi dram odt correction value"
486	default 0
487	---help---
488	Set the dram odt correction value (range -255 - 255). In allwinner
489	fex files, this option is found in bits 8-15 of the u32 odt_en variable
490	in the [dram] section. When bit 31 of the odt_en variable is set
491	then the correction is negative. Usually the value for this is 0.
492endif
493
494config SYS_CLK_FREQ
495	default 1008000000 if MACH_SUN4I
496	default 1008000000 if MACH_SUN5I
497	default 1008000000 if MACH_SUN6I
498	default 912000000 if MACH_SUN7I
499	default 816000000 if MACH_SUN50I || MACH_SUN50I_H5
500	default 1008000000 if MACH_SUN8I
501	default 1008000000 if MACH_SUN9I
502
503config SYS_CONFIG_NAME
504	default "sun4i" if MACH_SUN4I
505	default "sun5i" if MACH_SUN5I
506	default "sun6i" if MACH_SUN6I
507	default "sun7i" if MACH_SUN7I
508	default "sun8i" if MACH_SUN8I
509	default "sun9i" if MACH_SUN9I
510	default "sun50i" if MACH_SUN50I
511
512config SYS_BOARD
513	default "sunxi"
514
515config SYS_SOC
516	default "sunxi"
517
518config UART0_PORT_F
519	bool "UART0 on MicroSD breakout board"
520	default n
521	---help---
522	Repurpose the SD card slot for getting access to the UART0 serial
523	console. Primarily useful only for low level u-boot debugging on
524	tablets, where normal UART0 is difficult to access and requires
525	device disassembly and/or soldering. As the SD card can't be used
526	at the same time, the system can be only booted in the FEL mode.
527	Only enable this if you really know what you are doing.
528
529config OLD_SUNXI_KERNEL_COMPAT
530	bool "Enable workarounds for booting old kernels"
531	default n
532	---help---
533	Set this to enable various workarounds for old kernels, this results in
534	sub-optimal settings for newer kernels, only enable if needed.
535
536config MACPWR
537	string "MAC power pin"
538	default ""
539	help
540	  Set the pin used to power the MAC. This takes a string in the format
541	  understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
542
543config MMC0_CD_PIN
544	string "Card detect pin for mmc0"
545	default "PF6" if MACH_SUN8I_A83T || MACH_SUNXI_H3_H5 || MACH_SUN50I
546	default ""
547	---help---
548	Set the card detect pin for mmc0, leave empty to not use cd. This
549	takes a string in the format understood by sunxi_name_to_gpio, e.g.
550	PH1 for pin 1 of port H.
551
552config MMC1_CD_PIN
553	string "Card detect pin for mmc1"
554	default ""
555	---help---
556	See MMC0_CD_PIN help text.
557
558config MMC2_CD_PIN
559	string "Card detect pin for mmc2"
560	default ""
561	---help---
562	See MMC0_CD_PIN help text.
563
564config MMC3_CD_PIN
565	string "Card detect pin for mmc3"
566	default ""
567	---help---
568	See MMC0_CD_PIN help text.
569
570config MMC1_PINS
571	string "Pins for mmc1"
572	default ""
573	---help---
574	Set the pins used for mmc1, when applicable. This takes a string in the
575	format understood by sunxi_name_to_gpio_bank, e.g. PH for port H.
576
577config MMC2_PINS
578	string "Pins for mmc2"
579	default ""
580	---help---
581	See MMC1_PINS help text.
582
583config MMC3_PINS
584	string "Pins for mmc3"
585	default ""
586	---help---
587	See MMC1_PINS help text.
588
589config MMC_SUNXI_SLOT_EXTRA
590	int "mmc extra slot number"
591	default -1
592	---help---
593	sunxi builds always enable mmc0, some boards also have a second sdcard
594	slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
595	support for this.
596
597config INITIAL_USB_SCAN_DELAY
598	int "delay initial usb scan by x ms to allow builtin devices to init"
599	default 0
600	---help---
601	Some boards have on board usb devices which need longer than the
602	USB spec's 1 second to connect from board powerup. Set this config
603	option to a non 0 value to add an extra delay before the first usb
604	bus scan.
605
606config USB0_VBUS_PIN
607	string "Vbus enable pin for usb0 (otg)"
608	default ""
609	---help---
610	Set the Vbus enable pin for usb0 (otg). This takes a string in the
611	format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
612
613config USB0_VBUS_DET
614	string "Vbus detect pin for usb0 (otg)"
615	default ""
616	---help---
617	Set the Vbus detect pin for usb0 (otg). This takes a string in the
618	format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
619
620config USB0_ID_DET
621	string "ID detect pin for usb0 (otg)"
622	default ""
623	---help---
624	Set the ID detect pin for usb0 (otg). This takes a string in the
625	format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
626
627config USB1_VBUS_PIN
628	string "Vbus enable pin for usb1 (ehci0)"
629	default "PH6" if MACH_SUN4I || MACH_SUN7I
630	default "PH27" if MACH_SUN6I
631	---help---
632	Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
633	a string in the format understood by sunxi_name_to_gpio, e.g.
634	PH1 for pin 1 of port H.
635
636config USB2_VBUS_PIN
637	string "Vbus enable pin for usb2 (ehci1)"
638	default "PH3" if MACH_SUN4I || MACH_SUN7I
639	default "PH24" if MACH_SUN6I
640	---help---
641	See USB1_VBUS_PIN help text.
642
643config USB3_VBUS_PIN
644	string "Vbus enable pin for usb3 (ehci2)"
645	default ""
646	---help---
647	See USB1_VBUS_PIN help text.
648
649config I2C0_ENABLE
650	bool "Enable I2C/TWI controller 0"
651	default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_R40
652	default n if MACH_SUN6I || MACH_SUN8I
653	select CMD_I2C
654	---help---
655	This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
656	its clock and setting up the bus. This is especially useful on devices
657	with slaves connected to the bus or with pins exposed through e.g. an
658	expansion port/header.
659
660config I2C1_ENABLE
661	bool "Enable I2C/TWI controller 1"
662	default n
663	select CMD_I2C
664	---help---
665	See I2C0_ENABLE help text.
666
667config I2C2_ENABLE
668	bool "Enable I2C/TWI controller 2"
669	default n
670	select CMD_I2C
671	---help---
672	See I2C0_ENABLE help text.
673
674if MACH_SUN6I || MACH_SUN7I
675config I2C3_ENABLE
676	bool "Enable I2C/TWI controller 3"
677	default n
678	select CMD_I2C
679	---help---
680	See I2C0_ENABLE help text.
681endif
682
683if SUNXI_GEN_SUN6I
684config R_I2C_ENABLE
685	bool "Enable the PRCM I2C/TWI controller"
686	# This is used for the pmic on H3
687	default y if SY8106A_POWER
688	select CMD_I2C
689	---help---
690	Set this to y to enable the I2C controller which is part of the PRCM.
691endif
692
693if MACH_SUN7I
694config I2C4_ENABLE
695	bool "Enable I2C/TWI controller 4"
696	default n
697	select CMD_I2C
698	---help---
699	See I2C0_ENABLE help text.
700endif
701
702config AXP_GPIO
703	bool "Enable support for gpio-s on axp PMICs"
704	default n
705	---help---
706	Say Y here to enable support for the gpio pins of the axp PMIC ICs.
707
708config VIDEO_SUNXI
709	bool "Enable graphical uboot console on HDMI, LCD or VGA"
710	depends on !MACH_SUN8I_A83T
711	depends on !MACH_SUNXI_H3_H5
712	depends on !MACH_SUN8I_R40
713	depends on !MACH_SUN8I_V3S
714	depends on !MACH_SUN9I
715	depends on !MACH_SUN50I
716	select VIDEO
717	imply VIDEO_DT_SIMPLEFB
718	default y
719	---help---
720	Say Y here to add support for using a cfb console on the HDMI, LCD
721	or VGA output found on most sunxi devices. See doc/README.video for
722	info on how to select the video output and mode.
723
724config VIDEO_HDMI
725	bool "HDMI output support"
726	depends on VIDEO_SUNXI && !MACH_SUN8I
727	default y
728	---help---
729	Say Y here to add support for outputting video over HDMI.
730
731config VIDEO_VGA
732	bool "VGA output support"
733	depends on VIDEO_SUNXI && (MACH_SUN4I || MACH_SUN7I)
734	default n
735	---help---
736	Say Y here to add support for outputting video over VGA.
737
738config VIDEO_VGA_VIA_LCD
739	bool "VGA via LCD controller support"
740	depends on VIDEO_SUNXI && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
741	default n
742	---help---
743	Say Y here to add support for external DACs connected to the parallel
744	LCD interface driving a VGA connector, such as found on the
745	Olimex A13 boards.
746
747config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
748	bool "Force sync active high for VGA via LCD controller support"
749	depends on VIDEO_VGA_VIA_LCD
750	default n
751	---help---
752	Say Y here if you've a board which uses opendrain drivers for the vga
753	hsync and vsync signals. Opendrain drivers cannot generate steep enough
754	positive edges for a stable video output, so on boards with opendrain
755	drivers the sync signals must always be active high.
756
757config VIDEO_VGA_EXTERNAL_DAC_EN
758	string "LCD panel power enable pin"
759	depends on VIDEO_VGA_VIA_LCD
760	default ""
761	---help---
762	Set the enable pin for the external VGA DAC. This takes a string in the
763	format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
764
765config VIDEO_COMPOSITE
766	bool "Composite video output support"
767	depends on VIDEO_SUNXI && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
768	default n
769	---help---
770	Say Y here to add support for outputting composite video.
771
772config VIDEO_LCD_MODE
773	string "LCD panel timing details"
774	depends on VIDEO_SUNXI
775	default ""
776	---help---
777	LCD panel timing details string, leave empty if there is no LCD panel.
778	This is in drivers/video/videomodes.c: video_get_params() format, e.g.
779	x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
780	Also see: http://linux-sunxi.org/LCD
781
782config VIDEO_LCD_DCLK_PHASE
783	int "LCD panel display clock phase"
784	depends on VIDEO_SUNXI || DM_VIDEO
785	default 1
786	---help---
787	Select LCD panel display clock phase shift, range 0-3.
788
789config VIDEO_LCD_POWER
790	string "LCD panel power enable pin"
791	depends on VIDEO_SUNXI
792	default ""
793	---help---
794	Set the power enable pin for the LCD panel. This takes a string in the
795	format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
796
797config VIDEO_LCD_RESET
798	string "LCD panel reset pin"
799	depends on VIDEO_SUNXI
800	default ""
801	---help---
802	Set the reset pin for the LCD panel. This takes a string in the format
803	understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
804
805config VIDEO_LCD_BL_EN
806	string "LCD panel backlight enable pin"
807	depends on VIDEO_SUNXI
808	default ""
809	---help---
810	Set the backlight enable pin for the LCD panel. This takes a string in the
811	the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
812	port H.
813
814config VIDEO_LCD_BL_PWM
815	string "LCD panel backlight pwm pin"
816	depends on VIDEO_SUNXI
817	default ""
818	---help---
819	Set the backlight pwm pin for the LCD panel. This takes a string in the
820	format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
821
822config VIDEO_LCD_BL_PWM_ACTIVE_LOW
823	bool "LCD panel backlight pwm is inverted"
824	depends on VIDEO_SUNXI
825	default y
826	---help---
827	Set this if the backlight pwm output is active low.
828
829config VIDEO_LCD_PANEL_I2C
830	bool "LCD panel needs to be configured via i2c"
831	depends on VIDEO_SUNXI
832	default n
833	select CMD_I2C
834	---help---
835	Say y here if the LCD panel needs to be configured via i2c. This
836	will add a bitbang i2c controller using gpios to talk to the LCD.
837
838config VIDEO_LCD_PANEL_I2C_SDA
839	string "LCD panel i2c interface SDA pin"
840	depends on VIDEO_LCD_PANEL_I2C
841	default "PG12"
842	---help---
843	Set the SDA pin for the LCD i2c interface. This takes a string in the
844	format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
845
846config VIDEO_LCD_PANEL_I2C_SCL
847	string "LCD panel i2c interface SCL pin"
848	depends on VIDEO_LCD_PANEL_I2C
849	default "PG10"
850	---help---
851	Set the SCL pin for the LCD i2c interface. This takes a string in the
852	format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
853
854
855# Note only one of these may be selected at a time! But hidden choices are
856# not supported by Kconfig
857config VIDEO_LCD_IF_PARALLEL
858	bool
859
860config VIDEO_LCD_IF_LVDS
861	bool
862
863config SUNXI_DE2
864	bool
865	default n
866
867config VIDEO_DE2
868	bool "Display Engine 2 video driver"
869	depends on SUNXI_DE2
870	select DM_VIDEO
871	select DISPLAY
872	imply VIDEO_DT_SIMPLEFB
873	default y
874	---help---
875	Say y here if you want to build DE2 video driver which is present on
876	newer SoCs. Currently only HDMI output is supported.
877
878
879choice
880	prompt "LCD panel support"
881	depends on VIDEO_SUNXI
882	---help---
883	Select which type of LCD panel to support.
884
885config VIDEO_LCD_PANEL_PARALLEL
886	bool "Generic parallel interface LCD panel"
887	select VIDEO_LCD_IF_PARALLEL
888
889config VIDEO_LCD_PANEL_LVDS
890	bool "Generic lvds interface LCD panel"
891	select VIDEO_LCD_IF_LVDS
892
893config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
894	bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
895	select VIDEO_LCD_SSD2828
896	select VIDEO_LCD_IF_PARALLEL
897	---help---
898	7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
899
900config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
901	bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip"
902	select VIDEO_LCD_ANX9804
903	select VIDEO_LCD_IF_PARALLEL
904	select VIDEO_LCD_PANEL_I2C
905	---help---
906	Select this for eDP LCD panels with 4 lanes running at 1.62G,
907	connected via an ANX9804 bridge chip.
908
909config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
910	bool "Hitachi tx18d42vm LCD panel"
911	select VIDEO_LCD_HITACHI_TX18D42VM
912	select VIDEO_LCD_IF_LVDS
913	---help---
914	7.85" 1024x768 Hitachi tx18d42vm LCD panel support
915
916config VIDEO_LCD_TL059WV5C0
917	bool "tl059wv5c0 LCD panel"
918	select VIDEO_LCD_PANEL_I2C
919	select VIDEO_LCD_IF_PARALLEL
920	---help---
921	6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and
922	Aigo M60/M608/M606 tablets.
923
924endchoice
925
926config SATAPWR
927	string "SATA power pin"
928	default ""
929	help
930	  Set the pins used to power the SATA. This takes a string in the
931	  format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
932	  port H.
933
934config GMAC_TX_DELAY
935	int "GMAC Transmit Clock Delay Chain"
936	default 0
937	---help---
938	Set the GMAC Transmit Clock Delay Chain value.
939
940config SPL_STACK_R_ADDR
941	default 0x4fe00000 if MACH_SUN4I
942	default 0x4fe00000 if MACH_SUN5I
943	default 0x4fe00000 if MACH_SUN6I
944	default 0x4fe00000 if MACH_SUN7I
945	default 0x4fe00000 if MACH_SUN8I
946	default 0x2fe00000 if MACH_SUN9I
947	default 0x4fe00000 if MACH_SUN50I
948
949config SPL_SPI_SUNXI
950	bool "Support for SPI Flash on Allwinner SoCs in SPL"
951	depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I
952	help
953	  Enable support for SPI Flash. This option allows SPL to read from
954	  sunxi SPI Flash. It uses the same method as the boot ROM, so does
955	  not need any extra configuration.
956
957endif
958