1if ARCH_SUNXI 2 3config IDENT_STRING 4 default " Allwinner Technology" 5 6config SUNXI_HIGH_SRAM 7 bool 8 default n 9 ---help--- 10 Older Allwinner SoCs have their mask boot ROM mapped just below 4GB, 11 with the first SRAM region being located at address 0. 12 Some newer SoCs map the boot ROM at address 0 instead and move the 13 SRAM to 64KB, just behind the mask ROM. 14 Chips using the latter setup are supposed to select this option to 15 adjust the addresses accordingly. 16 17# Note only one of these may be selected at a time! But hidden choices are 18# not supported by Kconfig 19config SUNXI_GEN_SUN4I 20 bool 21 ---help--- 22 Select this for sunxi SoCs which have resets and clocks set up 23 as the original A10 (mach-sun4i). 24 25config SUNXI_GEN_SUN6I 26 bool 27 ---help--- 28 Select this for sunxi SoCs which have sun6i like periphery, like 29 separate ahb reset control registers, custom pmic bus, new style 30 watchdog, etc. 31 32config SUNXI_DRAM_DW 33 bool 34 ---help--- 35 Select this for sunxi SoCs which uses a DRAM controller like the 36 DesignWare controller used in H3, mainly SoCs after H3, which do 37 not have official open-source DRAM initialization code, but can 38 use modified H3 DRAM initialization code. 39 40if SUNXI_DRAM_DW 41config SUNXI_DRAM_DW_16BIT 42 bool 43 ---help--- 44 Select this for sunxi SoCs with DesignWare DRAM controller and 45 have only 16-bit memory buswidth. 46 47config SUNXI_DRAM_DW_32BIT 48 bool 49 ---help--- 50 Select this for sunxi SoCs with DesignWare DRAM controller with 51 32-bit memory buswidth. 52endif 53 54config MACH_SUNXI_H3_H5 55 bool 56 select DM_I2C 57 select SUNXI_DE2 58 select SUNXI_DRAM_DW 59 select SUNXI_DRAM_DW_32BIT 60 select SUNXI_GEN_SUN6I 61 select SUPPORT_SPL 62 63choice 64 prompt "Sunxi SoC Variant" 65 optional 66 67config MACH_SUN4I 68 bool "sun4i (Allwinner A10)" 69 select CPU_V7 70 select ARM_CORTEX_CPU_IS_UP 71 select SUNXI_GEN_SUN4I 72 select SUPPORT_SPL 73 74config MACH_SUN5I 75 bool "sun5i (Allwinner A13)" 76 select CPU_V7 77 select ARM_CORTEX_CPU_IS_UP 78 select SUNXI_GEN_SUN4I 79 select SUPPORT_SPL 80 81config MACH_SUN6I 82 bool "sun6i (Allwinner A31)" 83 select CPU_V7 84 select CPU_V7_HAS_NONSEC 85 select CPU_V7_HAS_VIRT 86 select ARCH_SUPPORT_PSCI 87 select SUNXI_GEN_SUN6I 88 select SUPPORT_SPL 89 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT 90 91config MACH_SUN7I 92 bool "sun7i (Allwinner A20)" 93 select CPU_V7 94 select CPU_V7_HAS_NONSEC 95 select CPU_V7_HAS_VIRT 96 select ARCH_SUPPORT_PSCI 97 select SUNXI_GEN_SUN4I 98 select SUPPORT_SPL 99 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT 100 101config MACH_SUN8I_A23 102 bool "sun8i (Allwinner A23)" 103 select CPU_V7 104 select CPU_V7_HAS_NONSEC 105 select CPU_V7_HAS_VIRT 106 select ARCH_SUPPORT_PSCI 107 select SUNXI_GEN_SUN6I 108 select SUPPORT_SPL 109 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT 110 111config MACH_SUN8I_A33 112 bool "sun8i (Allwinner A33)" 113 select CPU_V7 114 select CPU_V7_HAS_NONSEC 115 select CPU_V7_HAS_VIRT 116 select ARCH_SUPPORT_PSCI 117 select SUNXI_GEN_SUN6I 118 select SUPPORT_SPL 119 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT 120 121config MACH_SUN8I_A83T 122 bool "sun8i (Allwinner A83T)" 123 select CPU_V7 124 select SUNXI_GEN_SUN6I 125 select SUPPORT_SPL 126 127config MACH_SUN8I_H3 128 bool "sun8i (Allwinner H3)" 129 select CPU_V7 130 select CPU_V7_HAS_NONSEC 131 select CPU_V7_HAS_VIRT 132 select ARCH_SUPPORT_PSCI 133 select MACH_SUNXI_H3_H5 134 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT 135 136config MACH_SUN8I_R40 137 bool "sun8i (Allwinner R40)" 138 select CPU_V7 139 select CPU_V7_HAS_NONSEC 140 select CPU_V7_HAS_VIRT 141 select ARCH_SUPPORT_PSCI 142 select SUNXI_GEN_SUN6I 143 select SUPPORT_SPL 144 select SUNXI_DRAM_DW 145 select SUNXI_DRAM_DW_32BIT 146 147config MACH_SUN8I_V3S 148 bool "sun8i (Allwinner V3s)" 149 select CPU_V7 150 select CPU_V7_HAS_NONSEC 151 select CPU_V7_HAS_VIRT 152 select ARCH_SUPPORT_PSCI 153 select SUNXI_GEN_SUN6I 154 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT 155 156config MACH_SUN9I 157 bool "sun9i (Allwinner A80)" 158 select CPU_V7 159 select SUNXI_HIGH_SRAM 160 select SUNXI_GEN_SUN6I 161 select SUPPORT_SPL 162 163config MACH_SUN50I 164 bool "sun50i (Allwinner A64)" 165 select ARM64 166 select DM_I2C 167 select SUNXI_DE2 168 select SUNXI_GEN_SUN6I 169 select SUNXI_HIGH_SRAM 170 select SUPPORT_SPL 171 select SUNXI_DRAM_DW 172 select SUNXI_DRAM_DW_32BIT 173 select FIT 174 select SPL_LOAD_FIT 175 176config MACH_SUN50I_H5 177 bool "sun50i (Allwinner H5)" 178 select ARM64 179 select MACH_SUNXI_H3_H5 180 select SUNXI_HIGH_SRAM 181 select FIT 182 select SPL_LOAD_FIT 183 184endchoice 185 186# The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33" 187config MACH_SUN8I 188 bool 189 default y if MACH_SUN8I_A23 190 default y if MACH_SUN8I_A33 191 default y if MACH_SUN8I_A83T 192 default y if MACH_SUNXI_H3_H5 193 default y if MACH_SUN8I_R40 194 default y if MACH_SUN8I_V3S 195 196config RESERVE_ALLWINNER_BOOT0_HEADER 197 bool "reserve space for Allwinner boot0 header" 198 select ENABLE_ARM_SOC_BOOT0_HOOK 199 ---help--- 200 Prepend a 1536 byte (empty) header to the U-Boot image file, to be 201 filled with magic values post build. The Allwinner provided boot0 202 blob relies on this information to load and execute U-Boot. 203 Only needed on 64-bit Allwinner boards so far when using boot0. 204 205config ARM_BOOT_HOOK_RMR 206 bool 207 depends on ARM64 208 default y 209 select ENABLE_ARM_SOC_BOOT0_HOOK 210 ---help--- 211 Insert some ARM32 code at the very beginning of the U-Boot binary 212 which uses an RMR register write to bring the core into AArch64 mode. 213 The very first instruction acts as a switch, since it's carefully 214 chosen to be a NOP in one mode and a branch in the other, so the 215 code would only be executed if not already in AArch64. 216 This allows both the SPL and the U-Boot proper to be entered in 217 either mode and switch to AArch64 if needed. 218 219if SUNXI_DRAM_DW 220config SUNXI_DRAM_DDR3 221 bool 222 223config SUNXI_DRAM_DDR2 224 bool 225 226choice 227 prompt "DRAM Type and Timing" 228 default SUNXI_DRAM_DDR3_1333 if !MACH_SUN8I_V3S 229 default SUNXI_DRAM_DDR2_V3S if MACH_SUN8I_V3S 230 231config SUNXI_DRAM_DDR3_1333 232 bool "DDR3 1333" 233 select SUNXI_DRAM_DDR3 234 depends on !MACH_SUN8I_V3S 235 ---help--- 236 This option is the original only supported memory type, which suits 237 many H3/H5/A64 boards available now. 238 239config SUNXI_DRAM_DDR2_V3S 240 bool "DDR2 found in V3s chip" 241 select SUNXI_DRAM_DDR2 242 depends on MACH_SUN8I_V3S 243 ---help--- 244 This option is only for the DDR2 memory chip which is co-packaged in 245 Allwinner V3s SoC. 246 247endchoice 248endif 249 250config DRAM_TYPE 251 int "sunxi dram type" 252 depends on MACH_SUN8I_A83T 253 default 3 254 ---help--- 255 Set the dram type, 3: DDR3, 7: LPDDR3 256 257config DRAM_CLK 258 int "sunxi dram clock speed" 259 default 792 if MACH_SUN9I 260 default 648 if MACH_SUN8I_R40 261 default 312 if MACH_SUN6I || MACH_SUN8I 262 default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I 263 default 672 if MACH_SUN50I 264 ---help--- 265 Set the dram clock speed, valid range 240 - 480 (prior to sun9i), 266 must be a multiple of 24. For the sun9i (A80), the tested values 267 (for DDR3-1600) are 312 to 792. 268 269if MACH_SUN5I || MACH_SUN7I 270config DRAM_MBUS_CLK 271 int "sunxi mbus clock speed" 272 default 300 273 ---help--- 274 Set the mbus clock speed. The maximum on sun5i hardware is 300MHz. 275 276endif 277 278config DRAM_ZQ 279 int "sunxi dram zq value" 280 default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I 281 default 127 if MACH_SUN7I 282 default 3881979 if MACH_SUN8I_R40 283 default 4145117 if MACH_SUN9I 284 default 3881915 if MACH_SUN50I 285 ---help--- 286 Set the dram zq value. 287 288config DRAM_ODT_EN 289 bool "sunxi dram odt enable" 290 default n if !MACH_SUN8I_A23 291 default y if MACH_SUN8I_A23 292 default y if MACH_SUN8I_R40 293 default y if MACH_SUN50I 294 ---help--- 295 Select this to enable dram odt (on die termination). 296 297if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I 298config DRAM_EMR1 299 int "sunxi dram emr1 value" 300 default 0 if MACH_SUN4I 301 default 4 if MACH_SUN5I || MACH_SUN7I 302 ---help--- 303 Set the dram controller emr1 value. 304 305config DRAM_TPR3 306 hex "sunxi dram tpr3 value" 307 default 0 308 ---help--- 309 Set the dram controller tpr3 parameter. This parameter configures 310 the delay on the command lane and also phase shifts, which are 311 applied for sampling incoming read data. The default value 0 312 means that no phase/delay adjustments are necessary. Properly 313 configuring this parameter increases reliability at high DRAM 314 clock speeds. 315 316config DRAM_DQS_GATING_DELAY 317 hex "sunxi dram dqs_gating_delay value" 318 default 0 319 ---help--- 320 Set the dram controller dqs_gating_delay parmeter. Each byte 321 encodes the DQS gating delay for each byte lane. The delay 322 granularity is 1/4 cycle. For example, the value 0x05060606 323 means that the delay is 5 quarter-cycles for one lane (1.25 324 cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes. 325 The default value 0 means autodetection. The results of hardware 326 autodetection are not very reliable and depend on the chip 327 temperature (sometimes producing different results on cold start 328 and warm reboot). But the accuracy of hardware autodetection 329 is usually good enough, unless running at really high DRAM 330 clocks speeds (up to 600MHz). If unsure, keep as 0. 331 332choice 333 prompt "sunxi dram timings" 334 default DRAM_TIMINGS_VENDOR_MAGIC 335 ---help--- 336 Select the timings of the DDR3 chips. 337 338config DRAM_TIMINGS_VENDOR_MAGIC 339 bool "Magic vendor timings from Android" 340 ---help--- 341 The same DRAM timings as in the Allwinner boot0 bootloader. 342 343config DRAM_TIMINGS_DDR3_1066F_1333H 344 bool "JEDEC DDR3-1333H with down binning to DDR3-1066F" 345 ---help--- 346 Use the timings of the standard JEDEC DDR3-1066F speed bin for 347 DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin 348 for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips 349 used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333 350 or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm 351 that down binning to DDR3-1066F is supported (because DDR3-1066F 352 uses a bit faster timings than DDR3-1333H). 353 354config DRAM_TIMINGS_DDR3_800E_1066G_1333J 355 bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J" 356 ---help--- 357 Use the timings of the slowest possible JEDEC speed bin for the 358 selected DRAM_CLK. Depending on the DRAM_CLK value, it may be 359 DDR3-800E, DDR3-1066G or DDR3-1333J. 360 361endchoice 362 363endif 364 365if MACH_SUN8I_A23 366config DRAM_ODT_CORRECTION 367 int "sunxi dram odt correction value" 368 default 0 369 ---help--- 370 Set the dram odt correction value (range -255 - 255). In allwinner 371 fex files, this option is found in bits 8-15 of the u32 odt_en variable 372 in the [dram] section. When bit 31 of the odt_en variable is set 373 then the correction is negative. Usually the value for this is 0. 374endif 375 376config SYS_CLK_FREQ 377 default 1008000000 if MACH_SUN4I 378 default 1008000000 if MACH_SUN5I 379 default 1008000000 if MACH_SUN6I 380 default 912000000 if MACH_SUN7I 381 default 1008000000 if MACH_SUN8I 382 default 1008000000 if MACH_SUN9I 383 default 816000000 if MACH_SUN50I 384 385config SYS_CONFIG_NAME 386 default "sun4i" if MACH_SUN4I 387 default "sun5i" if MACH_SUN5I 388 default "sun6i" if MACH_SUN6I 389 default "sun7i" if MACH_SUN7I 390 default "sun8i" if MACH_SUN8I 391 default "sun9i" if MACH_SUN9I 392 default "sun50i" if MACH_SUN50I 393 394config SYS_BOARD 395 default "sunxi" 396 397config SYS_SOC 398 default "sunxi" 399 400config UART0_PORT_F 401 bool "UART0 on MicroSD breakout board" 402 default n 403 ---help--- 404 Repurpose the SD card slot for getting access to the UART0 serial 405 console. Primarily useful only for low level u-boot debugging on 406 tablets, where normal UART0 is difficult to access and requires 407 device disassembly and/or soldering. As the SD card can't be used 408 at the same time, the system can be only booted in the FEL mode. 409 Only enable this if you really know what you are doing. 410 411config OLD_SUNXI_KERNEL_COMPAT 412 bool "Enable workarounds for booting old kernels" 413 default n 414 ---help--- 415 Set this to enable various workarounds for old kernels, this results in 416 sub-optimal settings for newer kernels, only enable if needed. 417 418config MACPWR 419 string "MAC power pin" 420 default "" 421 help 422 Set the pin used to power the MAC. This takes a string in the format 423 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. 424 425config MMC0_CD_PIN 426 string "Card detect pin for mmc0" 427 default "PF6" if MACH_SUN8I_A83T || MACH_SUNXI_H3_H5 || MACH_SUN50I 428 default "" 429 ---help--- 430 Set the card detect pin for mmc0, leave empty to not use cd. This 431 takes a string in the format understood by sunxi_name_to_gpio, e.g. 432 PH1 for pin 1 of port H. 433 434config MMC1_CD_PIN 435 string "Card detect pin for mmc1" 436 default "" 437 ---help--- 438 See MMC0_CD_PIN help text. 439 440config MMC2_CD_PIN 441 string "Card detect pin for mmc2" 442 default "" 443 ---help--- 444 See MMC0_CD_PIN help text. 445 446config MMC3_CD_PIN 447 string "Card detect pin for mmc3" 448 default "" 449 ---help--- 450 See MMC0_CD_PIN help text. 451 452config MMC1_PINS 453 string "Pins for mmc1" 454 default "" 455 ---help--- 456 Set the pins used for mmc1, when applicable. This takes a string in the 457 format understood by sunxi_name_to_gpio_bank, e.g. PH for port H. 458 459config MMC2_PINS 460 string "Pins for mmc2" 461 default "" 462 ---help--- 463 See MMC1_PINS help text. 464 465config MMC3_PINS 466 string "Pins for mmc3" 467 default "" 468 ---help--- 469 See MMC1_PINS help text. 470 471config MMC_SUNXI_SLOT_EXTRA 472 int "mmc extra slot number" 473 default -1 474 ---help--- 475 sunxi builds always enable mmc0, some boards also have a second sdcard 476 slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable 477 support for this. 478 479config INITIAL_USB_SCAN_DELAY 480 int "delay initial usb scan by x ms to allow builtin devices to init" 481 default 0 482 ---help--- 483 Some boards have on board usb devices which need longer than the 484 USB spec's 1 second to connect from board powerup. Set this config 485 option to a non 0 value to add an extra delay before the first usb 486 bus scan. 487 488config USB0_VBUS_PIN 489 string "Vbus enable pin for usb0 (otg)" 490 default "" 491 ---help--- 492 Set the Vbus enable pin for usb0 (otg). This takes a string in the 493 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. 494 495config USB0_VBUS_DET 496 string "Vbus detect pin for usb0 (otg)" 497 default "" 498 ---help--- 499 Set the Vbus detect pin for usb0 (otg). This takes a string in the 500 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. 501 502config USB0_ID_DET 503 string "ID detect pin for usb0 (otg)" 504 default "" 505 ---help--- 506 Set the ID detect pin for usb0 (otg). This takes a string in the 507 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. 508 509config USB1_VBUS_PIN 510 string "Vbus enable pin for usb1 (ehci0)" 511 default "PH6" if MACH_SUN4I || MACH_SUN7I 512 default "PH27" if MACH_SUN6I 513 ---help--- 514 Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes 515 a string in the format understood by sunxi_name_to_gpio, e.g. 516 PH1 for pin 1 of port H. 517 518config USB2_VBUS_PIN 519 string "Vbus enable pin for usb2 (ehci1)" 520 default "PH3" if MACH_SUN4I || MACH_SUN7I 521 default "PH24" if MACH_SUN6I 522 ---help--- 523 See USB1_VBUS_PIN help text. 524 525config USB3_VBUS_PIN 526 string "Vbus enable pin for usb3 (ehci2)" 527 default "" 528 ---help--- 529 See USB1_VBUS_PIN help text. 530 531config I2C0_ENABLE 532 bool "Enable I2C/TWI controller 0" 533 default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_R40 534 default n if MACH_SUN6I || MACH_SUN8I 535 select CMD_I2C 536 ---help--- 537 This allows enabling I2C/TWI controller 0 by muxing its pins, enabling 538 its clock and setting up the bus. This is especially useful on devices 539 with slaves connected to the bus or with pins exposed through e.g. an 540 expansion port/header. 541 542config I2C1_ENABLE 543 bool "Enable I2C/TWI controller 1" 544 default n 545 select CMD_I2C 546 ---help--- 547 See I2C0_ENABLE help text. 548 549config I2C2_ENABLE 550 bool "Enable I2C/TWI controller 2" 551 default n 552 select CMD_I2C 553 ---help--- 554 See I2C0_ENABLE help text. 555 556if MACH_SUN6I || MACH_SUN7I 557config I2C3_ENABLE 558 bool "Enable I2C/TWI controller 3" 559 default n 560 select CMD_I2C 561 ---help--- 562 See I2C0_ENABLE help text. 563endif 564 565if SUNXI_GEN_SUN6I 566config R_I2C_ENABLE 567 bool "Enable the PRCM I2C/TWI controller" 568 # This is used for the pmic on H3 569 default y if SY8106A_POWER 570 select CMD_I2C 571 ---help--- 572 Set this to y to enable the I2C controller which is part of the PRCM. 573endif 574 575if MACH_SUN7I 576config I2C4_ENABLE 577 bool "Enable I2C/TWI controller 4" 578 default n 579 select CMD_I2C 580 ---help--- 581 See I2C0_ENABLE help text. 582endif 583 584config AXP_GPIO 585 bool "Enable support for gpio-s on axp PMICs" 586 default n 587 ---help--- 588 Say Y here to enable support for the gpio pins of the axp PMIC ICs. 589 590config VIDEO 591 bool "Enable graphical uboot console on HDMI, LCD or VGA" 592 depends on !MACH_SUN8I_A83T 593 depends on !MACH_SUNXI_H3_H5 594 depends on !MACH_SUN8I_R40 595 depends on !MACH_SUN8I_V3S 596 depends on !MACH_SUN9I 597 depends on !MACH_SUN50I 598 default y 599 ---help--- 600 Say Y here to add support for using a cfb console on the HDMI, LCD 601 or VGA output found on most sunxi devices. See doc/README.video for 602 info on how to select the video output and mode. 603 604config VIDEO_HDMI 605 bool "HDMI output support" 606 depends on VIDEO && !MACH_SUN8I 607 default y 608 ---help--- 609 Say Y here to add support for outputting video over HDMI. 610 611config VIDEO_VGA 612 bool "VGA output support" 613 depends on VIDEO && (MACH_SUN4I || MACH_SUN7I) 614 default n 615 ---help--- 616 Say Y here to add support for outputting video over VGA. 617 618config VIDEO_VGA_VIA_LCD 619 bool "VGA via LCD controller support" 620 depends on VIDEO && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I) 621 default n 622 ---help--- 623 Say Y here to add support for external DACs connected to the parallel 624 LCD interface driving a VGA connector, such as found on the 625 Olimex A13 boards. 626 627config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH 628 bool "Force sync active high for VGA via LCD controller support" 629 depends on VIDEO_VGA_VIA_LCD 630 default n 631 ---help--- 632 Say Y here if you've a board which uses opendrain drivers for the vga 633 hsync and vsync signals. Opendrain drivers cannot generate steep enough 634 positive edges for a stable video output, so on boards with opendrain 635 drivers the sync signals must always be active high. 636 637config VIDEO_VGA_EXTERNAL_DAC_EN 638 string "LCD panel power enable pin" 639 depends on VIDEO_VGA_VIA_LCD 640 default "" 641 ---help--- 642 Set the enable pin for the external VGA DAC. This takes a string in the 643 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. 644 645config VIDEO_COMPOSITE 646 bool "Composite video output support" 647 depends on VIDEO && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I) 648 default n 649 ---help--- 650 Say Y here to add support for outputting composite video. 651 652config VIDEO_LCD_MODE 653 string "LCD panel timing details" 654 depends on VIDEO 655 default "" 656 ---help--- 657 LCD panel timing details string, leave empty if there is no LCD panel. 658 This is in drivers/video/videomodes.c: video_get_params() format, e.g. 659 x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0 660 Also see: http://linux-sunxi.org/LCD 661 662config VIDEO_LCD_DCLK_PHASE 663 int "LCD panel display clock phase" 664 depends on VIDEO 665 default 1 666 ---help--- 667 Select LCD panel display clock phase shift, range 0-3. 668 669config VIDEO_LCD_POWER 670 string "LCD panel power enable pin" 671 depends on VIDEO 672 default "" 673 ---help--- 674 Set the power enable pin for the LCD panel. This takes a string in the 675 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. 676 677config VIDEO_LCD_RESET 678 string "LCD panel reset pin" 679 depends on VIDEO 680 default "" 681 ---help--- 682 Set the reset pin for the LCD panel. This takes a string in the format 683 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. 684 685config VIDEO_LCD_BL_EN 686 string "LCD panel backlight enable pin" 687 depends on VIDEO 688 default "" 689 ---help--- 690 Set the backlight enable pin for the LCD panel. This takes a string in the 691 the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of 692 port H. 693 694config VIDEO_LCD_BL_PWM 695 string "LCD panel backlight pwm pin" 696 depends on VIDEO 697 default "" 698 ---help--- 699 Set the backlight pwm pin for the LCD panel. This takes a string in the 700 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. 701 702config VIDEO_LCD_BL_PWM_ACTIVE_LOW 703 bool "LCD panel backlight pwm is inverted" 704 depends on VIDEO 705 default y 706 ---help--- 707 Set this if the backlight pwm output is active low. 708 709config VIDEO_LCD_PANEL_I2C 710 bool "LCD panel needs to be configured via i2c" 711 depends on VIDEO 712 default n 713 select CMD_I2C 714 ---help--- 715 Say y here if the LCD panel needs to be configured via i2c. This 716 will add a bitbang i2c controller using gpios to talk to the LCD. 717 718config VIDEO_LCD_PANEL_I2C_SDA 719 string "LCD panel i2c interface SDA pin" 720 depends on VIDEO_LCD_PANEL_I2C 721 default "PG12" 722 ---help--- 723 Set the SDA pin for the LCD i2c interface. This takes a string in the 724 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. 725 726config VIDEO_LCD_PANEL_I2C_SCL 727 string "LCD panel i2c interface SCL pin" 728 depends on VIDEO_LCD_PANEL_I2C 729 default "PG10" 730 ---help--- 731 Set the SCL pin for the LCD i2c interface. This takes a string in the 732 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. 733 734 735# Note only one of these may be selected at a time! But hidden choices are 736# not supported by Kconfig 737config VIDEO_LCD_IF_PARALLEL 738 bool 739 740config VIDEO_LCD_IF_LVDS 741 bool 742 743config SUNXI_DE2 744 bool 745 default n 746 747config VIDEO_DE2 748 bool "Display Engine 2 video driver" 749 depends on SUNXI_DE2 750 select DM_VIDEO 751 select DISPLAY 752 default y 753 ---help--- 754 Say y here if you want to build DE2 video driver which is present on 755 newer SoCs. Currently only HDMI output is supported. 756 757 758choice 759 prompt "LCD panel support" 760 depends on VIDEO 761 ---help--- 762 Select which type of LCD panel to support. 763 764config VIDEO_LCD_PANEL_PARALLEL 765 bool "Generic parallel interface LCD panel" 766 select VIDEO_LCD_IF_PARALLEL 767 768config VIDEO_LCD_PANEL_LVDS 769 bool "Generic lvds interface LCD panel" 770 select VIDEO_LCD_IF_LVDS 771 772config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828 773 bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip" 774 select VIDEO_LCD_SSD2828 775 select VIDEO_LCD_IF_PARALLEL 776 ---help--- 777 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0 778 779config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804 780 bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip" 781 select VIDEO_LCD_ANX9804 782 select VIDEO_LCD_IF_PARALLEL 783 select VIDEO_LCD_PANEL_I2C 784 ---help--- 785 Select this for eDP LCD panels with 4 lanes running at 1.62G, 786 connected via an ANX9804 bridge chip. 787 788config VIDEO_LCD_PANEL_HITACHI_TX18D42VM 789 bool "Hitachi tx18d42vm LCD panel" 790 select VIDEO_LCD_HITACHI_TX18D42VM 791 select VIDEO_LCD_IF_LVDS 792 ---help--- 793 7.85" 1024x768 Hitachi tx18d42vm LCD panel support 794 795config VIDEO_LCD_TL059WV5C0 796 bool "tl059wv5c0 LCD panel" 797 select VIDEO_LCD_PANEL_I2C 798 select VIDEO_LCD_IF_PARALLEL 799 ---help--- 800 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and 801 Aigo M60/M608/M606 tablets. 802 803endchoice 804 805config SATAPWR 806 string "SATA power pin" 807 default "" 808 help 809 Set the pins used to power the SATA. This takes a string in the 810 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of 811 port H. 812 813config GMAC_TX_DELAY 814 int "GMAC Transmit Clock Delay Chain" 815 default 0 816 ---help--- 817 Set the GMAC Transmit Clock Delay Chain value. 818 819config SPL_STACK_R_ADDR 820 default 0x4fe00000 if MACH_SUN4I 821 default 0x4fe00000 if MACH_SUN5I 822 default 0x4fe00000 if MACH_SUN6I 823 default 0x4fe00000 if MACH_SUN7I 824 default 0x4fe00000 if MACH_SUN8I 825 default 0x2fe00000 if MACH_SUN9I 826 default 0x4fe00000 if MACH_SUN50I 827 828endif 829