xref: /openbmc/u-boot/arch/arm/mach-sunxi/Kconfig (revision 23a06416)
1if ARCH_SUNXI
2
3config SPL_LDSCRIPT
4	default "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" if !ARM64
5
6config IDENT_STRING
7	default " Allwinner Technology"
8
9config SUNXI_HIGH_SRAM
10	bool
11	default n
12	---help---
13	Older Allwinner SoCs have their mask boot ROM mapped just below 4GB,
14	with the first SRAM region being located at address 0.
15	Some newer SoCs map the boot ROM at address 0 instead and move the
16	SRAM to 64KB, just behind the mask ROM.
17	Chips using the latter setup are supposed to select this option to
18	adjust the addresses accordingly.
19
20# Note only one of these may be selected at a time! But hidden choices are
21# not supported by Kconfig
22config SUNXI_GEN_SUN4I
23	bool
24	---help---
25	Select this for sunxi SoCs which have resets and clocks set up
26	as the original A10 (mach-sun4i).
27
28config SUNXI_GEN_SUN6I
29	bool
30	---help---
31	Select this for sunxi SoCs which have sun6i like periphery, like
32	separate ahb reset control registers, custom pmic bus, new style
33	watchdog, etc.
34
35config SUNXI_DRAM_DW
36	bool
37	---help---
38	Select this for sunxi SoCs which uses a DRAM controller like the
39	DesignWare controller used in H3, mainly SoCs after H3, which do
40	not have official open-source DRAM initialization code, but can
41	use modified H3 DRAM initialization code.
42
43if SUNXI_DRAM_DW
44config SUNXI_DRAM_DW_16BIT
45	bool
46	---help---
47	Select this for sunxi SoCs with DesignWare DRAM controller and
48	have only 16-bit memory buswidth.
49
50config SUNXI_DRAM_DW_32BIT
51	bool
52	---help---
53	Select this for sunxi SoCs with DesignWare DRAM controller with
54	32-bit memory buswidth.
55endif
56
57config MACH_SUNXI_H3_H5
58	bool
59	select DM_I2C
60	select SUNXI_DE2
61	select SUNXI_DRAM_DW
62	select SUNXI_DRAM_DW_32BIT
63	select SUNXI_GEN_SUN6I
64	select SUPPORT_SPL
65
66choice
67	prompt "Sunxi SoC Variant"
68	optional
69
70config MACH_SUN4I
71	bool "sun4i (Allwinner A10)"
72	select CPU_V7
73	select ARM_CORTEX_CPU_IS_UP
74	select SUNXI_GEN_SUN4I
75	select SUPPORT_SPL
76
77config MACH_SUN5I
78	bool "sun5i (Allwinner A13)"
79	select CPU_V7
80	select ARM_CORTEX_CPU_IS_UP
81	select SUNXI_GEN_SUN4I
82	select SUPPORT_SPL
83
84config MACH_SUN6I
85	bool "sun6i (Allwinner A31)"
86	select CPU_V7
87	select CPU_V7_HAS_NONSEC
88	select CPU_V7_HAS_VIRT
89	select ARCH_SUPPORT_PSCI
90	select SUNXI_GEN_SUN6I
91	select SUPPORT_SPL
92	select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
93
94config MACH_SUN7I
95	bool "sun7i (Allwinner A20)"
96	select CPU_V7
97	select CPU_V7_HAS_NONSEC
98	select CPU_V7_HAS_VIRT
99	select ARCH_SUPPORT_PSCI
100	select SUNXI_GEN_SUN4I
101	select SUPPORT_SPL
102	select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
103
104config MACH_SUN8I_A23
105	bool "sun8i (Allwinner A23)"
106	select CPU_V7
107	select CPU_V7_HAS_NONSEC
108	select CPU_V7_HAS_VIRT
109	select ARCH_SUPPORT_PSCI
110	select SUNXI_GEN_SUN6I
111	select SUPPORT_SPL
112	select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
113
114config MACH_SUN8I_A33
115	bool "sun8i (Allwinner A33)"
116	select CPU_V7
117	select CPU_V7_HAS_NONSEC
118	select CPU_V7_HAS_VIRT
119	select ARCH_SUPPORT_PSCI
120	select SUNXI_GEN_SUN6I
121	select SUPPORT_SPL
122	select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
123
124config MACH_SUN8I_A83T
125	bool "sun8i (Allwinner A83T)"
126	select CPU_V7
127	select SUNXI_GEN_SUN6I
128	select MMC_SUNXI_HAS_NEW_MODE
129	select SUPPORT_SPL
130
131config MACH_SUN8I_H3
132	bool "sun8i (Allwinner H3)"
133	select CPU_V7
134	select CPU_V7_HAS_NONSEC
135	select CPU_V7_HAS_VIRT
136	select ARCH_SUPPORT_PSCI
137	select MACH_SUNXI_H3_H5
138	select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
139
140config MACH_SUN8I_R40
141	bool "sun8i (Allwinner R40)"
142	select CPU_V7
143	select CPU_V7_HAS_NONSEC
144	select CPU_V7_HAS_VIRT
145	select ARCH_SUPPORT_PSCI
146	select SUNXI_GEN_SUN6I
147	select SUPPORT_SPL
148	select SUNXI_DRAM_DW
149	select SUNXI_DRAM_DW_32BIT
150
151config MACH_SUN8I_V3S
152	bool "sun8i (Allwinner V3s)"
153	select CPU_V7
154	select CPU_V7_HAS_NONSEC
155	select CPU_V7_HAS_VIRT
156	select ARCH_SUPPORT_PSCI
157	select SUNXI_GEN_SUN6I
158	select SUNXI_DRAM_DW
159	select SUNXI_DRAM_DW_16BIT
160	select SUPPORT_SPL
161	select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
162
163config MACH_SUN9I
164	bool "sun9i (Allwinner A80)"
165	select CPU_V7
166	select SUNXI_HIGH_SRAM
167	select SUNXI_GEN_SUN6I
168	select SUPPORT_SPL
169
170config MACH_SUN50I
171	bool "sun50i (Allwinner A64)"
172	select ARM64
173	select DM_I2C
174	select SUNXI_DE2
175	select SUNXI_GEN_SUN6I
176	select SUNXI_HIGH_SRAM
177	select SUPPORT_SPL
178	select SUNXI_DRAM_DW
179	select SUNXI_DRAM_DW_32BIT
180	select FIT
181	select SPL_LOAD_FIT
182
183config MACH_SUN50I_H5
184	bool "sun50i (Allwinner H5)"
185	select ARM64
186	select MACH_SUNXI_H3_H5
187	select SUNXI_HIGH_SRAM
188	select FIT
189	select SPL_LOAD_FIT
190
191endchoice
192
193# The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
194config MACH_SUN8I
195	bool
196	default y if MACH_SUN8I_A23
197	default y if MACH_SUN8I_A33
198	default y if MACH_SUN8I_A83T
199	default y if MACH_SUNXI_H3_H5
200	default y if MACH_SUN8I_R40
201	default y if MACH_SUN8I_V3S
202
203config RESERVE_ALLWINNER_BOOT0_HEADER
204	bool "reserve space for Allwinner boot0 header"
205	select ENABLE_ARM_SOC_BOOT0_HOOK
206	---help---
207	Prepend a 1536 byte (empty) header to the U-Boot image file, to be
208	filled with magic values post build. The Allwinner provided boot0
209	blob relies on this information to load and execute U-Boot.
210	Only needed on 64-bit Allwinner boards so far when using boot0.
211
212config ARM_BOOT_HOOK_RMR
213	bool
214	depends on ARM64
215	default y
216	select ENABLE_ARM_SOC_BOOT0_HOOK
217	---help---
218	Insert some ARM32 code at the very beginning of the U-Boot binary
219	which uses an RMR register write to bring the core into AArch64 mode.
220	The very first instruction acts as a switch, since it's carefully
221	chosen to be a NOP in one mode and a branch in the other, so the
222	code would only be executed if not already in AArch64.
223	This allows both the SPL and the U-Boot proper to be entered in
224	either mode and switch to AArch64 if needed.
225
226if SUNXI_DRAM_DW
227config SUNXI_DRAM_DDR3
228	bool
229
230config SUNXI_DRAM_DDR2
231	bool
232
233config SUNXI_DRAM_LPDDR3
234	bool
235
236choice
237	prompt "DRAM Type and Timing"
238	default SUNXI_DRAM_DDR3_1333 if !MACH_SUN8I_V3S
239	default SUNXI_DRAM_DDR2_V3S if MACH_SUN8I_V3S
240
241config SUNXI_DRAM_DDR3_1333
242	bool "DDR3 1333"
243	select SUNXI_DRAM_DDR3
244	depends on !MACH_SUN8I_V3S
245	---help---
246	This option is the original only supported memory type, which suits
247	many H3/H5/A64 boards available now.
248
249config SUNXI_DRAM_LPDDR3_STOCK
250	bool "LPDDR3 with Allwinner stock configuration"
251	select SUNXI_DRAM_LPDDR3
252	---help---
253	This option is the LPDDR3 timing used by the stock boot0 by
254	Allwinner.
255
256config SUNXI_DRAM_DDR2_V3S
257	bool "DDR2 found in V3s chip"
258	select SUNXI_DRAM_DDR2
259	depends on MACH_SUN8I_V3S
260	---help---
261	This option is only for the DDR2 memory chip which is co-packaged in
262	Allwinner V3s SoC.
263
264endchoice
265endif
266
267config DRAM_TYPE
268	int "sunxi dram type"
269	depends on MACH_SUN8I_A83T
270	default 3
271	---help---
272	Set the dram type, 3: DDR3, 7: LPDDR3
273
274config DRAM_CLK
275	int "sunxi dram clock speed"
276	default 792 if MACH_SUN9I
277	default 648 if MACH_SUN8I_R40
278	default 312 if MACH_SUN6I || MACH_SUN8I
279	default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || \
280		       MACH_SUN8I_V3S
281	default 672 if MACH_SUN50I
282	---help---
283	Set the dram clock speed, valid range 240 - 480 (prior to sun9i),
284	must be a multiple of 24. For the sun9i (A80), the tested values
285	(for DDR3-1600) are 312 to 792.
286
287if MACH_SUN5I || MACH_SUN7I
288config DRAM_MBUS_CLK
289	int "sunxi mbus clock speed"
290	default 300
291	---help---
292	Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
293
294endif
295
296config DRAM_ZQ
297	int "sunxi dram zq value"
298	default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
299	default 127 if MACH_SUN7I
300	default 14779 if MACH_SUN8I_V3S
301	default 3881979 if MACH_SUN8I_R40
302	default 4145117 if MACH_SUN9I
303	default 3881915 if MACH_SUN50I
304	---help---
305	Set the dram zq value.
306
307config DRAM_ODT_EN
308	bool "sunxi dram odt enable"
309	default n if !MACH_SUN8I_A23
310	default y if MACH_SUN8I_A23
311	default y if MACH_SUN8I_R40
312	default y if MACH_SUN50I
313	---help---
314	Select this to enable dram odt (on die termination).
315
316if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
317config DRAM_EMR1
318	int "sunxi dram emr1 value"
319	default 0 if MACH_SUN4I
320	default 4 if MACH_SUN5I || MACH_SUN7I
321	---help---
322	Set the dram controller emr1 value.
323
324config DRAM_TPR3
325	hex "sunxi dram tpr3 value"
326	default 0
327	---help---
328	Set the dram controller tpr3 parameter. This parameter configures
329	the delay on the command lane and also phase shifts, which are
330	applied for sampling incoming read data. The default value 0
331	means that no phase/delay adjustments are necessary. Properly
332	configuring this parameter increases reliability at high DRAM
333	clock speeds.
334
335config DRAM_DQS_GATING_DELAY
336	hex "sunxi dram dqs_gating_delay value"
337	default 0
338	---help---
339	Set the dram controller dqs_gating_delay parmeter. Each byte
340	encodes the DQS gating delay for each byte lane. The delay
341	granularity is 1/4 cycle. For example, the value 0x05060606
342	means that the delay is 5 quarter-cycles for one lane (1.25
343	cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
344	The default value 0 means autodetection. The results of hardware
345	autodetection are not very reliable and depend on the chip
346	temperature (sometimes producing different results on cold start
347	and warm reboot). But the accuracy of hardware autodetection
348	is usually good enough, unless running at really high DRAM
349	clocks speeds (up to 600MHz). If unsure, keep as 0.
350
351choice
352	prompt "sunxi dram timings"
353	default DRAM_TIMINGS_VENDOR_MAGIC
354	---help---
355	Select the timings of the DDR3 chips.
356
357config DRAM_TIMINGS_VENDOR_MAGIC
358	bool "Magic vendor timings from Android"
359	---help---
360	The same DRAM timings as in the Allwinner boot0 bootloader.
361
362config DRAM_TIMINGS_DDR3_1066F_1333H
363	bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
364	---help---
365	Use the timings of the standard JEDEC DDR3-1066F speed bin for
366	DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
367	for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
368	used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
369	or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
370	that down binning to DDR3-1066F is supported (because DDR3-1066F
371	uses a bit faster timings than DDR3-1333H).
372
373config DRAM_TIMINGS_DDR3_800E_1066G_1333J
374	bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
375	---help---
376	Use the timings of the slowest possible JEDEC speed bin for the
377	selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
378	DDR3-800E, DDR3-1066G or DDR3-1333J.
379
380endchoice
381
382endif
383
384if MACH_SUN8I_A23
385config DRAM_ODT_CORRECTION
386	int "sunxi dram odt correction value"
387	default 0
388	---help---
389	Set the dram odt correction value (range -255 - 255). In allwinner
390	fex files, this option is found in bits 8-15 of the u32 odt_en variable
391	in the [dram] section. When bit 31 of the odt_en variable is set
392	then the correction is negative. Usually the value for this is 0.
393endif
394
395config SYS_CLK_FREQ
396	default 1008000000 if MACH_SUN4I
397	default 1008000000 if MACH_SUN5I
398	default 1008000000 if MACH_SUN6I
399	default 912000000 if MACH_SUN7I
400	default 1008000000 if MACH_SUN8I
401	default 1008000000 if MACH_SUN9I
402	default 816000000 if MACH_SUN50I
403
404config SYS_CONFIG_NAME
405	default "sun4i" if MACH_SUN4I
406	default "sun5i" if MACH_SUN5I
407	default "sun6i" if MACH_SUN6I
408	default "sun7i" if MACH_SUN7I
409	default "sun8i" if MACH_SUN8I
410	default "sun9i" if MACH_SUN9I
411	default "sun50i" if MACH_SUN50I
412
413config SYS_BOARD
414	default "sunxi"
415
416config SYS_SOC
417	default "sunxi"
418
419config UART0_PORT_F
420	bool "UART0 on MicroSD breakout board"
421	default n
422	---help---
423	Repurpose the SD card slot for getting access to the UART0 serial
424	console. Primarily useful only for low level u-boot debugging on
425	tablets, where normal UART0 is difficult to access and requires
426	device disassembly and/or soldering. As the SD card can't be used
427	at the same time, the system can be only booted in the FEL mode.
428	Only enable this if you really know what you are doing.
429
430config OLD_SUNXI_KERNEL_COMPAT
431	bool "Enable workarounds for booting old kernels"
432	default n
433	---help---
434	Set this to enable various workarounds for old kernels, this results in
435	sub-optimal settings for newer kernels, only enable if needed.
436
437config MACPWR
438	string "MAC power pin"
439	default ""
440	help
441	  Set the pin used to power the MAC. This takes a string in the format
442	  understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
443
444config MMC0_CD_PIN
445	string "Card detect pin for mmc0"
446	default "PF6" if MACH_SUN8I_A83T || MACH_SUNXI_H3_H5 || MACH_SUN50I
447	default ""
448	---help---
449	Set the card detect pin for mmc0, leave empty to not use cd. This
450	takes a string in the format understood by sunxi_name_to_gpio, e.g.
451	PH1 for pin 1 of port H.
452
453config MMC1_CD_PIN
454	string "Card detect pin for mmc1"
455	default ""
456	---help---
457	See MMC0_CD_PIN help text.
458
459config MMC2_CD_PIN
460	string "Card detect pin for mmc2"
461	default ""
462	---help---
463	See MMC0_CD_PIN help text.
464
465config MMC3_CD_PIN
466	string "Card detect pin for mmc3"
467	default ""
468	---help---
469	See MMC0_CD_PIN help text.
470
471config MMC1_PINS
472	string "Pins for mmc1"
473	default ""
474	---help---
475	Set the pins used for mmc1, when applicable. This takes a string in the
476	format understood by sunxi_name_to_gpio_bank, e.g. PH for port H.
477
478config MMC2_PINS
479	string "Pins for mmc2"
480	default ""
481	---help---
482	See MMC1_PINS help text.
483
484config MMC3_PINS
485	string "Pins for mmc3"
486	default ""
487	---help---
488	See MMC1_PINS help text.
489
490config MMC_SUNXI_SLOT_EXTRA
491	int "mmc extra slot number"
492	default -1
493	---help---
494	sunxi builds always enable mmc0, some boards also have a second sdcard
495	slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
496	support for this.
497
498config INITIAL_USB_SCAN_DELAY
499	int "delay initial usb scan by x ms to allow builtin devices to init"
500	default 0
501	---help---
502	Some boards have on board usb devices which need longer than the
503	USB spec's 1 second to connect from board powerup. Set this config
504	option to a non 0 value to add an extra delay before the first usb
505	bus scan.
506
507config USB0_VBUS_PIN
508	string "Vbus enable pin for usb0 (otg)"
509	default ""
510	---help---
511	Set the Vbus enable pin for usb0 (otg). This takes a string in the
512	format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
513
514config USB0_VBUS_DET
515	string "Vbus detect pin for usb0 (otg)"
516	default ""
517	---help---
518	Set the Vbus detect pin for usb0 (otg). This takes a string in the
519	format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
520
521config USB0_ID_DET
522	string "ID detect pin for usb0 (otg)"
523	default ""
524	---help---
525	Set the ID detect pin for usb0 (otg). This takes a string in the
526	format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
527
528config USB1_VBUS_PIN
529	string "Vbus enable pin for usb1 (ehci0)"
530	default "PH6" if MACH_SUN4I || MACH_SUN7I
531	default "PH27" if MACH_SUN6I
532	---help---
533	Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
534	a string in the format understood by sunxi_name_to_gpio, e.g.
535	PH1 for pin 1 of port H.
536
537config USB2_VBUS_PIN
538	string "Vbus enable pin for usb2 (ehci1)"
539	default "PH3" if MACH_SUN4I || MACH_SUN7I
540	default "PH24" if MACH_SUN6I
541	---help---
542	See USB1_VBUS_PIN help text.
543
544config USB3_VBUS_PIN
545	string "Vbus enable pin for usb3 (ehci2)"
546	default ""
547	---help---
548	See USB1_VBUS_PIN help text.
549
550config I2C0_ENABLE
551	bool "Enable I2C/TWI controller 0"
552	default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_R40
553	default n if MACH_SUN6I || MACH_SUN8I
554	select CMD_I2C
555	---help---
556	This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
557	its clock and setting up the bus. This is especially useful on devices
558	with slaves connected to the bus or with pins exposed through e.g. an
559	expansion port/header.
560
561config I2C1_ENABLE
562	bool "Enable I2C/TWI controller 1"
563	default n
564	select CMD_I2C
565	---help---
566	See I2C0_ENABLE help text.
567
568config I2C2_ENABLE
569	bool "Enable I2C/TWI controller 2"
570	default n
571	select CMD_I2C
572	---help---
573	See I2C0_ENABLE help text.
574
575if MACH_SUN6I || MACH_SUN7I
576config I2C3_ENABLE
577	bool "Enable I2C/TWI controller 3"
578	default n
579	select CMD_I2C
580	---help---
581	See I2C0_ENABLE help text.
582endif
583
584if SUNXI_GEN_SUN6I
585config R_I2C_ENABLE
586	bool "Enable the PRCM I2C/TWI controller"
587	# This is used for the pmic on H3
588	default y if SY8106A_POWER
589	select CMD_I2C
590	---help---
591	Set this to y to enable the I2C controller which is part of the PRCM.
592endif
593
594if MACH_SUN7I
595config I2C4_ENABLE
596	bool "Enable I2C/TWI controller 4"
597	default n
598	select CMD_I2C
599	---help---
600	See I2C0_ENABLE help text.
601endif
602
603config AXP_GPIO
604	bool "Enable support for gpio-s on axp PMICs"
605	default n
606	---help---
607	Say Y here to enable support for the gpio pins of the axp PMIC ICs.
608
609config VIDEO
610	bool "Enable graphical uboot console on HDMI, LCD or VGA"
611	depends on !MACH_SUN8I_A83T
612	depends on !MACH_SUNXI_H3_H5
613	depends on !MACH_SUN8I_R40
614	depends on !MACH_SUN8I_V3S
615	depends on !MACH_SUN9I
616	depends on !MACH_SUN50I
617	default y
618	---help---
619	Say Y here to add support for using a cfb console on the HDMI, LCD
620	or VGA output found on most sunxi devices. See doc/README.video for
621	info on how to select the video output and mode.
622
623config VIDEO_HDMI
624	bool "HDMI output support"
625	depends on VIDEO && !MACH_SUN8I
626	default y
627	---help---
628	Say Y here to add support for outputting video over HDMI.
629
630config VIDEO_VGA
631	bool "VGA output support"
632	depends on VIDEO && (MACH_SUN4I || MACH_SUN7I)
633	default n
634	---help---
635	Say Y here to add support for outputting video over VGA.
636
637config VIDEO_VGA_VIA_LCD
638	bool "VGA via LCD controller support"
639	depends on VIDEO && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
640	default n
641	---help---
642	Say Y here to add support for external DACs connected to the parallel
643	LCD interface driving a VGA connector, such as found on the
644	Olimex A13 boards.
645
646config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
647	bool "Force sync active high for VGA via LCD controller support"
648	depends on VIDEO_VGA_VIA_LCD
649	default n
650	---help---
651	Say Y here if you've a board which uses opendrain drivers for the vga
652	hsync and vsync signals. Opendrain drivers cannot generate steep enough
653	positive edges for a stable video output, so on boards with opendrain
654	drivers the sync signals must always be active high.
655
656config VIDEO_VGA_EXTERNAL_DAC_EN
657	string "LCD panel power enable pin"
658	depends on VIDEO_VGA_VIA_LCD
659	default ""
660	---help---
661	Set the enable pin for the external VGA DAC. This takes a string in the
662	format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
663
664config VIDEO_COMPOSITE
665	bool "Composite video output support"
666	depends on VIDEO && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
667	default n
668	---help---
669	Say Y here to add support for outputting composite video.
670
671config VIDEO_LCD_MODE
672	string "LCD panel timing details"
673	depends on VIDEO
674	default ""
675	---help---
676	LCD panel timing details string, leave empty if there is no LCD panel.
677	This is in drivers/video/videomodes.c: video_get_params() format, e.g.
678	x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
679	Also see: http://linux-sunxi.org/LCD
680
681config VIDEO_LCD_DCLK_PHASE
682	int "LCD panel display clock phase"
683	depends on VIDEO
684	default 1
685	---help---
686	Select LCD panel display clock phase shift, range 0-3.
687
688config VIDEO_LCD_POWER
689	string "LCD panel power enable pin"
690	depends on VIDEO
691	default ""
692	---help---
693	Set the power enable pin for the LCD panel. This takes a string in the
694	format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
695
696config VIDEO_LCD_RESET
697	string "LCD panel reset pin"
698	depends on VIDEO
699	default ""
700	---help---
701	Set the reset pin for the LCD panel. This takes a string in the format
702	understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
703
704config VIDEO_LCD_BL_EN
705	string "LCD panel backlight enable pin"
706	depends on VIDEO
707	default ""
708	---help---
709	Set the backlight enable pin for the LCD panel. This takes a string in the
710	the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
711	port H.
712
713config VIDEO_LCD_BL_PWM
714	string "LCD panel backlight pwm pin"
715	depends on VIDEO
716	default ""
717	---help---
718	Set the backlight pwm pin for the LCD panel. This takes a string in the
719	format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
720
721config VIDEO_LCD_BL_PWM_ACTIVE_LOW
722	bool "LCD panel backlight pwm is inverted"
723	depends on VIDEO
724	default y
725	---help---
726	Set this if the backlight pwm output is active low.
727
728config VIDEO_LCD_PANEL_I2C
729	bool "LCD panel needs to be configured via i2c"
730	depends on VIDEO
731	default n
732	select CMD_I2C
733	---help---
734	Say y here if the LCD panel needs to be configured via i2c. This
735	will add a bitbang i2c controller using gpios to talk to the LCD.
736
737config VIDEO_LCD_PANEL_I2C_SDA
738	string "LCD panel i2c interface SDA pin"
739	depends on VIDEO_LCD_PANEL_I2C
740	default "PG12"
741	---help---
742	Set the SDA pin for the LCD i2c interface. This takes a string in the
743	format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
744
745config VIDEO_LCD_PANEL_I2C_SCL
746	string "LCD panel i2c interface SCL pin"
747	depends on VIDEO_LCD_PANEL_I2C
748	default "PG10"
749	---help---
750	Set the SCL pin for the LCD i2c interface. This takes a string in the
751	format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
752
753
754# Note only one of these may be selected at a time! But hidden choices are
755# not supported by Kconfig
756config VIDEO_LCD_IF_PARALLEL
757	bool
758
759config VIDEO_LCD_IF_LVDS
760	bool
761
762config SUNXI_DE2
763	bool
764	default n
765
766config VIDEO_DE2
767	bool "Display Engine 2 video driver"
768	depends on SUNXI_DE2
769	select DM_VIDEO
770	select DISPLAY
771	default y
772	---help---
773	Say y here if you want to build DE2 video driver which is present on
774	newer SoCs. Currently only HDMI output is supported.
775
776
777choice
778	prompt "LCD panel support"
779	depends on VIDEO
780	---help---
781	Select which type of LCD panel to support.
782
783config VIDEO_LCD_PANEL_PARALLEL
784	bool "Generic parallel interface LCD panel"
785	select VIDEO_LCD_IF_PARALLEL
786
787config VIDEO_LCD_PANEL_LVDS
788	bool "Generic lvds interface LCD panel"
789	select VIDEO_LCD_IF_LVDS
790
791config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
792	bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
793	select VIDEO_LCD_SSD2828
794	select VIDEO_LCD_IF_PARALLEL
795	---help---
796	7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
797
798config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
799	bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip"
800	select VIDEO_LCD_ANX9804
801	select VIDEO_LCD_IF_PARALLEL
802	select VIDEO_LCD_PANEL_I2C
803	---help---
804	Select this for eDP LCD panels with 4 lanes running at 1.62G,
805	connected via an ANX9804 bridge chip.
806
807config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
808	bool "Hitachi tx18d42vm LCD panel"
809	select VIDEO_LCD_HITACHI_TX18D42VM
810	select VIDEO_LCD_IF_LVDS
811	---help---
812	7.85" 1024x768 Hitachi tx18d42vm LCD panel support
813
814config VIDEO_LCD_TL059WV5C0
815	bool "tl059wv5c0 LCD panel"
816	select VIDEO_LCD_PANEL_I2C
817	select VIDEO_LCD_IF_PARALLEL
818	---help---
819	6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and
820	Aigo M60/M608/M606 tablets.
821
822endchoice
823
824config SATAPWR
825	string "SATA power pin"
826	default ""
827	help
828	  Set the pins used to power the SATA. This takes a string in the
829	  format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
830	  port H.
831
832config GMAC_TX_DELAY
833	int "GMAC Transmit Clock Delay Chain"
834	default 0
835	---help---
836	Set the GMAC Transmit Clock Delay Chain value.
837
838config SPL_STACK_R_ADDR
839	default 0x4fe00000 if MACH_SUN4I
840	default 0x4fe00000 if MACH_SUN5I
841	default 0x4fe00000 if MACH_SUN6I
842	default 0x4fe00000 if MACH_SUN7I
843	default 0x4fe00000 if MACH_SUN8I
844	default 0x2fe00000 if MACH_SUN9I
845	default 0x4fe00000 if MACH_SUN50I
846
847endif
848