xref: /openbmc/u-boot/arch/arm/mach-stm32mp/spl.c (revision 11dfd1a3)
12514c2d0SPatrick Delaunay /*
22514c2d0SPatrick Delaunay  * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
32514c2d0SPatrick Delaunay  *
42514c2d0SPatrick Delaunay  * SPDX-License-Identifier:	GPL-2.0+	BSD-3-Clause
52514c2d0SPatrick Delaunay  */
62514c2d0SPatrick Delaunay 
72514c2d0SPatrick Delaunay #include <common.h>
82514c2d0SPatrick Delaunay #include <dm.h>
92514c2d0SPatrick Delaunay #include <spl.h>
10*11dfd1a3SPatrick Delaunay #include <asm/io.h>
112514c2d0SPatrick Delaunay 
122514c2d0SPatrick Delaunay u32 spl_boot_device(void)
132514c2d0SPatrick Delaunay {
14*11dfd1a3SPatrick Delaunay 	u32 boot_mode;
15*11dfd1a3SPatrick Delaunay 
16*11dfd1a3SPatrick Delaunay 	boot_mode = (readl(TAMP_BOOT_CONTEXT) & TAMP_BOOT_MODE_MASK) >>
17*11dfd1a3SPatrick Delaunay 		    TAMP_BOOT_MODE_SHIFT;
18*11dfd1a3SPatrick Delaunay 	clrsetbits_le32(TAMP_BOOT_CONTEXT,
19*11dfd1a3SPatrick Delaunay 			TAMP_BOOT_MODE_MASK,
20*11dfd1a3SPatrick Delaunay 			boot_mode << TAMP_BOOT_MODE_SHIFT);
21*11dfd1a3SPatrick Delaunay 
22*11dfd1a3SPatrick Delaunay 	switch (boot_mode) {
23*11dfd1a3SPatrick Delaunay 	case BOOT_FLASH_SD_1:
24*11dfd1a3SPatrick Delaunay 	case BOOT_FLASH_EMMC_1:
25*11dfd1a3SPatrick Delaunay 		return BOOT_DEVICE_MMC1;
26*11dfd1a3SPatrick Delaunay 	case BOOT_FLASH_SD_2:
27*11dfd1a3SPatrick Delaunay 	case BOOT_FLASH_EMMC_2:
28*11dfd1a3SPatrick Delaunay 		return BOOT_DEVICE_MMC2;
29*11dfd1a3SPatrick Delaunay 	}
30*11dfd1a3SPatrick Delaunay 
312514c2d0SPatrick Delaunay 	return BOOT_DEVICE_MMC1;
322514c2d0SPatrick Delaunay }
332514c2d0SPatrick Delaunay 
342514c2d0SPatrick Delaunay u32 spl_boot_mode(const u32 boot_device)
352514c2d0SPatrick Delaunay {
362514c2d0SPatrick Delaunay 	return MMCSD_MODE_RAW;
372514c2d0SPatrick Delaunay }
382514c2d0SPatrick Delaunay 
39*11dfd1a3SPatrick Delaunay int spl_boot_partition(const u32 boot_device)
40*11dfd1a3SPatrick Delaunay {
41*11dfd1a3SPatrick Delaunay 	switch (boot_device) {
42*11dfd1a3SPatrick Delaunay 	case BOOT_DEVICE_MMC1:
43*11dfd1a3SPatrick Delaunay 		return CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION;
44*11dfd1a3SPatrick Delaunay 	case BOOT_DEVICE_MMC2:
45*11dfd1a3SPatrick Delaunay 		return CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_MMC2;
46*11dfd1a3SPatrick Delaunay 	default:
47*11dfd1a3SPatrick Delaunay 		return -EINVAL;
48*11dfd1a3SPatrick Delaunay 	}
49*11dfd1a3SPatrick Delaunay }
50*11dfd1a3SPatrick Delaunay 
512514c2d0SPatrick Delaunay void board_init_f(ulong dummy)
522514c2d0SPatrick Delaunay {
532514c2d0SPatrick Delaunay 	struct udevice *dev;
542514c2d0SPatrick Delaunay 	int ret;
552514c2d0SPatrick Delaunay 
562514c2d0SPatrick Delaunay 	arch_cpu_init();
572514c2d0SPatrick Delaunay 
582514c2d0SPatrick Delaunay 	ret = spl_early_init();
592514c2d0SPatrick Delaunay 	if (ret) {
602514c2d0SPatrick Delaunay 		debug("spl_early_init() failed: %d\n", ret);
612514c2d0SPatrick Delaunay 		hang();
622514c2d0SPatrick Delaunay 	}
632514c2d0SPatrick Delaunay 
642514c2d0SPatrick Delaunay 	ret = uclass_get_device(UCLASS_CLK, 0, &dev);
652514c2d0SPatrick Delaunay 	if (ret) {
662514c2d0SPatrick Delaunay 		debug("Clock init failed: %d\n", ret);
672514c2d0SPatrick Delaunay 		return;
682514c2d0SPatrick Delaunay 	}
692514c2d0SPatrick Delaunay 
702514c2d0SPatrick Delaunay 	ret = uclass_get_device(UCLASS_RESET, 0, &dev);
712514c2d0SPatrick Delaunay 	if (ret) {
722514c2d0SPatrick Delaunay 		debug("Reset init failed: %d\n", ret);
732514c2d0SPatrick Delaunay 		return;
742514c2d0SPatrick Delaunay 	}
752514c2d0SPatrick Delaunay 
762514c2d0SPatrick Delaunay 	ret = uclass_get_device(UCLASS_PINCTRL, 0, &dev);
772514c2d0SPatrick Delaunay 	if (ret) {
782514c2d0SPatrick Delaunay 		debug("%s: Cannot find pinctrl device\n", __func__);
792514c2d0SPatrick Delaunay 		return;
802514c2d0SPatrick Delaunay 	}
812514c2d0SPatrick Delaunay 
822514c2d0SPatrick Delaunay 	/* enable console uart printing */
832514c2d0SPatrick Delaunay 	preloader_console_init();
842514c2d0SPatrick Delaunay 
852514c2d0SPatrick Delaunay 	ret = uclass_get_device(UCLASS_RAM, 0, &dev);
862514c2d0SPatrick Delaunay 	if (ret) {
872514c2d0SPatrick Delaunay 		debug("DRAM init failed: %d\n", ret);
882514c2d0SPatrick Delaunay 		return;
892514c2d0SPatrick Delaunay 	}
902514c2d0SPatrick Delaunay }
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