1*2514c2d0SPatrick Delaunay /* 2*2514c2d0SPatrick Delaunay * Copyright (C) 2018, STMicroelectronics - All Rights Reserved 3*2514c2d0SPatrick Delaunay * 4*2514c2d0SPatrick Delaunay * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause 5*2514c2d0SPatrick Delaunay */ 6*2514c2d0SPatrick Delaunay 7*2514c2d0SPatrick Delaunay #ifndef _MACH_STM32_H_ 8*2514c2d0SPatrick Delaunay #define _MACH_STM32_H_ 9*2514c2d0SPatrick Delaunay 10*2514c2d0SPatrick Delaunay /* 11*2514c2d0SPatrick Delaunay * Peripheral memory map 12*2514c2d0SPatrick Delaunay * only address used before device tree parsing 13*2514c2d0SPatrick Delaunay */ 14*2514c2d0SPatrick Delaunay #define STM32_RCC_BASE 0x50000000 15*2514c2d0SPatrick Delaunay #define STM32_PWR_BASE 0x50001000 16*2514c2d0SPatrick Delaunay #define STM32_DBGMCU_BASE 0x50081000 17*2514c2d0SPatrick Delaunay #define STM32_TZC_BASE 0x5C006000 18*2514c2d0SPatrick Delaunay #define STM32_ETZPC_BASE 0x5C007000 19*2514c2d0SPatrick Delaunay #define STM32_TAMP_BASE 0x5C00A000 20*2514c2d0SPatrick Delaunay 21*2514c2d0SPatrick Delaunay #define STM32_SYSRAM_BASE 0x2FFC0000 22*2514c2d0SPatrick Delaunay #define STM32_SYSRAM_SIZE SZ_256K 23*2514c2d0SPatrick Delaunay 24*2514c2d0SPatrick Delaunay #define STM32_DDR_BASE 0xC0000000 25*2514c2d0SPatrick Delaunay #define STM32_DDR_SIZE SZ_1G 26*2514c2d0SPatrick Delaunay 27*2514c2d0SPatrick Delaunay #endif /* _MACH_STM32_H_ */ 28