183d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 22514c2d0SPatrick Delaunay /* 32514c2d0SPatrick Delaunay * (C) Copyright 2016 42514c2d0SPatrick Delaunay * Vikas Manocha, <vikas.manocha@st.com> 52514c2d0SPatrick Delaunay */ 62514c2d0SPatrick Delaunay 72514c2d0SPatrick Delaunay #ifndef _STM32_GPIO_H_ 82514c2d0SPatrick Delaunay #define _STM32_GPIO_H_ 92514c2d0SPatrick Delaunay #include <asm/gpio.h> 102514c2d0SPatrick Delaunay 11*b2f84e37SPatrice Chotard #define STM32_GPIOS_PER_BANK 16 12*b2f84e37SPatrice Chotard 132514c2d0SPatrick Delaunay enum stm32_gpio_port { 142514c2d0SPatrick Delaunay STM32_GPIO_PORT_A = 0, 152514c2d0SPatrick Delaunay STM32_GPIO_PORT_B, 162514c2d0SPatrick Delaunay STM32_GPIO_PORT_C, 172514c2d0SPatrick Delaunay STM32_GPIO_PORT_D, 182514c2d0SPatrick Delaunay STM32_GPIO_PORT_E, 192514c2d0SPatrick Delaunay STM32_GPIO_PORT_F, 202514c2d0SPatrick Delaunay STM32_GPIO_PORT_G, 212514c2d0SPatrick Delaunay STM32_GPIO_PORT_H, 222514c2d0SPatrick Delaunay STM32_GPIO_PORT_I 232514c2d0SPatrick Delaunay }; 242514c2d0SPatrick Delaunay 252514c2d0SPatrick Delaunay enum stm32_gpio_pin { 262514c2d0SPatrick Delaunay STM32_GPIO_PIN_0 = 0, 272514c2d0SPatrick Delaunay STM32_GPIO_PIN_1, 282514c2d0SPatrick Delaunay STM32_GPIO_PIN_2, 292514c2d0SPatrick Delaunay STM32_GPIO_PIN_3, 302514c2d0SPatrick Delaunay STM32_GPIO_PIN_4, 312514c2d0SPatrick Delaunay STM32_GPIO_PIN_5, 322514c2d0SPatrick Delaunay STM32_GPIO_PIN_6, 332514c2d0SPatrick Delaunay STM32_GPIO_PIN_7, 342514c2d0SPatrick Delaunay STM32_GPIO_PIN_8, 352514c2d0SPatrick Delaunay STM32_GPIO_PIN_9, 362514c2d0SPatrick Delaunay STM32_GPIO_PIN_10, 372514c2d0SPatrick Delaunay STM32_GPIO_PIN_11, 382514c2d0SPatrick Delaunay STM32_GPIO_PIN_12, 392514c2d0SPatrick Delaunay STM32_GPIO_PIN_13, 402514c2d0SPatrick Delaunay STM32_GPIO_PIN_14, 412514c2d0SPatrick Delaunay STM32_GPIO_PIN_15 422514c2d0SPatrick Delaunay }; 432514c2d0SPatrick Delaunay 442514c2d0SPatrick Delaunay enum stm32_gpio_mode { 452514c2d0SPatrick Delaunay STM32_GPIO_MODE_IN = 0, 462514c2d0SPatrick Delaunay STM32_GPIO_MODE_OUT, 472514c2d0SPatrick Delaunay STM32_GPIO_MODE_AF, 482514c2d0SPatrick Delaunay STM32_GPIO_MODE_AN 492514c2d0SPatrick Delaunay }; 502514c2d0SPatrick Delaunay 512514c2d0SPatrick Delaunay enum stm32_gpio_otype { 522514c2d0SPatrick Delaunay STM32_GPIO_OTYPE_PP = 0, 532514c2d0SPatrick Delaunay STM32_GPIO_OTYPE_OD 542514c2d0SPatrick Delaunay }; 552514c2d0SPatrick Delaunay 562514c2d0SPatrick Delaunay enum stm32_gpio_speed { 572514c2d0SPatrick Delaunay STM32_GPIO_SPEED_2M = 0, 582514c2d0SPatrick Delaunay STM32_GPIO_SPEED_25M, 592514c2d0SPatrick Delaunay STM32_GPIO_SPEED_50M, 602514c2d0SPatrick Delaunay STM32_GPIO_SPEED_100M 612514c2d0SPatrick Delaunay }; 622514c2d0SPatrick Delaunay 632514c2d0SPatrick Delaunay enum stm32_gpio_pupd { 642514c2d0SPatrick Delaunay STM32_GPIO_PUPD_NO = 0, 652514c2d0SPatrick Delaunay STM32_GPIO_PUPD_UP, 662514c2d0SPatrick Delaunay STM32_GPIO_PUPD_DOWN 672514c2d0SPatrick Delaunay }; 682514c2d0SPatrick Delaunay 692514c2d0SPatrick Delaunay enum stm32_gpio_af { 702514c2d0SPatrick Delaunay STM32_GPIO_AF0 = 0, 712514c2d0SPatrick Delaunay STM32_GPIO_AF1, 722514c2d0SPatrick Delaunay STM32_GPIO_AF2, 732514c2d0SPatrick Delaunay STM32_GPIO_AF3, 742514c2d0SPatrick Delaunay STM32_GPIO_AF4, 752514c2d0SPatrick Delaunay STM32_GPIO_AF5, 762514c2d0SPatrick Delaunay STM32_GPIO_AF6, 772514c2d0SPatrick Delaunay STM32_GPIO_AF7, 782514c2d0SPatrick Delaunay STM32_GPIO_AF8, 792514c2d0SPatrick Delaunay STM32_GPIO_AF9, 802514c2d0SPatrick Delaunay STM32_GPIO_AF10, 812514c2d0SPatrick Delaunay STM32_GPIO_AF11, 822514c2d0SPatrick Delaunay STM32_GPIO_AF12, 832514c2d0SPatrick Delaunay STM32_GPIO_AF13, 842514c2d0SPatrick Delaunay STM32_GPIO_AF14, 852514c2d0SPatrick Delaunay STM32_GPIO_AF15 862514c2d0SPatrick Delaunay }; 872514c2d0SPatrick Delaunay 882514c2d0SPatrick Delaunay struct stm32_gpio_dsc { 892514c2d0SPatrick Delaunay enum stm32_gpio_port port; 902514c2d0SPatrick Delaunay enum stm32_gpio_pin pin; 912514c2d0SPatrick Delaunay }; 922514c2d0SPatrick Delaunay 932514c2d0SPatrick Delaunay struct stm32_gpio_ctl { 942514c2d0SPatrick Delaunay enum stm32_gpio_mode mode; 952514c2d0SPatrick Delaunay enum stm32_gpio_otype otype; 962514c2d0SPatrick Delaunay enum stm32_gpio_speed speed; 972514c2d0SPatrick Delaunay enum stm32_gpio_pupd pupd; 982514c2d0SPatrick Delaunay enum stm32_gpio_af af; 992514c2d0SPatrick Delaunay }; 1002514c2d0SPatrick Delaunay 1012514c2d0SPatrick Delaunay struct stm32_gpio_regs { 1022514c2d0SPatrick Delaunay u32 moder; /* GPIO port mode */ 1032514c2d0SPatrick Delaunay u32 otyper; /* GPIO port output type */ 1042514c2d0SPatrick Delaunay u32 ospeedr; /* GPIO port output speed */ 1052514c2d0SPatrick Delaunay u32 pupdr; /* GPIO port pull-up/pull-down */ 1062514c2d0SPatrick Delaunay u32 idr; /* GPIO port input data */ 1072514c2d0SPatrick Delaunay u32 odr; /* GPIO port output data */ 1082514c2d0SPatrick Delaunay u32 bsrr; /* GPIO port bit set/reset */ 1092514c2d0SPatrick Delaunay u32 lckr; /* GPIO port configuration lock */ 1102514c2d0SPatrick Delaunay u32 afr[2]; /* GPIO alternate function */ 1112514c2d0SPatrick Delaunay }; 1122514c2d0SPatrick Delaunay 1132514c2d0SPatrick Delaunay struct stm32_gpio_priv { 1142514c2d0SPatrick Delaunay struct stm32_gpio_regs *regs; 115dbf928ddSPatrice Chotard unsigned int gpio_range; 1162514c2d0SPatrick Delaunay }; 117dbf928ddSPatrice Chotard 118dbf928ddSPatrice Chotard int stm32_offset_to_index(struct udevice *dev, unsigned int offset); 119dbf928ddSPatrice Chotard 1202514c2d0SPatrick Delaunay #endif /* _STM32_GPIO_H_ */ 121