1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause 2 /* 3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved 4 */ 5 #include <common.h> 6 #include <clk.h> 7 #include <debug_uart.h> 8 #include <environment.h> 9 #include <misc.h> 10 #include <asm/io.h> 11 #include <asm/arch/stm32.h> 12 #include <asm/arch/sys_proto.h> 13 #include <dm/device.h> 14 #include <dm/uclass.h> 15 16 /* RCC register */ 17 #define RCC_TZCR (STM32_RCC_BASE + 0x00) 18 #define RCC_DBGCFGR (STM32_RCC_BASE + 0x080C) 19 #define RCC_BDCR (STM32_RCC_BASE + 0x0140) 20 #define RCC_MP_APB5ENSETR (STM32_RCC_BASE + 0x0208) 21 #define RCC_BDCR_VSWRST BIT(31) 22 #define RCC_BDCR_RTCSRC GENMASK(17, 16) 23 #define RCC_DBGCFGR_DBGCKEN BIT(8) 24 25 /* Security register */ 26 #define ETZPC_TZMA1_SIZE (STM32_ETZPC_BASE + 0x04) 27 #define ETZPC_DECPROT0 (STM32_ETZPC_BASE + 0x10) 28 29 #define TZC_GATE_KEEPER (STM32_TZC_BASE + 0x008) 30 #define TZC_REGION_ATTRIBUTE0 (STM32_TZC_BASE + 0x110) 31 #define TZC_REGION_ID_ACCESS0 (STM32_TZC_BASE + 0x114) 32 33 #define TAMP_CR1 (STM32_TAMP_BASE + 0x00) 34 35 #define PWR_CR1 (STM32_PWR_BASE + 0x00) 36 #define PWR_CR1_DBP BIT(8) 37 38 /* DBGMCU register */ 39 #define DBGMCU_IDC (STM32_DBGMCU_BASE + 0x00) 40 #define DBGMCU_APB4FZ1 (STM32_DBGMCU_BASE + 0x2C) 41 #define DBGMCU_APB4FZ1_IWDG2 BIT(2) 42 #define DBGMCU_IDC_DEV_ID_MASK GENMASK(11, 0) 43 #define DBGMCU_IDC_DEV_ID_SHIFT 0 44 #define DBGMCU_IDC_REV_ID_MASK GENMASK(31, 16) 45 #define DBGMCU_IDC_REV_ID_SHIFT 16 46 47 /* boot interface from Bootrom 48 * - boot instance = bit 31:16 49 * - boot device = bit 15:0 50 */ 51 #define BOOTROM_PARAM_ADDR 0x2FFC0078 52 #define BOOTROM_MODE_MASK GENMASK(15, 0) 53 #define BOOTROM_MODE_SHIFT 0 54 #define BOOTROM_INSTANCE_MASK GENMASK(31, 16) 55 #define BOOTROM_INSTANCE_SHIFT 16 56 57 /* BSEC OTP index */ 58 #define BSEC_OTP_SERIAL 13 59 #define BSEC_OTP_MAC 57 60 61 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) 62 static void security_init(void) 63 { 64 /* Disable the backup domain write protection */ 65 /* the protection is enable at each reset by hardware */ 66 /* And must be disable by software */ 67 setbits_le32(PWR_CR1, PWR_CR1_DBP); 68 69 while (!(readl(PWR_CR1) & PWR_CR1_DBP)) 70 ; 71 72 /* If RTC clock isn't enable so this is a cold boot then we need 73 * to reset the backup domain 74 */ 75 if (!(readl(RCC_BDCR) & RCC_BDCR_RTCSRC)) { 76 setbits_le32(RCC_BDCR, RCC_BDCR_VSWRST); 77 while (!(readl(RCC_BDCR) & RCC_BDCR_VSWRST)) 78 ; 79 clrbits_le32(RCC_BDCR, RCC_BDCR_VSWRST); 80 } 81 82 /* allow non secure access in Write/Read for all peripheral */ 83 writel(GENMASK(25, 0), ETZPC_DECPROT0); 84 85 /* Open SYSRAM for no secure access */ 86 writel(0x0, ETZPC_TZMA1_SIZE); 87 88 /* enable TZC1 TZC2 clock */ 89 writel(BIT(11) | BIT(12), RCC_MP_APB5ENSETR); 90 91 /* Region 0 set to no access by default */ 92 /* bit 0 / 16 => nsaid0 read/write Enable 93 * bit 1 / 17 => nsaid1 read/write Enable 94 * ... 95 * bit 15 / 31 => nsaid15 read/write Enable 96 */ 97 writel(0xFFFFFFFF, TZC_REGION_ID_ACCESS0); 98 /* bit 30 / 31 => Secure Global Enable : write/read */ 99 /* bit 0 / 1 => Region Enable for filter 0/1 */ 100 writel(BIT(0) | BIT(1) | BIT(30) | BIT(31), TZC_REGION_ATTRIBUTE0); 101 102 /* Enable Filter 0 and 1 */ 103 setbits_le32(TZC_GATE_KEEPER, BIT(0) | BIT(1)); 104 105 /* RCC trust zone deactivated */ 106 writel(0x0, RCC_TZCR); 107 108 /* TAMP: deactivate the internal tamper 109 * Bit 23 ITAMP8E: monotonic counter overflow 110 * Bit 20 ITAMP5E: RTC calendar overflow 111 * Bit 19 ITAMP4E: HSE monitoring 112 * Bit 18 ITAMP3E: LSE monitoring 113 * Bit 16 ITAMP1E: RTC power domain supply monitoring 114 */ 115 writel(0x0, TAMP_CR1); 116 } 117 118 /* 119 * Debug init 120 */ 121 static void dbgmcu_init(void) 122 { 123 setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN); 124 125 /* Freeze IWDG2 if Cortex-A7 is in debug mode */ 126 setbits_le32(DBGMCU_APB4FZ1, DBGMCU_APB4FZ1_IWDG2); 127 } 128 #endif /* !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) */ 129 130 static u32 get_bootmode(void) 131 { 132 u32 boot_mode; 133 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) 134 u32 bootrom_itf = readl(BOOTROM_PARAM_ADDR); 135 u32 bootrom_device, bootrom_instance; 136 137 bootrom_device = 138 (bootrom_itf & BOOTROM_MODE_MASK) >> BOOTROM_MODE_SHIFT; 139 bootrom_instance = 140 (bootrom_itf & BOOTROM_INSTANCE_MASK) >> BOOTROM_INSTANCE_SHIFT; 141 boot_mode = 142 ((bootrom_device << BOOT_TYPE_SHIFT) & BOOT_TYPE_MASK) | 143 ((bootrom_instance << BOOT_INSTANCE_SHIFT) & 144 BOOT_INSTANCE_MASK); 145 146 /* save the boot mode in TAMP backup register */ 147 clrsetbits_le32(TAMP_BOOT_CONTEXT, 148 TAMP_BOOT_MODE_MASK, 149 boot_mode << TAMP_BOOT_MODE_SHIFT); 150 #else 151 /* read TAMP backup register */ 152 boot_mode = (readl(TAMP_BOOT_CONTEXT) & TAMP_BOOT_MODE_MASK) >> 153 TAMP_BOOT_MODE_SHIFT; 154 #endif 155 return boot_mode; 156 } 157 158 /* 159 * Early system init 160 */ 161 int arch_cpu_init(void) 162 { 163 u32 boot_mode; 164 165 /* early armv7 timer init: needed for polling */ 166 timer_init(); 167 168 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) 169 dbgmcu_init(); 170 171 security_init(); 172 #endif 173 174 /* get bootmode from BootRom context: saved in TAMP register */ 175 boot_mode = get_bootmode(); 176 177 if ((boot_mode & TAMP_BOOT_DEVICE_MASK) == BOOT_SERIAL_UART) 178 gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE; 179 #if defined(CONFIG_DEBUG_UART) && \ 180 (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)) 181 else 182 debug_uart_init(); 183 #endif 184 185 return 0; 186 } 187 188 void enable_caches(void) 189 { 190 /* Enable D-cache. I-cache is already enabled in start.S */ 191 dcache_enable(); 192 } 193 194 static u32 read_idc(void) 195 { 196 setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN); 197 198 return readl(DBGMCU_IDC); 199 } 200 201 u32 get_cpu_rev(void) 202 { 203 return (read_idc() & DBGMCU_IDC_REV_ID_MASK) >> DBGMCU_IDC_REV_ID_SHIFT; 204 } 205 206 u32 get_cpu_type(void) 207 { 208 return (read_idc() & DBGMCU_IDC_DEV_ID_MASK) >> DBGMCU_IDC_DEV_ID_SHIFT; 209 } 210 211 #if defined(CONFIG_DISPLAY_CPUINFO) 212 int print_cpuinfo(void) 213 { 214 char *cpu_s, *cpu_r; 215 216 switch (get_cpu_type()) { 217 case CPU_STMP32MP15x: 218 cpu_s = "15x"; 219 break; 220 default: 221 cpu_s = "?"; 222 break; 223 } 224 225 switch (get_cpu_rev()) { 226 case CPU_REVA: 227 cpu_r = "A"; 228 break; 229 case CPU_REVB: 230 cpu_r = "B"; 231 break; 232 default: 233 cpu_r = "?"; 234 break; 235 } 236 237 printf("CPU: STM32MP%s.%s\n", cpu_s, cpu_r); 238 239 return 0; 240 } 241 #endif /* CONFIG_DISPLAY_CPUINFO */ 242 243 static void setup_boot_mode(void) 244 { 245 char cmd[60]; 246 u32 boot_ctx = readl(TAMP_BOOT_CONTEXT); 247 u32 boot_mode = 248 (boot_ctx & TAMP_BOOT_MODE_MASK) >> TAMP_BOOT_MODE_SHIFT; 249 int instance = (boot_mode & TAMP_BOOT_INSTANCE_MASK) - 1; 250 251 pr_debug("%s: boot_ctx=0x%x => boot_mode=%x, instance=%d\n", 252 __func__, boot_ctx, boot_mode, instance); 253 254 switch (boot_mode & TAMP_BOOT_DEVICE_MASK) { 255 case BOOT_SERIAL_UART: 256 sprintf(cmd, "%d", instance); 257 env_set("boot_device", "uart"); 258 env_set("boot_instance", cmd); 259 break; 260 case BOOT_SERIAL_USB: 261 env_set("boot_device", "usb"); 262 env_set("boot_instance", "0"); 263 break; 264 case BOOT_FLASH_SD: 265 case BOOT_FLASH_EMMC: 266 sprintf(cmd, "%d", instance); 267 env_set("boot_device", "mmc"); 268 env_set("boot_instance", cmd); 269 break; 270 case BOOT_FLASH_NAND: 271 env_set("boot_device", "nand"); 272 env_set("boot_instance", "0"); 273 break; 274 case BOOT_FLASH_NOR: 275 env_set("boot_device", "nor"); 276 env_set("boot_instance", "0"); 277 break; 278 default: 279 pr_debug("unexpected boot mode = %x\n", boot_mode); 280 break; 281 } 282 } 283 284 /* 285 * If there is no MAC address in the environment, then it will be initialized 286 * (silently) from the value in the OTP. 287 */ 288 static int setup_mac_address(void) 289 { 290 #if defined(CONFIG_NET) 291 int ret; 292 int i; 293 u32 otp[2]; 294 uchar enetaddr[6]; 295 struct udevice *dev; 296 297 /* MAC already in environment */ 298 if (eth_env_get_enetaddr("ethaddr", enetaddr)) 299 return 0; 300 301 ret = uclass_get_device_by_driver(UCLASS_MISC, 302 DM_GET_DRIVER(stm32mp_bsec), 303 &dev); 304 if (ret) 305 return ret; 306 307 ret = misc_read(dev, BSEC_OTP_MAC * 4 + STM32_BSEC_OTP_OFFSET, 308 otp, sizeof(otp)); 309 if (ret < 0) 310 return ret; 311 312 for (i = 0; i < 6; i++) 313 enetaddr[i] = ((uint8_t *)&otp)[i]; 314 315 if (!is_valid_ethaddr(enetaddr)) { 316 pr_err("invalid MAC address in OTP %pM", enetaddr); 317 return -EINVAL; 318 } 319 pr_debug("OTP MAC address = %pM\n", enetaddr); 320 ret = !eth_env_set_enetaddr("ethaddr", enetaddr); 321 if (!ret) 322 pr_err("Failed to set mac address %pM from OTP: %d\n", 323 enetaddr, ret); 324 #endif 325 326 return 0; 327 } 328 329 static int setup_serial_number(void) 330 { 331 char serial_string[25]; 332 u32 otp[3] = {0, 0, 0 }; 333 struct udevice *dev; 334 int ret; 335 336 if (env_get("serial#")) 337 return 0; 338 339 ret = uclass_get_device_by_driver(UCLASS_MISC, 340 DM_GET_DRIVER(stm32mp_bsec), 341 &dev); 342 if (ret) 343 return ret; 344 345 ret = misc_read(dev, BSEC_OTP_SERIAL * 4 + STM32_BSEC_OTP_OFFSET, 346 otp, sizeof(otp)); 347 if (ret < 0) 348 return ret; 349 350 sprintf(serial_string, "%08x%08x%08x", otp[0], otp[1], otp[2]); 351 env_set("serial#", serial_string); 352 353 return 0; 354 } 355 356 int arch_misc_init(void) 357 { 358 setup_boot_mode(); 359 setup_mac_address(); 360 setup_serial_number(); 361 362 return 0; 363 } 364