1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause 2 /* 3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved 4 */ 5 #include <common.h> 6 #include <clk.h> 7 #include <asm/io.h> 8 #include <asm/arch/stm32.h> 9 #include <asm/arch/sys_proto.h> 10 #include <dm/uclass.h> 11 12 /* RCC register */ 13 #define RCC_TZCR (STM32_RCC_BASE + 0x00) 14 #define RCC_DBGCFGR (STM32_RCC_BASE + 0x080C) 15 #define RCC_BDCR (STM32_RCC_BASE + 0x0140) 16 #define RCC_MP_APB5ENSETR (STM32_RCC_BASE + 0x0208) 17 #define RCC_BDCR_VSWRST BIT(31) 18 #define RCC_BDCR_RTCSRC GENMASK(17, 16) 19 #define RCC_DBGCFGR_DBGCKEN BIT(8) 20 21 /* Security register */ 22 #define ETZPC_TZMA1_SIZE (STM32_ETZPC_BASE + 0x04) 23 #define ETZPC_DECPROT0 (STM32_ETZPC_BASE + 0x10) 24 25 #define TZC_GATE_KEEPER (STM32_TZC_BASE + 0x008) 26 #define TZC_REGION_ATTRIBUTE0 (STM32_TZC_BASE + 0x110) 27 #define TZC_REGION_ID_ACCESS0 (STM32_TZC_BASE + 0x114) 28 29 #define TAMP_CR1 (STM32_TAMP_BASE + 0x00) 30 31 #define PWR_CR1 (STM32_PWR_BASE + 0x00) 32 #define PWR_CR1_DBP BIT(8) 33 34 /* DBGMCU register */ 35 #define DBGMCU_IDC (STM32_DBGMCU_BASE + 0x00) 36 #define DBGMCU_APB4FZ1 (STM32_DBGMCU_BASE + 0x2C) 37 #define DBGMCU_APB4FZ1_IWDG2 BIT(2) 38 #define DBGMCU_IDC_DEV_ID_MASK GENMASK(11, 0) 39 #define DBGMCU_IDC_DEV_ID_SHIFT 0 40 #define DBGMCU_IDC_REV_ID_MASK GENMASK(31, 16) 41 #define DBGMCU_IDC_REV_ID_SHIFT 16 42 43 /* boot interface from Bootrom 44 * - boot instance = bit 31:16 45 * - boot device = bit 15:0 46 */ 47 #define BOOTROM_PARAM_ADDR 0x2FFC0078 48 #define BOOTROM_MODE_MASK GENMASK(15, 0) 49 #define BOOTROM_MODE_SHIFT 0 50 #define BOOTROM_INSTANCE_MASK GENMASK(31, 16) 51 #define BOOTROM_INSTANCE_SHIFT 16 52 53 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) 54 static void security_init(void) 55 { 56 /* Disable the backup domain write protection */ 57 /* the protection is enable at each reset by hardware */ 58 /* And must be disable by software */ 59 setbits_le32(PWR_CR1, PWR_CR1_DBP); 60 61 while (!(readl(PWR_CR1) & PWR_CR1_DBP)) 62 ; 63 64 /* If RTC clock isn't enable so this is a cold boot then we need 65 * to reset the backup domain 66 */ 67 if (!(readl(RCC_BDCR) & RCC_BDCR_RTCSRC)) { 68 setbits_le32(RCC_BDCR, RCC_BDCR_VSWRST); 69 while (!(readl(RCC_BDCR) & RCC_BDCR_VSWRST)) 70 ; 71 clrbits_le32(RCC_BDCR, RCC_BDCR_VSWRST); 72 } 73 74 /* allow non secure access in Write/Read for all peripheral */ 75 writel(GENMASK(25, 0), ETZPC_DECPROT0); 76 77 /* Open SYSRAM for no secure access */ 78 writel(0x0, ETZPC_TZMA1_SIZE); 79 80 /* enable TZC1 TZC2 clock */ 81 writel(BIT(11) | BIT(12), RCC_MP_APB5ENSETR); 82 83 /* Region 0 set to no access by default */ 84 /* bit 0 / 16 => nsaid0 read/write Enable 85 * bit 1 / 17 => nsaid1 read/write Enable 86 * ... 87 * bit 15 / 31 => nsaid15 read/write Enable 88 */ 89 writel(0xFFFFFFFF, TZC_REGION_ID_ACCESS0); 90 /* bit 30 / 31 => Secure Global Enable : write/read */ 91 /* bit 0 / 1 => Region Enable for filter 0/1 */ 92 writel(BIT(0) | BIT(1) | BIT(30) | BIT(31), TZC_REGION_ATTRIBUTE0); 93 94 /* Enable Filter 0 and 1 */ 95 setbits_le32(TZC_GATE_KEEPER, BIT(0) | BIT(1)); 96 97 /* RCC trust zone deactivated */ 98 writel(0x0, RCC_TZCR); 99 100 /* TAMP: deactivate the internal tamper 101 * Bit 23 ITAMP8E: monotonic counter overflow 102 * Bit 20 ITAMP5E: RTC calendar overflow 103 * Bit 19 ITAMP4E: HSE monitoring 104 * Bit 18 ITAMP3E: LSE monitoring 105 * Bit 16 ITAMP1E: RTC power domain supply monitoring 106 */ 107 writel(0x0, TAMP_CR1); 108 } 109 110 /* 111 * Debug init 112 */ 113 static void dbgmcu_init(void) 114 { 115 setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN); 116 117 /* Freeze IWDG2 if Cortex-A7 is in debug mode */ 118 setbits_le32(DBGMCU_APB4FZ1, DBGMCU_APB4FZ1_IWDG2); 119 } 120 #endif /* !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) */ 121 122 static u32 get_bootmode(void) 123 { 124 u32 boot_mode; 125 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) 126 u32 bootrom_itf = readl(BOOTROM_PARAM_ADDR); 127 u32 bootrom_device, bootrom_instance; 128 129 bootrom_device = 130 (bootrom_itf & BOOTROM_MODE_MASK) >> BOOTROM_MODE_SHIFT; 131 bootrom_instance = 132 (bootrom_itf & BOOTROM_INSTANCE_MASK) >> BOOTROM_INSTANCE_SHIFT; 133 boot_mode = 134 ((bootrom_device << BOOT_TYPE_SHIFT) & BOOT_TYPE_MASK) | 135 ((bootrom_instance << BOOT_INSTANCE_SHIFT) & 136 BOOT_INSTANCE_MASK); 137 138 /* save the boot mode in TAMP backup register */ 139 clrsetbits_le32(TAMP_BOOT_CONTEXT, 140 TAMP_BOOT_MODE_MASK, 141 boot_mode << TAMP_BOOT_MODE_SHIFT); 142 #else 143 /* read TAMP backup register */ 144 boot_mode = (readl(TAMP_BOOT_CONTEXT) & TAMP_BOOT_MODE_MASK) >> 145 TAMP_BOOT_MODE_SHIFT; 146 #endif 147 return boot_mode; 148 } 149 150 /* 151 * Early system init 152 */ 153 int arch_cpu_init(void) 154 { 155 /* early armv7 timer init: needed for polling */ 156 timer_init(); 157 158 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) 159 dbgmcu_init(); 160 161 security_init(); 162 #endif 163 /* get bootmode from BootRom context: saved in TAMP register */ 164 get_bootmode(); 165 166 return 0; 167 } 168 169 void enable_caches(void) 170 { 171 /* Enable D-cache. I-cache is already enabled in start.S */ 172 dcache_enable(); 173 } 174 175 static u32 read_idc(void) 176 { 177 setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN); 178 179 return readl(DBGMCU_IDC); 180 } 181 182 u32 get_cpu_rev(void) 183 { 184 return (read_idc() & DBGMCU_IDC_REV_ID_MASK) >> DBGMCU_IDC_REV_ID_SHIFT; 185 } 186 187 u32 get_cpu_type(void) 188 { 189 return (read_idc() & DBGMCU_IDC_DEV_ID_MASK) >> DBGMCU_IDC_DEV_ID_SHIFT; 190 } 191 192 #if defined(CONFIG_DISPLAY_CPUINFO) 193 int print_cpuinfo(void) 194 { 195 char *cpu_s, *cpu_r; 196 197 switch (get_cpu_type()) { 198 case CPU_STMP32MP15x: 199 cpu_s = "15x"; 200 break; 201 default: 202 cpu_s = "?"; 203 break; 204 } 205 206 switch (get_cpu_rev()) { 207 case CPU_REVA: 208 cpu_r = "A"; 209 break; 210 case CPU_REVB: 211 cpu_r = "B"; 212 break; 213 default: 214 cpu_r = "?"; 215 break; 216 } 217 218 printf("CPU: STM32MP%s.%s\n", cpu_s, cpu_r); 219 220 return 0; 221 } 222 #endif /* CONFIG_DISPLAY_CPUINFO */ 223 224 static void setup_boot_mode(void) 225 { 226 char cmd[60]; 227 u32 boot_ctx = readl(TAMP_BOOT_CONTEXT); 228 u32 boot_mode = 229 (boot_ctx & TAMP_BOOT_MODE_MASK) >> TAMP_BOOT_MODE_SHIFT; 230 int instance = (boot_mode & TAMP_BOOT_INSTANCE_MASK) - 1; 231 232 pr_debug("%s: boot_ctx=0x%x => boot_mode=%x, instance=%d\n", 233 __func__, boot_ctx, boot_mode, instance); 234 235 switch (boot_mode & TAMP_BOOT_DEVICE_MASK) { 236 case BOOT_SERIAL_UART: 237 sprintf(cmd, "%d", instance); 238 env_set("boot_device", "uart"); 239 env_set("boot_instance", cmd); 240 break; 241 case BOOT_SERIAL_USB: 242 env_set("boot_device", "usb"); 243 env_set("boot_instance", "0"); 244 break; 245 case BOOT_FLASH_SD: 246 case BOOT_FLASH_EMMC: 247 sprintf(cmd, "%d", instance); 248 env_set("boot_device", "mmc"); 249 env_set("boot_instance", cmd); 250 break; 251 case BOOT_FLASH_NAND: 252 env_set("boot_device", "nand"); 253 env_set("boot_instance", "0"); 254 break; 255 case BOOT_FLASH_NOR: 256 env_set("boot_device", "nor"); 257 env_set("boot_instance", "0"); 258 break; 259 default: 260 pr_debug("unexpected boot mode = %x\n", boot_mode); 261 break; 262 } 263 } 264 265 int arch_misc_init(void) 266 { 267 setup_boot_mode(); 268 269 return 0; 270 } 271