1 /* 2 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause 5 */ 6 #include <common.h> 7 #include <clk.h> 8 #include <asm/io.h> 9 #include <asm/arch/stm32.h> 10 11 void enable_caches(void) 12 { 13 /* Enable D-cache. I-cache is already enabled in start.S */ 14 dcache_enable(); 15 } 16 17 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) 18 /********************************************** 19 * Security init 20 *********************************************/ 21 #define ETZPC_TZMA1_SIZE (STM32_ETZPC_BASE + 0x04) 22 #define ETZPC_DECPROT0 (STM32_ETZPC_BASE + 0x10) 23 24 #define TZC_GATE_KEEPER (STM32_TZC_BASE + 0x008) 25 #define TZC_REGION_ATTRIBUTE0 (STM32_TZC_BASE + 0x110) 26 #define TZC_REGION_ID_ACCESS0 (STM32_TZC_BASE + 0x114) 27 28 #define TAMP_CR1 (STM32_TAMP_BASE + 0x00) 29 30 #define PWR_CR1 (STM32_PWR_BASE + 0x00) 31 #define PWR_CR1_DBP BIT(8) 32 33 #define RCC_TZCR (STM32_RCC_BASE + 0x00) 34 #define RCC_BDCR (STM32_RCC_BASE + 0x0140) 35 #define RCC_MP_APB5ENSETR (STM32_RCC_BASE + 0x0208) 36 37 #define RCC_BDCR_VSWRST BIT(31) 38 #define RCC_BDCR_RTCSRC GENMASK(17, 16) 39 40 static void security_init(void) 41 { 42 /* Disable the backup domain write protection */ 43 /* the protection is enable at each reset by hardware */ 44 /* And must be disable by software */ 45 setbits_le32(PWR_CR1, PWR_CR1_DBP); 46 47 while (!(readl(PWR_CR1) & PWR_CR1_DBP)) 48 ; 49 50 /* If RTC clock isn't enable so this is a cold boot then we need 51 * to reset the backup domain 52 */ 53 if (!(readl(RCC_BDCR) & RCC_BDCR_RTCSRC)) { 54 setbits_le32(RCC_BDCR, RCC_BDCR_VSWRST); 55 while (!(readl(RCC_BDCR) & RCC_BDCR_VSWRST)) 56 ; 57 clrbits_le32(RCC_BDCR, RCC_BDCR_VSWRST); 58 } 59 60 /* allow non secure access in Write/Read for all peripheral */ 61 writel(GENMASK(25, 0), ETZPC_DECPROT0); 62 63 /* Open SYSRAM for no secure access */ 64 writel(0x0, ETZPC_TZMA1_SIZE); 65 66 /* enable TZC1 TZC2 clock */ 67 writel(BIT(11) | BIT(12), RCC_MP_APB5ENSETR); 68 69 /* Region 0 set to no access by default */ 70 /* bit 0 / 16 => nsaid0 read/write Enable 71 * bit 1 / 17 => nsaid1 read/write Enable 72 * ... 73 * bit 15 / 31 => nsaid15 read/write Enable 74 */ 75 writel(0xFFFFFFFF, TZC_REGION_ID_ACCESS0); 76 /* bit 30 / 31 => Secure Global Enable : write/read */ 77 /* bit 0 / 1 => Region Enable for filter 0/1 */ 78 writel(BIT(0) | BIT(1) | BIT(30) | BIT(31), TZC_REGION_ATTRIBUTE0); 79 80 /* Enable Filter 0 and 1 */ 81 setbits_le32(TZC_GATE_KEEPER, BIT(0) | BIT(1)); 82 83 /* RCC trust zone deactivated */ 84 writel(0x0, RCC_TZCR); 85 86 /* TAMP: deactivate the internal tamper 87 * Bit 23 ITAMP8E: monotonic counter overflow 88 * Bit 20 ITAMP5E: RTC calendar overflow 89 * Bit 19 ITAMP4E: HSE monitoring 90 * Bit 18 ITAMP3E: LSE monitoring 91 * Bit 16 ITAMP1E: RTC power domain supply monitoring 92 */ 93 writel(0x0, TAMP_CR1); 94 } 95 96 /********************************************** 97 * Debug init 98 *********************************************/ 99 #define RCC_DBGCFGR (STM32_RCC_BASE + 0x080C) 100 #define RCC_DBGCFGR_DBGCKEN BIT(8) 101 102 #define DBGMCU_APB4FZ1 (STM32_DBGMCU_BASE + 0x2C) 103 #define DBGMCU_APB4FZ1_IWDG2 BIT(2) 104 105 static void dbgmcu_init(void) 106 { 107 setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN); 108 109 /* Freeze IWDG2 if Cortex-A7 is in debug mode */ 110 setbits_le32(DBGMCU_APB4FZ1, DBGMCU_APB4FZ1_IWDG2); 111 } 112 #endif /* !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) */ 113 114 int arch_cpu_init(void) 115 { 116 /* early armv7 timer init: needed for polling */ 117 timer_init(); 118 119 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) 120 dbgmcu_init(); 121 122 security_init(); 123 #endif 124 125 return 0; 126 } 127 128 #if defined(CONFIG_DISPLAY_CPUINFO) 129 int print_cpuinfo(void) 130 { 131 printf("CPU: STM32MP15x\n"); 132 133 return 0; 134 } 135 #endif /* CONFIG_DISPLAY_CPUINFO */ 136 137 void reset_cpu(ulong addr) 138 { 139 } 140