1*c729fb25SPatrice Chotard /* 2*c729fb25SPatrice Chotard * Copyright (C) 2017, STMicroelectronics - All Rights Reserved 3*c729fb25SPatrice Chotard * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics. 4*c729fb25SPatrice Chotard * 5*c729fb25SPatrice Chotard * SPDX-License-Identifier: GPL-2.0+ 6*c729fb25SPatrice Chotard */ 7*c729fb25SPatrice Chotard 8*c729fb25SPatrice Chotard #include <common.h> 9*c729fb25SPatrice Chotard #include <asm/io.h> 10*c729fb25SPatrice Chotard #include <asm/armv7m_mpu.h> 11*c729fb25SPatrice Chotard 12*c729fb25SPatrice Chotard int arch_cpu_init(void) 13*c729fb25SPatrice Chotard { 14*c729fb25SPatrice Chotard int i; 15*c729fb25SPatrice Chotard 16*c729fb25SPatrice Chotard struct mpu_region_config stm32_region_config[] = { 17*c729fb25SPatrice Chotard /* 18*c729fb25SPatrice Chotard * Make all 4GB cacheable & executable. We are overriding it 19*c729fb25SPatrice Chotard * with next region for any requirement. e.g. below region1, 20*c729fb25SPatrice Chotard * 2 etc. 21*c729fb25SPatrice Chotard * In other words, the area not coming in following 22*c729fb25SPatrice Chotard * regions configuration is the one configured here in region_0 23*c729fb25SPatrice Chotard * (cacheable & executable). 24*c729fb25SPatrice Chotard */ 25*c729fb25SPatrice Chotard { 0x00000000, REGION_0, XN_DIS, PRIV_RW_USR_RW, 26*c729fb25SPatrice Chotard O_I_WB_RD_WR_ALLOC, REGION_4GB }, 27*c729fb25SPatrice Chotard 28*c729fb25SPatrice Chotard /* armv7m code area */ 29*c729fb25SPatrice Chotard { 0x00000000, REGION_1, XN_DIS, PRIV_RW_USR_RW, 30*c729fb25SPatrice Chotard STRONG_ORDER, REGION_512MB }, 31*c729fb25SPatrice Chotard 32*c729fb25SPatrice Chotard /* Device area : Not executable */ 33*c729fb25SPatrice Chotard { 0x40000000, REGION_2, XN_EN, PRIV_RW_USR_RW, 34*c729fb25SPatrice Chotard DEVICE_NON_SHARED, REGION_512MB }, 35*c729fb25SPatrice Chotard 36*c729fb25SPatrice Chotard /* 37*c729fb25SPatrice Chotard * Armv7m fixed configuration: strongly ordered & not 38*c729fb25SPatrice Chotard * executable, not cacheable 39*c729fb25SPatrice Chotard */ 40*c729fb25SPatrice Chotard { 0xE0000000, REGION_3, XN_EN, PRIV_RW_USR_RW, 41*c729fb25SPatrice Chotard STRONG_ORDER, REGION_512MB }, 42*c729fb25SPatrice Chotard 43*c729fb25SPatrice Chotard #if !defined(CONFIG_STM32H7) 44*c729fb25SPatrice Chotard /* Device area : Not executable */ 45*c729fb25SPatrice Chotard { 0xA0000000, REGION_4, XN_EN, PRIV_RW_USR_RW, 46*c729fb25SPatrice Chotard DEVICE_NON_SHARED, REGION_512MB }, 47*c729fb25SPatrice Chotard #endif 48*c729fb25SPatrice Chotard }; 49*c729fb25SPatrice Chotard 50*c729fb25SPatrice Chotard disable_mpu(); 51*c729fb25SPatrice Chotard for (i = 0; i < ARRAY_SIZE(stm32_region_config); i++) 52*c729fb25SPatrice Chotard mpu_config(&stm32_region_config[i]); 53*c729fb25SPatrice Chotard enable_mpu(); 54*c729fb25SPatrice Chotard 55*c729fb25SPatrice Chotard return 0; 56*c729fb25SPatrice Chotard } 57