1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+ 2c729fb25SPatrice Chotard /* 3c729fb25SPatrice Chotard * Copyright (C) 2017, STMicroelectronics - All Rights Reserved 4c729fb25SPatrice Chotard * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics. 5c729fb25SPatrice Chotard */ 6c729fb25SPatrice Chotard 7c729fb25SPatrice Chotard #include <common.h> 8c729fb25SPatrice Chotard #include <asm/io.h> 9c729fb25SPatrice Chotard #include <asm/armv7m_mpu.h> 10c729fb25SPatrice Chotard 11c729fb25SPatrice Chotard int arch_cpu_init(void) 12c729fb25SPatrice Chotard { 13c729fb25SPatrice Chotard int i; 14c729fb25SPatrice Chotard 15c729fb25SPatrice Chotard struct mpu_region_config stm32_region_config[] = { 16c729fb25SPatrice Chotard /* 17f5bd13edSPatrice Chotard * Make SDRAM area cacheable & executable. 18c729fb25SPatrice Chotard */ 19f5bd13edSPatrice Chotard #if defined(CONFIG_STM32F4) 20c729fb25SPatrice Chotard { 0x00000000, REGION_0, XN_DIS, PRIV_RW_USR_RW, 21f5bd13edSPatrice Chotard O_I_WB_RD_WR_ALLOC, REGION_16MB }, 22f5bd13edSPatrice Chotard #endif 23c729fb25SPatrice Chotard 24f5bd13edSPatrice Chotard #if defined(CONFIG_STM32F7) 25f5bd13edSPatrice Chotard { 0xC0000000, REGION_0, XN_DIS, PRIV_RW_USR_RW, 26f5bd13edSPatrice Chotard O_I_WB_RD_WR_ALLOC, REGION_16MB }, 27f5bd13edSPatrice Chotard #endif 28c729fb25SPatrice Chotard 29f5bd13edSPatrice Chotard #if defined(CONFIG_STM32H7) 30f5bd13edSPatrice Chotard { 0xD0000000, REGION_0, XN_DIS, PRIV_RW_USR_RW, 31f5bd13edSPatrice Chotard O_I_WB_RD_WR_ALLOC, REGION_32MB }, 32c729fb25SPatrice Chotard #endif 33c729fb25SPatrice Chotard }; 34c729fb25SPatrice Chotard 35c729fb25SPatrice Chotard disable_mpu(); 36c729fb25SPatrice Chotard for (i = 0; i < ARRAY_SIZE(stm32_region_config); i++) 37c729fb25SPatrice Chotard mpu_config(&stm32_region_config[i]); 38c729fb25SPatrice Chotard enable_mpu(); 39c729fb25SPatrice Chotard 40c729fb25SPatrice Chotard return 0; 41c729fb25SPatrice Chotard } 42