1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright (C) 2015 Marek Vasut <marex@denx.de>
4  */
5 
6 #include <common.h>
7 #include <errno.h>
8 #include <asm/arch/sdram.h>
9 
10 /* Board-specific header. */
11 #include <qts/sdram_config.h>
12 
13 static const struct socfpga_sdram_config sdram_config = {
14 	.ctrl_cfg =
15 		(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE <<
16 			SDR_CTRLGRP_CTRLCFG_MEMTYPE_LSB)		|
17 		(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL <<
18 			SDR_CTRLGRP_CTRLCFG_MEMBL_LSB)			|
19 		(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER <<
20 			SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB)		|
21 		(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN <<
22 			SDR_CTRLGRP_CTRLCFG_ECCEN_LSB)			|
23 		(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN <<
24 			SDR_CTRLGRP_CTRLCFG_ECCCORREN_LSB)		|
25 		(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN <<
26 			SDR_CTRLGRP_CTRLCFG_REORDEREN_LSB)		|
27 		(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT <<
28 			SDR_CTRLGRP_CTRLCFG_STARVELIMIT_LSB)		|
29 		(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN <<
30 			SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB)		|
31 		(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS <<
32 			SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB),
33 	.dram_timing1 =
34 		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL <<
35 			SDR_CTRLGRP_DRAMTIMING1_TCWL_LSB)		|
36 		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL <<
37 			SDR_CTRLGRP_DRAMTIMING1_TAL_LSB)		|
38 		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL <<
39 			SDR_CTRLGRP_DRAMTIMING1_TCL_LSB)		|
40 		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD <<
41 			SDR_CTRLGRP_DRAMTIMING1_TRRD_LSB)		|
42 		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW <<
43 			SDR_CTRLGRP_DRAMTIMING1_TFAW_LSB)		|
44 		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC <<
45 			SDR_CTRLGRP_DRAMTIMING1_TRFC_LSB),
46 	.dram_timing2 =
47 		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI <<
48 			SDR_CTRLGRP_DRAMTIMING2_TREFI_LSB)		|
49 		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD <<
50 			SDR_CTRLGRP_DRAMTIMING2_TRCD_LSB)		|
51 		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP <<
52 			SDR_CTRLGRP_DRAMTIMING2_TRP_LSB)		|
53 		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR <<
54 			SDR_CTRLGRP_DRAMTIMING2_TWR_LSB)		|
55 		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR <<
56 			SDR_CTRLGRP_DRAMTIMING2_TWTR_LSB),
57 	.dram_timing3 =
58 		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP <<
59 			SDR_CTRLGRP_DRAMTIMING3_TRTP_LSB)		|
60 		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS <<
61 			SDR_CTRLGRP_DRAMTIMING3_TRAS_LSB)		|
62 		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC <<
63 			SDR_CTRLGRP_DRAMTIMING3_TRC_LSB)		|
64 		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD <<
65 			SDR_CTRLGRP_DRAMTIMING3_TMRD_LSB)		|
66 		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD <<
67 			SDR_CTRLGRP_DRAMTIMING3_TCCD_LSB),
68 	.dram_timing4 =
69 		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT <<
70 			SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_LSB)	|
71 		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT <<
72 			SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_LSB),
73 	.lowpwr_timing =
74 		(CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES <<
75 			SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_LSB)	|
76 		(CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES <<
77 			SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_LSB),
78 	.dram_odt =
79 		(CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ <<
80 			SDR_CTRLGRP_DRAMODT_READ_LSB)			|
81 		(CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE <<
82 			SDR_CTRLGRP_DRAMODT_WRITE_LSB),
83 	.extratime1 =
84 	(CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR <<
85 			SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_LSB)		|
86 	(CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC <<
87 			SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_BC_LSB)		|
88 (CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP <<
89 			SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_DIFF_LSB),
90 	.dram_addrw =
91 		(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS <<
92 			SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB)		|
93 		(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS <<
94 			SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB)		|
95 		(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS <<
96 			SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB)		|
97 		((CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS - 1) <<
98 			SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB),
99 	.dram_if_width =
100 		(CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH <<
101 			SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_LSB),
102 	.dram_dev_width =
103 		(CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH <<
104 			SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_LSB),
105 	.dram_intr =
106 		(CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN <<
107 			SDR_CTRLGRP_DRAMINTR_INTREN_LSB),
108 	.lowpwr_eq =
109 		(CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK <<
110 			SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_LSB),
111 	.static_cfg =
112 		(CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL <<
113 			SDR_CTRLGRP_STATICCFG_MEMBL_LSB)		|
114 		(CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA <<
115 			SDR_CTRLGRP_STATICCFG_USEECCASDATA_LSB),
116 	.ctrl_width =
117 		(CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH <<
118 			SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_LSB),
119 	.cport_width =
120 		(CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH <<
121 			SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_LSB),
122 	.cport_wmap =
123 		(CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP <<
124 			SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_LSB),
125 	.cport_rmap =
126 		(CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP <<
127 			SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_LSB),
128 	.rfifo_cmap =
129 		(CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP <<
130 			SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_LSB),
131 	.wfifo_cmap =
132 		(CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP <<
133 			SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_LSB),
134 	.cport_rdwr =
135 		(CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR <<
136 			SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_LSB),
137 	.port_cfg =
138 		(CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN <<
139 			SDR_CTRLGRP_PORTCFG_AUTOPCHEN_LSB),
140 	.fpgaport_rst = CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST,
141 	.fifo_cfg =
142 		(CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE <<
143 			SDR_CTRLGRP_FIFOCFG_SYNCMODE_LSB)		|
144 		(CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC <<
145 			SDR_CTRLGRP_FIFOCFG_INCSYNC_LSB),
146 	.mp_priority =
147 		(CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY <<
148 			SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_LSB),
149 	.mp_weight0 =
150 		(CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 <<
151 			SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_LSB),
152 	.mp_weight1 =
153 		(CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 <<
154 			SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_LSB) |
155 		(CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 <<
156 			SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_LSB),
157 	.mp_weight2 =
158 		(CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 <<
159 			SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_LSB),
160 	.mp_weight3 =
161 		(CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 <<
162 			SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_LSB),
163 	.mp_pacing0 =
164 		(CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 <<
165 			SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_LSB),
166 	.mp_pacing1 =
167 		(CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 <<
168 			SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_LSB) |
169 		(CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 <<
170 			SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_LSB),
171 	.mp_pacing2 =
172 		(CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 <<
173 			SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_LSB),
174 	.mp_pacing3 =
175 		(CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 <<
176 			SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_LSB),
177 	.mp_threshold0 =
178 		(CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 <<
179 			SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_LSB),
180 	.mp_threshold1 =
181 		(CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 <<
182 			SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_LSB),
183 	.mp_threshold2 =
184 		(CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 <<
185 			SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_LSB),
186 	.phy_ctrl0 = CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0,
187 };
188 
189 static const struct socfpga_sdram_rw_mgr_config rw_mgr_config = {
190 	.activate_0_and_1		= RW_MGR_ACTIVATE_0_AND_1,
191 	.activate_0_and_1_wait1		= RW_MGR_ACTIVATE_0_AND_1_WAIT1,
192 	.activate_0_and_1_wait2		= RW_MGR_ACTIVATE_0_AND_1_WAIT2,
193 	.activate_1			= RW_MGR_ACTIVATE_1,
194 	.clear_dqs_enable		= RW_MGR_CLEAR_DQS_ENABLE,
195 	.guaranteed_read		= RW_MGR_GUARANTEED_READ,
196 	.guaranteed_read_cont		= RW_MGR_GUARANTEED_READ_CONT,
197 	.guaranteed_write		= RW_MGR_GUARANTEED_WRITE,
198 	.guaranteed_write_wait0		= RW_MGR_GUARANTEED_WRITE_WAIT0,
199 	.guaranteed_write_wait1		= RW_MGR_GUARANTEED_WRITE_WAIT1,
200 	.guaranteed_write_wait2		= RW_MGR_GUARANTEED_WRITE_WAIT2,
201 	.guaranteed_write_wait3		= RW_MGR_GUARANTEED_WRITE_WAIT3,
202 	.idle				= RW_MGR_IDLE,
203 	.idle_loop1			= RW_MGR_IDLE_LOOP1,
204 	.idle_loop2			= RW_MGR_IDLE_LOOP2,
205 	.init_reset_0_cke_0		= RW_MGR_INIT_RESET_0_CKE_0,
206 	.init_reset_1_cke_0		= RW_MGR_INIT_RESET_1_CKE_0,
207 	.lfsr_wr_rd_bank_0		= RW_MGR_LFSR_WR_RD_BANK_0,
208 	.lfsr_wr_rd_bank_0_data		= RW_MGR_LFSR_WR_RD_BANK_0_DATA,
209 	.lfsr_wr_rd_bank_0_dqs		= RW_MGR_LFSR_WR_RD_BANK_0_DQS,
210 	.lfsr_wr_rd_bank_0_nop		= RW_MGR_LFSR_WR_RD_BANK_0_NOP,
211 	.lfsr_wr_rd_bank_0_wait		= RW_MGR_LFSR_WR_RD_BANK_0_WAIT,
212 	.lfsr_wr_rd_bank_0_wl_1		= RW_MGR_LFSR_WR_RD_BANK_0_WL_1,
213 	.lfsr_wr_rd_dm_bank_0		= RW_MGR_LFSR_WR_RD_DM_BANK_0,
214 	.lfsr_wr_rd_dm_bank_0_data	= RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA,
215 	.lfsr_wr_rd_dm_bank_0_dqs	= RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS,
216 	.lfsr_wr_rd_dm_bank_0_nop	= RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP,
217 	.lfsr_wr_rd_dm_bank_0_wait	= RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT,
218 	.lfsr_wr_rd_dm_bank_0_wl_1	= RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1,
219 	.mrs0_dll_reset			= RW_MGR_MRS0_DLL_RESET,
220 	.mrs0_dll_reset_mirr		= RW_MGR_MRS0_DLL_RESET_MIRR,
221 	.mrs0_user			= RW_MGR_MRS0_USER,
222 	.mrs0_user_mirr			= RW_MGR_MRS0_USER_MIRR,
223 	.mrs1				= RW_MGR_MRS1,
224 	.mrs1_mirr			= RW_MGR_MRS1_MIRR,
225 	.mrs2				= RW_MGR_MRS2,
226 	.mrs2_mirr			= RW_MGR_MRS2_MIRR,
227 	.mrs3				= RW_MGR_MRS3,
228 	.mrs3_mirr			= RW_MGR_MRS3_MIRR,
229 	.precharge_all			= RW_MGR_PRECHARGE_ALL,
230 	.read_b2b			= RW_MGR_READ_B2B,
231 	.read_b2b_wait1			= RW_MGR_READ_B2B_WAIT1,
232 	.read_b2b_wait2			= RW_MGR_READ_B2B_WAIT2,
233 	.refresh_all			= RW_MGR_REFRESH_ALL,
234 	.rreturn			= RW_MGR_RETURN,
235 	.sgle_read			= RW_MGR_SGLE_READ,
236 	.zqcl				= RW_MGR_ZQCL,
237 
238 	.true_mem_data_mask_width	= RW_MGR_TRUE_MEM_DATA_MASK_WIDTH,
239 	.mem_address_mirroring		= RW_MGR_MEM_ADDRESS_MIRRORING,
240 	.mem_data_mask_width		= RW_MGR_MEM_DATA_MASK_WIDTH,
241 	.mem_data_width			= RW_MGR_MEM_DATA_WIDTH,
242 	.mem_dq_per_read_dqs		= RW_MGR_MEM_DQ_PER_READ_DQS,
243 	.mem_dq_per_write_dqs		= RW_MGR_MEM_DQ_PER_WRITE_DQS,
244 	.mem_if_read_dqs_width		= RW_MGR_MEM_IF_READ_DQS_WIDTH,
245 	.mem_if_write_dqs_width		= RW_MGR_MEM_IF_WRITE_DQS_WIDTH,
246 	.mem_number_of_cs_per_dimm	= RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM,
247 	.mem_number_of_ranks		= RW_MGR_MEM_NUMBER_OF_RANKS,
248 	.mem_virtual_groups_per_read_dqs =
249 		RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS,
250 	.mem_virtual_groups_per_write_dqs =
251 		RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS,
252 };
253 
254 struct socfpga_sdram_io_config io_config = {
255 	.delay_per_dchain_tap		= IO_DELAY_PER_DCHAIN_TAP,
256 	.delay_per_dqs_en_dchain_tap	= IO_DELAY_PER_DQS_EN_DCHAIN_TAP,
257 	.delay_per_opa_tap		= IO_DELAY_PER_OPA_TAP,
258 	.dll_chain_length		= IO_DLL_CHAIN_LENGTH,
259 	.dqdqs_out_phase_max		= IO_DQDQS_OUT_PHASE_MAX,
260 	.dqs_en_delay_max		= IO_DQS_EN_DELAY_MAX,
261 	.dqs_en_delay_offset		= IO_DQS_EN_DELAY_OFFSET,
262 	.dqs_en_phase_max		= IO_DQS_EN_PHASE_MAX,
263 	.dqs_in_delay_max		= IO_DQS_IN_DELAY_MAX,
264 	.dqs_in_reserve			= IO_DQS_IN_RESERVE,
265 	.dqs_out_reserve		= IO_DQS_OUT_RESERVE,
266 	.io_in_delay_max		= IO_IO_IN_DELAY_MAX,
267 	.io_out1_delay_max		= IO_IO_OUT1_DELAY_MAX,
268 	.io_out2_delay_max		= IO_IO_OUT2_DELAY_MAX,
269 	.shift_dqs_en_when_shift_dqs	= IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS,
270 };
271 
272 struct socfpga_sdram_misc_config misc_config = {
273 	.afi_rate_ratio			= AFI_RATE_RATIO,
274 	.calib_lfifo_offset		= CALIB_LFIFO_OFFSET,
275 	.calib_vfifo_offset		= CALIB_VFIFO_OFFSET,
276 	.enable_super_quick_calibration	= ENABLE_SUPER_QUICK_CALIBRATION,
277 	.max_latency_count_width	= MAX_LATENCY_COUNT_WIDTH,
278 	.read_valid_fifo_size		= READ_VALID_FIFO_SIZE,
279 	.reg_file_init_seq_signature	= REG_FILE_INIT_SEQ_SIGNATURE,
280 	.tinit_cntr0_val		= TINIT_CNTR0_VAL,
281 	.tinit_cntr1_val		= TINIT_CNTR1_VAL,
282 	.tinit_cntr2_val		= TINIT_CNTR2_VAL,
283 	.treset_cntr0_val		= TRESET_CNTR0_VAL,
284 	.treset_cntr1_val		= TRESET_CNTR1_VAL,
285 	.treset_cntr2_val		= TRESET_CNTR2_VAL,
286 };
287 
288 const struct socfpga_sdram_config *socfpga_get_sdram_config(void)
289 {
290 	return &sdram_config;
291 }
292 
293 void socfpga_get_seq_ac_init(const u32 **init, unsigned int *nelem)
294 {
295 	*init = ac_rom_init;
296 	*nelem = ARRAY_SIZE(ac_rom_init);
297 }
298 
299 void socfpga_get_seq_inst_init(const u32 **init, unsigned int *nelem)
300 {
301 	*init = inst_rom_init;
302 	*nelem = ARRAY_SIZE(inst_rom_init);
303 }
304 
305 const struct socfpga_sdram_rw_mgr_config *socfpga_get_sdram_rwmgr_config(void)
306 {
307 	return &rw_mgr_config;
308 }
309 
310 const struct socfpga_sdram_io_config *socfpga_get_sdram_io_config(void)
311 {
312 	return &io_config;
313 }
314 
315 const struct socfpga_sdram_misc_config *socfpga_get_sdram_misc_config(void)
316 {
317 	return &misc_config;
318 }
319