1*508791a0SLey Foon Tan // SPDX-License-Identifier: GPL-2.0 2*508791a0SLey Foon Tan /* 3*508791a0SLey Foon Tan * Copyright (C) 2016-2018 Intel Corporation <www.intel.com> 4*508791a0SLey Foon Tan * 5*508791a0SLey Foon Tan */ 6*508791a0SLey Foon Tan 7*508791a0SLey Foon Tan #include <common.h> 8*508791a0SLey Foon Tan #include <asm/arch/clock_manager.h> 9*508791a0SLey Foon Tan #include <asm/io.h> 10*508791a0SLey Foon Tan #include <asm/arch/handoff_s10.h> 11*508791a0SLey Foon Tan #include <asm/arch/system_manager.h> 12*508791a0SLey Foon Tan 13*508791a0SLey Foon Tan static const struct socfpga_system_manager *sysmgr_regs = 14*508791a0SLey Foon Tan (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; 15*508791a0SLey Foon Tan cm_get_default_config(void)16*508791a0SLey Foon Tanconst struct cm_config * const cm_get_default_config(void) 17*508791a0SLey Foon Tan { 18*508791a0SLey Foon Tan struct cm_config *cm_handoff_cfg = (struct cm_config *) 19*508791a0SLey Foon Tan (S10_HANDOFF_CLOCK + S10_HANDOFF_OFFSET_DATA); 20*508791a0SLey Foon Tan u32 *conversion = (u32 *)cm_handoff_cfg; 21*508791a0SLey Foon Tan u32 i; 22*508791a0SLey Foon Tan u32 handoff_clk = readl(S10_HANDOFF_CLOCK); 23*508791a0SLey Foon Tan 24*508791a0SLey Foon Tan if (swab32(handoff_clk) == S10_HANDOFF_MAGIC_CLOCK) { 25*508791a0SLey Foon Tan writel(swab32(handoff_clk), S10_HANDOFF_CLOCK); 26*508791a0SLey Foon Tan for (i = 0; i < (sizeof(*cm_handoff_cfg) / sizeof(u32)); i++) 27*508791a0SLey Foon Tan conversion[i] = swab32(conversion[i]); 28*508791a0SLey Foon Tan return cm_handoff_cfg; 29*508791a0SLey Foon Tan } else if (handoff_clk == S10_HANDOFF_MAGIC_CLOCK) { 30*508791a0SLey Foon Tan return cm_handoff_cfg; 31*508791a0SLey Foon Tan } 32*508791a0SLey Foon Tan 33*508791a0SLey Foon Tan return NULL; 34*508791a0SLey Foon Tan } 35*508791a0SLey Foon Tan cm_get_osc_clk_hz(void)36*508791a0SLey Foon Tanconst unsigned int cm_get_osc_clk_hz(void) 37*508791a0SLey Foon Tan { 38*508791a0SLey Foon Tan #ifdef CONFIG_SPL_BUILD 39*508791a0SLey Foon Tan u32 clock = readl(S10_HANDOFF_CLOCK_OSC); 40*508791a0SLey Foon Tan 41*508791a0SLey Foon Tan writel(clock, &sysmgr_regs->boot_scratch_cold1); 42*508791a0SLey Foon Tan #endif 43*508791a0SLey Foon Tan return readl(&sysmgr_regs->boot_scratch_cold1); 44*508791a0SLey Foon Tan } 45*508791a0SLey Foon Tan cm_get_intosc_clk_hz(void)46*508791a0SLey Foon Tanconst unsigned int cm_get_intosc_clk_hz(void) 47*508791a0SLey Foon Tan { 48*508791a0SLey Foon Tan return CLKMGR_INTOSC_HZ; 49*508791a0SLey Foon Tan } 50*508791a0SLey Foon Tan cm_get_fpga_clk_hz(void)51*508791a0SLey Foon Tanconst unsigned int cm_get_fpga_clk_hz(void) 52*508791a0SLey Foon Tan { 53*508791a0SLey Foon Tan #ifdef CONFIG_SPL_BUILD 54*508791a0SLey Foon Tan u32 clock = readl(S10_HANDOFF_CLOCK_FPGA); 55*508791a0SLey Foon Tan 56*508791a0SLey Foon Tan writel(clock, &sysmgr_regs->boot_scratch_cold2); 57*508791a0SLey Foon Tan #endif 58*508791a0SLey Foon Tan return readl(&sysmgr_regs->boot_scratch_cold2); 59*508791a0SLey Foon Tan } 60