1 /*
2  * Copyright (C) 2015 Marek Vasut <marex@denx.de>
3  *
4  * SPDX-License-Identifier:    GPL-2.0+
5  */
6 
7 #include <common.h>
8 #include <asm/arch/clock_manager.h>
9 #include <qts/pll_config.h>
10 
11 #define MAIN_VCO_BASE (					\
12 	(CONFIG_HPS_MAINPLLGRP_VCO_DENOM <<		\
13 		CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET) |	\
14 	(CONFIG_HPS_MAINPLLGRP_VCO_NUMER <<		\
15 		CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET)	\
16 	)
17 
18 #define PERI_VCO_BASE (					\
19 	(CONFIG_HPS_PERPLLGRP_VCO_PSRC <<		\
20 		CLKMGR_PERPLLGRP_VCO_PSRC_OFFSET) |	\
21 	(CONFIG_HPS_PERPLLGRP_VCO_DENOM <<		\
22 		CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET) |	\
23 	(CONFIG_HPS_PERPLLGRP_VCO_NUMER <<		\
24 		CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET)	\
25 	)
26 
27 #define SDR_VCO_BASE (					\
28 	(CONFIG_HPS_SDRPLLGRP_VCO_SSRC <<		\
29 		CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET) |	\
30 	(CONFIG_HPS_SDRPLLGRP_VCO_DENOM <<		\
31 		CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET) |	\
32 	(CONFIG_HPS_SDRPLLGRP_VCO_NUMER <<		\
33 		CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET)	\
34 	)
35 
36 static const struct cm_config cm_default_cfg = {
37 	/* main group */
38 	MAIN_VCO_BASE,
39 	(CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT <<
40 		CLKMGR_MAINPLLGRP_MPUCLK_CNT_OFFSET),
41 	(CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT <<
42 		CLKMGR_MAINPLLGRP_MAINCLK_CNT_OFFSET),
43 	(CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT <<
44 		CLKMGR_MAINPLLGRP_DBGATCLK_CNT_OFFSET),
45 	(CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT <<
46 		CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_OFFSET),
47 	(CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT <<
48 		CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET),
49 	(CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT <<
50 		CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_OFFSET),
51 	(CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK <<
52 		CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_OFFSET) |
53 	(CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK <<
54 		CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_OFFSET) |
55 	(CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK <<
56 		CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_OFFSET) |
57 	(CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK <<
58 		CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET),
59 	(CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK <<
60 		CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_OFFSET) |
61 	(CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK <<
62 		CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_OFFSET),
63 	(CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK <<
64 		CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_OFFSET),
65 	(CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP <<
66 		CLKMGR_MAINPLLGRP_L4SRC_L4MP_OFFSET) |
67 	(CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP <<
68 		CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET),
69 
70 	/* peripheral group */
71 	PERI_VCO_BASE,
72 	(CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT <<
73 		CLKMGR_PERPLLGRP_EMAC0CLK_CNT_OFFSET),
74 	(CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT <<
75 		CLKMGR_PERPLLGRP_EMAC1CLK_CNT_OFFSET),
76 	(CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT <<
77 		CLKMGR_PERPLLGRP_PERQSPICLK_CNT_OFFSET),
78 	(CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT <<
79 		CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET),
80 	(CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT <<
81 		CLKMGR_PERPLLGRP_PERBASECLK_CNT_OFFSET),
82 	(CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT <<
83 		CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_OFFSET),
84 	(CONFIG_HPS_PERPLLGRP_DIV_USBCLK <<
85 		CLKMGR_PERPLLGRP_DIV_USBCLK_OFFSET) |
86 	(CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK <<
87 		CLKMGR_PERPLLGRP_DIV_SPIMCLK_OFFSET) |
88 	(CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK <<
89 		CLKMGR_PERPLLGRP_DIV_CAN0CLK_OFFSET) |
90 	(CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK <<
91 		CLKMGR_PERPLLGRP_DIV_CAN1CLK_OFFSET),
92 	(CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK <<
93 		CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_OFFSET),
94 	(CONFIG_HPS_PERPLLGRP_SRC_QSPI <<
95 		CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET) |
96 	(CONFIG_HPS_PERPLLGRP_SRC_NAND <<
97 		CLKMGR_PERPLLGRP_SRC_NAND_OFFSET) |
98 	(CONFIG_HPS_PERPLLGRP_SRC_SDMMC <<
99 		CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET),
100 
101 	/* sdram pll group */
102 	SDR_VCO_BASE,
103 	(CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE <<
104 		CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_OFFSET) |
105 	(CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT <<
106 		CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET),
107 	(CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE <<
108 		CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_OFFSET) |
109 	(CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT <<
110 		CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_OFFSET),
111 	(CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE <<
112 		CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_OFFSET) |
113 	(CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT <<
114 		CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_OFFSET),
115 	(CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE <<
116 		CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_OFFSET) |
117 	(CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT <<
118 		CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_OFFSET),
119 
120 	/* altera group */
121 	CONFIG_HPS_ALTERAGRP_MPUCLK,
122 };
123 
124 const struct cm_config * const cm_get_default_config(void)
125 {
126 	return &cm_default_cfg;
127 }
128 
129 const unsigned int cm_get_osc_clk_hz(const int osc)
130 {
131 	if (osc == 1)
132 		return CONFIG_HPS_CLK_OSC1_HZ;
133 	else if (osc == 2)
134 		return CONFIG_HPS_CLK_OSC2_HZ;
135 	else
136 		return 0;
137 }
138 
139 const unsigned int cm_get_f2s_per_ref_clk_hz(void)
140 {
141 	return CONFIG_HPS_CLK_F2S_PER_REF_HZ;
142 }
143 
144 const unsigned int cm_get_f2s_sdr_ref_clk_hz(void)
145 {
146 	return CONFIG_HPS_CLK_F2S_SDR_REF_HZ;
147 }
148