1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2016-2018 Intel Corporation <www.intel.com> 4 * 5 */ 6 7 #include <common.h> 8 #include <asm/io.h> 9 #include <asm/arch/system_manager.h> 10 11 DECLARE_GLOBAL_DATA_PTR; 12 13 static struct socfpga_system_manager *sysmgr_regs = 14 (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; 15 16 /* 17 * Configure all the pin muxes 18 */ 19 void sysmgr_pinmux_init(void) 20 { 21 populate_sysmgr_pinmux(); 22 populate_sysmgr_fpgaintf_module(); 23 } 24 25 /* 26 * Populate the value for SYSMGR.FPGAINTF.MODULE based on pinmux setting. 27 * The value is not wrote to SYSMGR.FPGAINTF.MODULE but 28 * CONFIG_SYSMGR_ISWGRP_HANDOFF. 29 */ 30 void populate_sysmgr_fpgaintf_module(void) 31 { 32 u32 handoff_val = 0; 33 34 /* Enable the signal for those HPS peripherals that use FPGA. */ 35 if (readl(&sysmgr_regs->nandusefpga) == SYSMGR_FPGAINTF_USEFPGA) 36 handoff_val |= SYSMGR_FPGAINTF_NAND; 37 if (readl(&sysmgr_regs->sdmmcusefpga) == SYSMGR_FPGAINTF_USEFPGA) 38 handoff_val |= SYSMGR_FPGAINTF_SDMMC; 39 if (readl(&sysmgr_regs->spim0usefpga) == SYSMGR_FPGAINTF_USEFPGA) 40 handoff_val |= SYSMGR_FPGAINTF_SPIM0; 41 if (readl(&sysmgr_regs->spim1usefpga) == SYSMGR_FPGAINTF_USEFPGA) 42 handoff_val |= SYSMGR_FPGAINTF_SPIM1; 43 writel(handoff_val, &sysmgr_regs->fpgaintf_en_2); 44 45 handoff_val = 0; 46 if (readl(&sysmgr_regs->rgmii0usefpga) == SYSMGR_FPGAINTF_USEFPGA) 47 handoff_val |= SYSMGR_FPGAINTF_EMAC0; 48 if (readl(&sysmgr_regs->rgmii1usefpga) == SYSMGR_FPGAINTF_USEFPGA) 49 handoff_val |= SYSMGR_FPGAINTF_EMAC1; 50 if (readl(&sysmgr_regs->rgmii2usefpga) == SYSMGR_FPGAINTF_USEFPGA) 51 handoff_val |= SYSMGR_FPGAINTF_EMAC2; 52 writel(handoff_val, &sysmgr_regs->fpgaintf_en_3); 53 } 54 55 /* 56 * Configure all the pin muxes 57 */ 58 void populate_sysmgr_pinmux(void) 59 { 60 const u32 *sys_mgr_table_u32; 61 unsigned int len, i; 62 63 /* setup the pin sel */ 64 sysmgr_pinmux_table_sel(&sys_mgr_table_u32, &len); 65 for (i = 0; i < len; i = i + 2) { 66 writel(sys_mgr_table_u32[i + 1], 67 sys_mgr_table_u32[i] + (u8 *)&sysmgr_regs->pinsel0[0]); 68 } 69 70 /* setup the pin ctrl */ 71 sysmgr_pinmux_table_ctrl(&sys_mgr_table_u32, &len); 72 for (i = 0; i < len; i = i + 2) { 73 writel(sys_mgr_table_u32[i + 1], 74 sys_mgr_table_u32[i] + (u8 *)&sysmgr_regs->ioctrl0[0]); 75 } 76 77 /* setup the fpga use */ 78 sysmgr_pinmux_table_fpga(&sys_mgr_table_u32, &len); 79 for (i = 0; i < len; i = i + 2) { 80 writel(sys_mgr_table_u32[i + 1], 81 sys_mgr_table_u32[i] + 82 (u8 *)&sysmgr_regs->rgmii0usefpga); 83 } 84 85 /* setup the IO delay */ 86 sysmgr_pinmux_table_delay(&sys_mgr_table_u32, &len); 87 for (i = 0; i < len; i = i + 2) { 88 writel(sys_mgr_table_u32[i + 1], 89 sys_mgr_table_u32[i] + (u8 *)&sysmgr_regs->iodelay0[0]); 90 } 91 } 92