1*73175d04SLey Foon Tan // SPDX-License-Identifier: GPL-2.0 2*73175d04SLey Foon Tan /* 3*73175d04SLey Foon Tan * Copyright (C) 2016-2018 Intel Corporation <www.intel.com> 4*73175d04SLey Foon Tan * 5*73175d04SLey Foon Tan */ 6*73175d04SLey Foon Tan 7*73175d04SLey Foon Tan #include <common.h> 8*73175d04SLey Foon Tan #include <asm/io.h> 9*73175d04SLey Foon Tan #include <asm/arch/system_manager.h> 10*73175d04SLey Foon Tan 11*73175d04SLey Foon Tan DECLARE_GLOBAL_DATA_PTR; 12*73175d04SLey Foon Tan 13*73175d04SLey Foon Tan static struct socfpga_system_manager *sysmgr_regs = 14*73175d04SLey Foon Tan (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; 15*73175d04SLey Foon Tan 16*73175d04SLey Foon Tan /* 17*73175d04SLey Foon Tan * Configure all the pin muxes 18*73175d04SLey Foon Tan */ 19*73175d04SLey Foon Tan void sysmgr_pinmux_init(void) 20*73175d04SLey Foon Tan { 21*73175d04SLey Foon Tan populate_sysmgr_pinmux(); 22*73175d04SLey Foon Tan populate_sysmgr_fpgaintf_module(); 23*73175d04SLey Foon Tan } 24*73175d04SLey Foon Tan 25*73175d04SLey Foon Tan /* 26*73175d04SLey Foon Tan * Populate the value for SYSMGR.FPGAINTF.MODULE based on pinmux setting. 27*73175d04SLey Foon Tan * The value is not wrote to SYSMGR.FPGAINTF.MODULE but 28*73175d04SLey Foon Tan * CONFIG_SYSMGR_ISWGRP_HANDOFF. 29*73175d04SLey Foon Tan */ 30*73175d04SLey Foon Tan void populate_sysmgr_fpgaintf_module(void) 31*73175d04SLey Foon Tan { 32*73175d04SLey Foon Tan u32 handoff_val = 0; 33*73175d04SLey Foon Tan 34*73175d04SLey Foon Tan /* Enable the signal for those HPS peripherals that use FPGA. */ 35*73175d04SLey Foon Tan if (readl(&sysmgr_regs->nandusefpga) == SYSMGR_FPGAINTF_USEFPGA) 36*73175d04SLey Foon Tan handoff_val |= SYSMGR_FPGAINTF_NAND; 37*73175d04SLey Foon Tan if (readl(&sysmgr_regs->sdmmcusefpga) == SYSMGR_FPGAINTF_USEFPGA) 38*73175d04SLey Foon Tan handoff_val |= SYSMGR_FPGAINTF_SDMMC; 39*73175d04SLey Foon Tan if (readl(&sysmgr_regs->spim0usefpga) == SYSMGR_FPGAINTF_USEFPGA) 40*73175d04SLey Foon Tan handoff_val |= SYSMGR_FPGAINTF_SPIM0; 41*73175d04SLey Foon Tan if (readl(&sysmgr_regs->spim1usefpga) == SYSMGR_FPGAINTF_USEFPGA) 42*73175d04SLey Foon Tan handoff_val |= SYSMGR_FPGAINTF_SPIM1; 43*73175d04SLey Foon Tan writel(handoff_val, &sysmgr_regs->fpgaintf_en_2); 44*73175d04SLey Foon Tan 45*73175d04SLey Foon Tan handoff_val = 0; 46*73175d04SLey Foon Tan if (readl(&sysmgr_regs->rgmii0usefpga) == SYSMGR_FPGAINTF_USEFPGA) 47*73175d04SLey Foon Tan handoff_val |= SYSMGR_FPGAINTF_EMAC0; 48*73175d04SLey Foon Tan if (readl(&sysmgr_regs->rgmii1usefpga) == SYSMGR_FPGAINTF_USEFPGA) 49*73175d04SLey Foon Tan handoff_val |= SYSMGR_FPGAINTF_EMAC1; 50*73175d04SLey Foon Tan if (readl(&sysmgr_regs->rgmii2usefpga) == SYSMGR_FPGAINTF_USEFPGA) 51*73175d04SLey Foon Tan handoff_val |= SYSMGR_FPGAINTF_EMAC2; 52*73175d04SLey Foon Tan writel(handoff_val, &sysmgr_regs->fpgaintf_en_3); 53*73175d04SLey Foon Tan } 54*73175d04SLey Foon Tan 55*73175d04SLey Foon Tan /* 56*73175d04SLey Foon Tan * Configure all the pin muxes 57*73175d04SLey Foon Tan */ 58*73175d04SLey Foon Tan void populate_sysmgr_pinmux(void) 59*73175d04SLey Foon Tan { 60*73175d04SLey Foon Tan const u32 *sys_mgr_table_u32; 61*73175d04SLey Foon Tan unsigned int len, i; 62*73175d04SLey Foon Tan 63*73175d04SLey Foon Tan /* setup the pin sel */ 64*73175d04SLey Foon Tan sysmgr_pinmux_table_sel(&sys_mgr_table_u32, &len); 65*73175d04SLey Foon Tan for (i = 0; i < len; i = i + 2) { 66*73175d04SLey Foon Tan writel(sys_mgr_table_u32[i + 1], 67*73175d04SLey Foon Tan sys_mgr_table_u32[i] + (u8 *)&sysmgr_regs->pinsel0[0]); 68*73175d04SLey Foon Tan } 69*73175d04SLey Foon Tan 70*73175d04SLey Foon Tan /* setup the pin ctrl */ 71*73175d04SLey Foon Tan sysmgr_pinmux_table_ctrl(&sys_mgr_table_u32, &len); 72*73175d04SLey Foon Tan for (i = 0; i < len; i = i + 2) { 73*73175d04SLey Foon Tan writel(sys_mgr_table_u32[i + 1], 74*73175d04SLey Foon Tan sys_mgr_table_u32[i] + (u8 *)&sysmgr_regs->ioctrl0[0]); 75*73175d04SLey Foon Tan } 76*73175d04SLey Foon Tan 77*73175d04SLey Foon Tan /* setup the fpga use */ 78*73175d04SLey Foon Tan sysmgr_pinmux_table_fpga(&sys_mgr_table_u32, &len); 79*73175d04SLey Foon Tan for (i = 0; i < len; i = i + 2) { 80*73175d04SLey Foon Tan writel(sys_mgr_table_u32[i + 1], 81*73175d04SLey Foon Tan sys_mgr_table_u32[i] + 82*73175d04SLey Foon Tan (u8 *)&sysmgr_regs->rgmii0usefpga); 83*73175d04SLey Foon Tan } 84*73175d04SLey Foon Tan 85*73175d04SLey Foon Tan /* setup the IO delay */ 86*73175d04SLey Foon Tan sysmgr_pinmux_table_delay(&sys_mgr_table_u32, &len); 87*73175d04SLey Foon Tan for (i = 0; i < len; i = i + 2) { 88*73175d04SLey Foon Tan writel(sys_mgr_table_u32[i + 1], 89*73175d04SLey Foon Tan sys_mgr_table_u32[i] + (u8 *)&sysmgr_regs->iodelay0[0]); 90*73175d04SLey Foon Tan } 91*73175d04SLey Foon Tan } 92