14765ddb0SLey Foon Tan // SPDX-License-Identifier: GPL-2.0 24765ddb0SLey Foon Tan /* 34765ddb0SLey Foon Tan * Copyright (C) 2016-2018 Intel Corporation <www.intel.com> 44765ddb0SLey Foon Tan * 54765ddb0SLey Foon Tan */ 64765ddb0SLey Foon Tan 74765ddb0SLey Foon Tan #include <asm/io.h> 84765ddb0SLey Foon Tan #include <asm/u-boot.h> 94765ddb0SLey Foon Tan #include <asm/utils.h> 104765ddb0SLey Foon Tan #include <common.h> 11*aa529663SLey Foon Tan #include <debug_uart.h> 124765ddb0SLey Foon Tan #include <image.h> 134765ddb0SLey Foon Tan #include <spl.h> 144765ddb0SLey Foon Tan #include <asm/arch/clock_manager.h> 154765ddb0SLey Foon Tan #include <asm/arch/firewall_s10.h> 164765ddb0SLey Foon Tan #include <asm/arch/mailbox_s10.h> 174765ddb0SLey Foon Tan #include <asm/arch/reset_manager.h> 184765ddb0SLey Foon Tan #include <asm/arch/sdram_s10.h> 194765ddb0SLey Foon Tan #include <asm/arch/system_manager.h> 204765ddb0SLey Foon Tan #include <watchdog.h> 214765ddb0SLey Foon Tan 224765ddb0SLey Foon Tan DECLARE_GLOBAL_DATA_PTR; 234765ddb0SLey Foon Tan 244765ddb0SLey Foon Tan static struct socfpga_system_manager *sysmgr_regs = 254765ddb0SLey Foon Tan (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; 264765ddb0SLey Foon Tan 274765ddb0SLey Foon Tan u32 spl_boot_device(void) 284765ddb0SLey Foon Tan { 294765ddb0SLey Foon Tan /* TODO: Get from SDM or handoff */ 304765ddb0SLey Foon Tan return BOOT_DEVICE_MMC1; 314765ddb0SLey Foon Tan } 324765ddb0SLey Foon Tan 334765ddb0SLey Foon Tan #ifdef CONFIG_SPL_MMC_SUPPORT 344765ddb0SLey Foon Tan u32 spl_boot_mode(const u32 boot_device) 354765ddb0SLey Foon Tan { 364765ddb0SLey Foon Tan #if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT) 374765ddb0SLey Foon Tan return MMCSD_MODE_FS; 384765ddb0SLey Foon Tan #else 394765ddb0SLey Foon Tan return MMCSD_MODE_RAW; 404765ddb0SLey Foon Tan #endif 414765ddb0SLey Foon Tan } 424765ddb0SLey Foon Tan #endif 434765ddb0SLey Foon Tan 444765ddb0SLey Foon Tan void spl_disable_firewall_l4_per(void) 454765ddb0SLey Foon Tan { 464765ddb0SLey Foon Tan const struct socfpga_firwall_l4_per *firwall_l4_per_base = 474765ddb0SLey Foon Tan (struct socfpga_firwall_l4_per *)SOCFPGA_FIREWALL_L4_PER; 484765ddb0SLey Foon Tan u32 i; 494765ddb0SLey Foon Tan const u32 *addr[] = { 504765ddb0SLey Foon Tan &firwall_l4_per_base->nand, 514765ddb0SLey Foon Tan &firwall_l4_per_base->nand_data, 524765ddb0SLey Foon Tan &firwall_l4_per_base->usb0, 534765ddb0SLey Foon Tan &firwall_l4_per_base->usb1, 544765ddb0SLey Foon Tan &firwall_l4_per_base->spim0, 554765ddb0SLey Foon Tan &firwall_l4_per_base->spim1, 564765ddb0SLey Foon Tan &firwall_l4_per_base->emac0, 574765ddb0SLey Foon Tan &firwall_l4_per_base->emac1, 584765ddb0SLey Foon Tan &firwall_l4_per_base->emac2, 594765ddb0SLey Foon Tan &firwall_l4_per_base->sdmmc, 604765ddb0SLey Foon Tan &firwall_l4_per_base->gpio0, 614765ddb0SLey Foon Tan &firwall_l4_per_base->gpio1, 624765ddb0SLey Foon Tan &firwall_l4_per_base->i2c0, 634765ddb0SLey Foon Tan &firwall_l4_per_base->i2c1, 644765ddb0SLey Foon Tan &firwall_l4_per_base->i2c2, 654765ddb0SLey Foon Tan &firwall_l4_per_base->i2c3, 664765ddb0SLey Foon Tan &firwall_l4_per_base->i2c4, 674765ddb0SLey Foon Tan &firwall_l4_per_base->timer0, 684765ddb0SLey Foon Tan &firwall_l4_per_base->timer1, 694765ddb0SLey Foon Tan &firwall_l4_per_base->uart0, 704765ddb0SLey Foon Tan &firwall_l4_per_base->uart1 714765ddb0SLey Foon Tan }; 724765ddb0SLey Foon Tan 734765ddb0SLey Foon Tan /* 744765ddb0SLey Foon Tan * The following lines of code will enable non-secure access 754765ddb0SLey Foon Tan * to nand, usb, spi, emac, sdmmc, gpio, i2c, timers and uart. This 764765ddb0SLey Foon Tan * is needed as most OS run in non-secure mode. Thus we need to 774765ddb0SLey Foon Tan * enable non-secure access to these peripherals in order for the 784765ddb0SLey Foon Tan * OS to use these peripherals. 794765ddb0SLey Foon Tan */ 804765ddb0SLey Foon Tan for (i = 0; i < ARRAY_SIZE(addr); i++) 814765ddb0SLey Foon Tan writel(FIREWALL_L4_DISABLE_ALL, addr[i]); 824765ddb0SLey Foon Tan } 834765ddb0SLey Foon Tan 844765ddb0SLey Foon Tan void spl_disable_firewall_l4_sys(void) 854765ddb0SLey Foon Tan { 864765ddb0SLey Foon Tan const struct socfpga_firwall_l4_sys *firwall_l4_sys_base = 874765ddb0SLey Foon Tan (struct socfpga_firwall_l4_sys *)SOCFPGA_FIREWALL_L4_SYS; 884765ddb0SLey Foon Tan u32 i; 894765ddb0SLey Foon Tan const u32 *addr[] = { 904765ddb0SLey Foon Tan &firwall_l4_sys_base->dma_ecc, 914765ddb0SLey Foon Tan &firwall_l4_sys_base->emac0rx_ecc, 924765ddb0SLey Foon Tan &firwall_l4_sys_base->emac0tx_ecc, 934765ddb0SLey Foon Tan &firwall_l4_sys_base->emac1rx_ecc, 944765ddb0SLey Foon Tan &firwall_l4_sys_base->emac1tx_ecc, 954765ddb0SLey Foon Tan &firwall_l4_sys_base->emac2rx_ecc, 964765ddb0SLey Foon Tan &firwall_l4_sys_base->emac2tx_ecc, 974765ddb0SLey Foon Tan &firwall_l4_sys_base->nand_ecc, 984765ddb0SLey Foon Tan &firwall_l4_sys_base->nand_read_ecc, 994765ddb0SLey Foon Tan &firwall_l4_sys_base->nand_write_ecc, 1004765ddb0SLey Foon Tan &firwall_l4_sys_base->ocram_ecc, 1014765ddb0SLey Foon Tan &firwall_l4_sys_base->sdmmc_ecc, 1024765ddb0SLey Foon Tan &firwall_l4_sys_base->usb0_ecc, 1034765ddb0SLey Foon Tan &firwall_l4_sys_base->usb1_ecc, 1044765ddb0SLey Foon Tan &firwall_l4_sys_base->clock_manager, 1054765ddb0SLey Foon Tan &firwall_l4_sys_base->io_manager, 1064765ddb0SLey Foon Tan &firwall_l4_sys_base->reset_manager, 1074765ddb0SLey Foon Tan &firwall_l4_sys_base->system_manager, 1084765ddb0SLey Foon Tan &firwall_l4_sys_base->watchdog0, 1094765ddb0SLey Foon Tan &firwall_l4_sys_base->watchdog1, 1104765ddb0SLey Foon Tan &firwall_l4_sys_base->watchdog2, 1114765ddb0SLey Foon Tan &firwall_l4_sys_base->watchdog3 1124765ddb0SLey Foon Tan }; 1134765ddb0SLey Foon Tan 1144765ddb0SLey Foon Tan for (i = 0; i < ARRAY_SIZE(addr); i++) 1154765ddb0SLey Foon Tan writel(FIREWALL_L4_DISABLE_ALL, addr[i]); 1164765ddb0SLey Foon Tan } 1174765ddb0SLey Foon Tan 1184765ddb0SLey Foon Tan void board_init_f(ulong dummy) 1194765ddb0SLey Foon Tan { 1204765ddb0SLey Foon Tan const struct cm_config *cm_default_cfg = cm_get_default_config(); 1214765ddb0SLey Foon Tan int ret; 1224765ddb0SLey Foon Tan 1234765ddb0SLey Foon Tan #ifdef CONFIG_HW_WATCHDOG 1244765ddb0SLey Foon Tan /* Ensure watchdog is paused when debugging is happening */ 1254765ddb0SLey Foon Tan writel(SYSMGR_WDDBG_PAUSE_ALL_CPU, &sysmgr_regs->wddbg); 1264765ddb0SLey Foon Tan 1274765ddb0SLey Foon Tan /* Enable watchdog before initializing the HW */ 1284765ddb0SLey Foon Tan socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1); 1294765ddb0SLey Foon Tan socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0); 1304765ddb0SLey Foon Tan hw_watchdog_init(); 1314765ddb0SLey Foon Tan #endif 1324765ddb0SLey Foon Tan 1334765ddb0SLey Foon Tan /* ensure all processors are not released prior Linux boot */ 1344765ddb0SLey Foon Tan writeq(0, CPU_RELEASE_ADDR); 1354765ddb0SLey Foon Tan 1364765ddb0SLey Foon Tan socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0); 1374765ddb0SLey Foon Tan timer_init(); 1384765ddb0SLey Foon Tan 1394765ddb0SLey Foon Tan populate_sysmgr_pinmux(); 1404765ddb0SLey Foon Tan 1414765ddb0SLey Foon Tan /* configuring the HPS clocks */ 1424765ddb0SLey Foon Tan cm_basic_init(cm_default_cfg); 1434765ddb0SLey Foon Tan 1444765ddb0SLey Foon Tan #ifdef CONFIG_DEBUG_UART 1454765ddb0SLey Foon Tan socfpga_per_reset(SOCFPGA_RESET(UART0), 0); 1464765ddb0SLey Foon Tan debug_uart_init(); 1474765ddb0SLey Foon Tan #endif 1484765ddb0SLey Foon Tan ret = spl_early_init(); 1494765ddb0SLey Foon Tan if (ret) { 1504765ddb0SLey Foon Tan debug("spl_early_init() failed: %d\n", ret); 1514765ddb0SLey Foon Tan hang(); 1524765ddb0SLey Foon Tan } 1534765ddb0SLey Foon Tan 1544765ddb0SLey Foon Tan preloader_console_init(); 1554765ddb0SLey Foon Tan cm_print_clock_quick_summary(); 1564765ddb0SLey Foon Tan 1574765ddb0SLey Foon Tan /* enable non-secure interface to DMA330 DMA and peripherals */ 1584765ddb0SLey Foon Tan writel(SYSMGR_DMA_IRQ_NS | SYSMGR_DMA_MGR_NS, &sysmgr_regs->dma); 1594765ddb0SLey Foon Tan writel(SYSMGR_DMAPERIPH_ALL_NS, &sysmgr_regs->dma_periph); 1604765ddb0SLey Foon Tan 1614765ddb0SLey Foon Tan spl_disable_firewall_l4_per(); 1624765ddb0SLey Foon Tan 1634765ddb0SLey Foon Tan spl_disable_firewall_l4_sys(); 1644765ddb0SLey Foon Tan 1654765ddb0SLey Foon Tan /* disable lwsocf2fpga and soc2fpga bridge security */ 1664765ddb0SLey Foon Tan writel(FIREWALL_BRIDGE_DISABLE_ALL, SOCFPGA_FIREWALL_SOC2FPGA); 1674765ddb0SLey Foon Tan writel(FIREWALL_BRIDGE_DISABLE_ALL, SOCFPGA_FIREWALL_LWSOC2FPGA); 1684765ddb0SLey Foon Tan 1694765ddb0SLey Foon Tan /* disable SMMU security */ 1704765ddb0SLey Foon Tan writel(FIREWALL_L4_DISABLE_ALL, SOCFPGA_FIREWALL_TCU); 1714765ddb0SLey Foon Tan 1724765ddb0SLey Foon Tan /* disable ocram security at CCU for non secure access */ 1734765ddb0SLey Foon Tan clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADMASK_MEM_RAM0), 1744765ddb0SLey Foon Tan CCU_ADMASK_P_MASK | CCU_ADMASK_NS_MASK); 1754765ddb0SLey Foon Tan clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADMASK_MEM_RAM0), 1764765ddb0SLey Foon Tan CCU_ADMASK_P_MASK | CCU_ADMASK_NS_MASK); 1774765ddb0SLey Foon Tan 1784765ddb0SLey Foon Tan debug("DDR: Initializing Hard Memory Controller\n"); 1794765ddb0SLey Foon Tan if (sdram_mmr_init_full(0)) { 1804765ddb0SLey Foon Tan puts("DDR: Initialization failed.\n"); 1814765ddb0SLey Foon Tan hang(); 1824765ddb0SLey Foon Tan } 1834765ddb0SLey Foon Tan 1844765ddb0SLey Foon Tan gd->ram_size = sdram_calculate_size(); 1854765ddb0SLey Foon Tan printf("DDR: %d MiB\n", (int)(gd->ram_size >> 20)); 1864765ddb0SLey Foon Tan 1874765ddb0SLey Foon Tan /* Sanity check ensure correct SDRAM size specified */ 1884765ddb0SLey Foon Tan debug("DDR: Running SDRAM size sanity check\n"); 1894765ddb0SLey Foon Tan if (get_ram_size(0, gd->ram_size) != gd->ram_size) { 1904765ddb0SLey Foon Tan puts("DDR: SDRAM size check failed!\n"); 1914765ddb0SLey Foon Tan hang(); 1924765ddb0SLey Foon Tan } 1934765ddb0SLey Foon Tan debug("DDR: SDRAM size check passed!\n"); 1944765ddb0SLey Foon Tan 1954765ddb0SLey Foon Tan mbox_init(); 1964765ddb0SLey Foon Tan 1974765ddb0SLey Foon Tan #ifdef CONFIG_CADENCE_QSPI 1984765ddb0SLey Foon Tan mbox_qspi_open(); 1994765ddb0SLey Foon Tan #endif 2004765ddb0SLey Foon Tan } 201