1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2012 Altera Corporation <www.altera.com> 4 */ 5 6 #include <common.h> 7 #include <asm/io.h> 8 #include <asm/pl310.h> 9 #include <asm/u-boot.h> 10 #include <asm/utils.h> 11 #include <image.h> 12 #include <asm/arch/reset_manager.h> 13 #include <spl.h> 14 #include <asm/arch/system_manager.h> 15 #include <asm/arch/freeze_controller.h> 16 #include <asm/arch/clock_manager.h> 17 #include <asm/arch/misc.h> 18 #include <asm/arch/scan_manager.h> 19 #include <asm/arch/sdram.h> 20 #include <asm/sections.h> 21 #include <debug_uart.h> 22 #include <fdtdec.h> 23 #include <watchdog.h> 24 25 DECLARE_GLOBAL_DATA_PTR; 26 27 static struct pl310_regs *const pl310 = 28 (struct pl310_regs *)CONFIG_SYS_PL310_BASE; 29 static const struct socfpga_system_manager *sysmgr_regs = 30 (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; 31 32 u32 spl_boot_device(void) 33 { 34 const u32 bsel = readl(&sysmgr_regs->bootinfo); 35 36 switch (SYSMGR_GET_BOOTINFO_BSEL(bsel)) { 37 case 0x1: /* FPGA (HPS2FPGA Bridge) */ 38 return BOOT_DEVICE_RAM; 39 case 0x2: /* NAND Flash (1.8V) */ 40 case 0x3: /* NAND Flash (3.0V) */ 41 socfpga_per_reset(SOCFPGA_RESET(NAND), 0); 42 return BOOT_DEVICE_NAND; 43 case 0x4: /* SD/MMC External Transceiver (1.8V) */ 44 case 0x5: /* SD/MMC Internal Transceiver (3.0V) */ 45 socfpga_per_reset(SOCFPGA_RESET(SDMMC), 0); 46 socfpga_per_reset(SOCFPGA_RESET(DMA), 0); 47 return BOOT_DEVICE_MMC1; 48 case 0x6: /* QSPI Flash (1.8V) */ 49 case 0x7: /* QSPI Flash (3.0V) */ 50 socfpga_per_reset(SOCFPGA_RESET(QSPI), 0); 51 return BOOT_DEVICE_SPI; 52 default: 53 printf("Invalid boot device (bsel=%08x)!\n", bsel); 54 hang(); 55 } 56 } 57 58 #ifdef CONFIG_SPL_MMC_SUPPORT 59 u32 spl_boot_mode(const u32 boot_device) 60 { 61 #if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4) 62 return MMCSD_MODE_FS; 63 #else 64 return MMCSD_MODE_RAW; 65 #endif 66 } 67 #endif 68 69 static void socfpga_pl310_clear(void) 70 { 71 u32 mask = 0xff, ena = 0; 72 73 icache_enable(); 74 75 /* Disable the L2 cache */ 76 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); 77 78 writel(0x111, &pl310->pl310_tag_latency_ctrl); 79 writel(0x121, &pl310->pl310_data_latency_ctrl); 80 81 /* enable BRESP, instruction and data prefetch, full line of zeroes */ 82 setbits_le32(&pl310->pl310_aux_ctrl, 83 L310_AUX_CTRL_DATA_PREFETCH_MASK | 84 L310_AUX_CTRL_INST_PREFETCH_MASK | 85 L310_SHARED_ATT_OVERRIDE_ENABLE); 86 87 /* Enable the L2 cache */ 88 ena = readl(&pl310->pl310_ctrl); 89 ena |= L2X0_CTRL_EN; 90 91 /* 92 * Invalidate the PL310 L2 cache. Keep the invalidation code 93 * entirely in L1 I-cache to avoid any bus traffic through 94 * the L2. 95 */ 96 asm volatile( 97 ".align 5 \n" 98 " b 3f \n" 99 "1: str %1, [%4] \n" 100 " dsb \n" 101 " isb \n" 102 " str %0, [%2] \n" 103 " dsb \n" 104 " isb \n" 105 "2: ldr %0, [%2] \n" 106 " cmp %0, #0 \n" 107 " bne 2b \n" 108 " str %0, [%3] \n" 109 " dsb \n" 110 " isb \n" 111 " b 4f \n" 112 "3: b 1b \n" 113 "4: nop \n" 114 : "+r"(mask), "+r"(ena) 115 : "r"(&pl310->pl310_inv_way), 116 "r"(&pl310->pl310_cache_sync), "r"(&pl310->pl310_ctrl) 117 : "memory", "cc"); 118 119 /* Disable the L2 cache */ 120 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); 121 } 122 123 void board_init_f(ulong dummy) 124 { 125 const struct cm_config *cm_default_cfg = cm_get_default_config(); 126 unsigned long sdram_size; 127 unsigned long reg; 128 int ret; 129 130 /* 131 * First C code to run. Clear fake OCRAM ECC first as SBE 132 * and DBE might triggered during power on 133 */ 134 reg = readl(&sysmgr_regs->eccgrp_ocram); 135 if (reg & SYSMGR_ECC_OCRAM_SERR) 136 writel(SYSMGR_ECC_OCRAM_SERR | SYSMGR_ECC_OCRAM_EN, 137 &sysmgr_regs->eccgrp_ocram); 138 if (reg & SYSMGR_ECC_OCRAM_DERR) 139 writel(SYSMGR_ECC_OCRAM_DERR | SYSMGR_ECC_OCRAM_EN, 140 &sysmgr_regs->eccgrp_ocram); 141 142 memset(__bss_start, 0, __bss_end - __bss_start); 143 144 socfpga_sdram_remap_zero(); 145 socfpga_pl310_clear(); 146 147 debug("Freezing all I/O banks\n"); 148 /* freeze all IO banks */ 149 sys_mgr_frzctrl_freeze_req(); 150 151 /* Put everything into reset but L4WD0. */ 152 socfpga_per_reset_all(); 153 154 if (!socfpga_is_booting_from_fpga()) { 155 /* Put FPGA bridges into reset too. */ 156 socfpga_bridges_reset(1); 157 } 158 159 socfpga_per_reset(SOCFPGA_RESET(SDR), 0); 160 socfpga_per_reset(SOCFPGA_RESET(UART0), 0); 161 socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0); 162 163 timer_init(); 164 165 debug("Reconfigure Clock Manager\n"); 166 /* reconfigure the PLLs */ 167 if (cm_basic_init(cm_default_cfg)) 168 hang(); 169 170 /* Enable bootrom to configure IOs. */ 171 sysmgr_config_warmrstcfgio(1); 172 173 /* configure the IOCSR / IO buffer settings */ 174 if (scan_mgr_configure_iocsr()) 175 hang(); 176 177 sysmgr_config_warmrstcfgio(0); 178 179 /* configure the pin muxing through system manager */ 180 sysmgr_config_warmrstcfgio(1); 181 sysmgr_pinmux_init(); 182 sysmgr_config_warmrstcfgio(0); 183 184 /* De-assert reset for peripherals and bridges based on handoff */ 185 reset_deassert_peripherals_handoff(); 186 socfpga_bridges_reset(0); 187 188 debug("Unfreezing/Thaw all I/O banks\n"); 189 /* unfreeze / thaw all IO banks */ 190 sys_mgr_frzctrl_thaw_req(); 191 192 #ifdef CONFIG_DEBUG_UART 193 socfpga_per_reset(SOCFPGA_RESET(UART0), 0); 194 debug_uart_init(); 195 #endif 196 197 ret = spl_early_init(); 198 if (ret) { 199 debug("spl_early_init() failed: %d\n", ret); 200 hang(); 201 } 202 203 /* enable console uart printing */ 204 preloader_console_init(); 205 206 if (sdram_mmr_init_full(0xffffffff) != 0) { 207 puts("SDRAM init failed.\n"); 208 hang(); 209 } 210 211 debug("SDRAM: Calibrating PHY\n"); 212 /* SDRAM calibration */ 213 if (sdram_calibration_full() == 0) { 214 puts("SDRAM calibration failed.\n"); 215 hang(); 216 } 217 218 sdram_size = sdram_calculate_size(); 219 debug("SDRAM: %ld MiB\n", sdram_size >> 20); 220 221 /* Sanity check ensure correct SDRAM size specified */ 222 if (get_ram_size(0, sdram_size) != sdram_size) { 223 puts("SDRAM size check failed!\n"); 224 hang(); 225 } 226 227 if (!socfpga_is_booting_from_fpga()) 228 socfpga_bridges_reset(1); 229 } 230