1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2012 Altera Corporation <www.altera.com> 4 */ 5 6 #include <common.h> 7 #include <asm/io.h> 8 #include <asm/pl310.h> 9 #include <asm/u-boot.h> 10 #include <asm/utils.h> 11 #include <image.h> 12 #include <asm/arch/reset_manager.h> 13 #include <spl.h> 14 #include <asm/arch/system_manager.h> 15 #include <asm/arch/freeze_controller.h> 16 #include <asm/arch/clock_manager.h> 17 #include <asm/arch/misc.h> 18 #include <asm/arch/scan_manager.h> 19 #include <asm/arch/sdram.h> 20 #include <asm/arch/scu.h> 21 #include <asm/arch/nic301.h> 22 #include <asm/sections.h> 23 #include <fdtdec.h> 24 #include <watchdog.h> 25 26 DECLARE_GLOBAL_DATA_PTR; 27 28 static struct pl310_regs *const pl310 = 29 (struct pl310_regs *)CONFIG_SYS_PL310_BASE; 30 static struct scu_registers *scu_regs = 31 (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS; 32 static struct nic301_registers *nic301_regs = 33 (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS; 34 static const struct socfpga_system_manager *sysmgr_regs = 35 (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; 36 37 u32 spl_boot_device(void) 38 { 39 const u32 bsel = readl(&sysmgr_regs->bootinfo); 40 41 switch (SYSMGR_GET_BOOTINFO_BSEL(bsel)) { 42 case 0x1: /* FPGA (HPS2FPGA Bridge) */ 43 return BOOT_DEVICE_RAM; 44 case 0x2: /* NAND Flash (1.8V) */ 45 case 0x3: /* NAND Flash (3.0V) */ 46 socfpga_per_reset(SOCFPGA_RESET(NAND), 0); 47 return BOOT_DEVICE_NAND; 48 case 0x4: /* SD/MMC External Transceiver (1.8V) */ 49 case 0x5: /* SD/MMC Internal Transceiver (3.0V) */ 50 socfpga_per_reset(SOCFPGA_RESET(SDMMC), 0); 51 socfpga_per_reset(SOCFPGA_RESET(DMA), 0); 52 return BOOT_DEVICE_MMC1; 53 case 0x6: /* QSPI Flash (1.8V) */ 54 case 0x7: /* QSPI Flash (3.0V) */ 55 socfpga_per_reset(SOCFPGA_RESET(QSPI), 0); 56 return BOOT_DEVICE_SPI; 57 default: 58 printf("Invalid boot device (bsel=%08x)!\n", bsel); 59 hang(); 60 } 61 } 62 63 #ifdef CONFIG_SPL_MMC_SUPPORT 64 u32 spl_boot_mode(const u32 boot_device) 65 { 66 #if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT) 67 return MMCSD_MODE_FS; 68 #else 69 return MMCSD_MODE_RAW; 70 #endif 71 } 72 #endif 73 74 static void socfpga_nic301_slave_ns(void) 75 { 76 writel(0x1, &nic301_regs->lwhps2fpgaregs); 77 writel(0x1, &nic301_regs->hps2fpgaregs); 78 writel(0x1, &nic301_regs->acp); 79 writel(0x1, &nic301_regs->rom); 80 writel(0x1, &nic301_regs->ocram); 81 writel(0x1, &nic301_regs->sdrdata); 82 } 83 84 void board_init_f(ulong dummy) 85 { 86 const struct cm_config *cm_default_cfg = cm_get_default_config(); 87 unsigned long sdram_size; 88 unsigned long reg; 89 90 /* 91 * First C code to run. Clear fake OCRAM ECC first as SBE 92 * and DBE might triggered during power on 93 */ 94 reg = readl(&sysmgr_regs->eccgrp_ocram); 95 if (reg & SYSMGR_ECC_OCRAM_SERR) 96 writel(SYSMGR_ECC_OCRAM_SERR | SYSMGR_ECC_OCRAM_EN, 97 &sysmgr_regs->eccgrp_ocram); 98 if (reg & SYSMGR_ECC_OCRAM_DERR) 99 writel(SYSMGR_ECC_OCRAM_DERR | SYSMGR_ECC_OCRAM_EN, 100 &sysmgr_regs->eccgrp_ocram); 101 102 memset(__bss_start, 0, __bss_end - __bss_start); 103 104 socfpga_nic301_slave_ns(); 105 106 /* Configure ARM MPU SNSAC register. */ 107 setbits_le32(&scu_regs->sacr, 0xfff); 108 109 /* Remap SDRAM to 0x0 */ 110 writel(0x1, &nic301_regs->remap); /* remap.mpuzero */ 111 writel(0x1, &pl310->pl310_addr_filter_start); 112 113 debug("Freezing all I/O banks\n"); 114 /* freeze all IO banks */ 115 sys_mgr_frzctrl_freeze_req(); 116 117 /* Put everything into reset but L4WD0. */ 118 socfpga_per_reset_all(); 119 /* Put FPGA bridges into reset too. */ 120 socfpga_bridges_reset(1); 121 122 socfpga_per_reset(SOCFPGA_RESET(SDR), 0); 123 socfpga_per_reset(SOCFPGA_RESET(UART0), 0); 124 socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0); 125 126 timer_init(); 127 128 debug("Reconfigure Clock Manager\n"); 129 /* reconfigure the PLLs */ 130 if (cm_basic_init(cm_default_cfg)) 131 hang(); 132 133 /* Enable bootrom to configure IOs. */ 134 sysmgr_config_warmrstcfgio(1); 135 136 /* configure the IOCSR / IO buffer settings */ 137 if (scan_mgr_configure_iocsr()) 138 hang(); 139 140 sysmgr_config_warmrstcfgio(0); 141 142 /* configure the pin muxing through system manager */ 143 sysmgr_config_warmrstcfgio(1); 144 sysmgr_pinmux_init(); 145 sysmgr_config_warmrstcfgio(0); 146 147 /* De-assert reset for peripherals and bridges based on handoff */ 148 reset_deassert_peripherals_handoff(); 149 socfpga_bridges_reset(0); 150 151 debug("Unfreezing/Thaw all I/O banks\n"); 152 /* unfreeze / thaw all IO banks */ 153 sys_mgr_frzctrl_thaw_req(); 154 155 /* enable console uart printing */ 156 preloader_console_init(); 157 158 if (sdram_mmr_init_full(0xffffffff) != 0) { 159 puts("SDRAM init failed.\n"); 160 hang(); 161 } 162 163 debug("SDRAM: Calibrating PHY\n"); 164 /* SDRAM calibration */ 165 if (sdram_calibration_full() == 0) { 166 puts("SDRAM calibration failed.\n"); 167 hang(); 168 } 169 170 sdram_size = sdram_calculate_size(); 171 debug("SDRAM: %ld MiB\n", sdram_size >> 20); 172 173 /* Sanity check ensure correct SDRAM size specified */ 174 if (get_ram_size(0, sdram_size) != sdram_size) { 175 puts("SDRAM size check failed!\n"); 176 hang(); 177 } 178 179 socfpga_bridges_reset(1); 180 181 /* Configure simple malloc base pointer into RAM. */ 182 gd->malloc_base = CONFIG_SYS_TEXT_BASE + (1024 * 1024); 183 } 184