1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  *  Copyright (C) 2012 Altera Corporation <www.altera.com>
4  */
5 
6 #include <common.h>
7 #include <asm/io.h>
8 #include <asm/u-boot.h>
9 #include <asm/utils.h>
10 #include <image.h>
11 #include <asm/arch/reset_manager.h>
12 #include <spl.h>
13 #include <asm/arch/system_manager.h>
14 #include <asm/arch/freeze_controller.h>
15 #include <asm/arch/clock_manager.h>
16 #include <asm/arch/misc.h>
17 #include <asm/arch/scan_manager.h>
18 #include <asm/arch/sdram.h>
19 #include <asm/sections.h>
20 #include <debug_uart.h>
21 #include <fdtdec.h>
22 #include <watchdog.h>
23 
24 DECLARE_GLOBAL_DATA_PTR;
25 
26 static const struct socfpga_system_manager *sysmgr_regs =
27 	(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
28 
29 u32 spl_boot_device(void)
30 {
31 	const u32 bsel = readl(&sysmgr_regs->bootinfo);
32 
33 	switch (SYSMGR_GET_BOOTINFO_BSEL(bsel)) {
34 	case 0x1:	/* FPGA (HPS2FPGA Bridge) */
35 		return BOOT_DEVICE_RAM;
36 	case 0x2:	/* NAND Flash (1.8V) */
37 	case 0x3:	/* NAND Flash (3.0V) */
38 		socfpga_per_reset(SOCFPGA_RESET(NAND), 0);
39 		return BOOT_DEVICE_NAND;
40 	case 0x4:	/* SD/MMC External Transceiver (1.8V) */
41 	case 0x5:	/* SD/MMC Internal Transceiver (3.0V) */
42 		socfpga_per_reset(SOCFPGA_RESET(SDMMC), 0);
43 		socfpga_per_reset(SOCFPGA_RESET(DMA), 0);
44 		return BOOT_DEVICE_MMC1;
45 	case 0x6:	/* QSPI Flash (1.8V) */
46 	case 0x7:	/* QSPI Flash (3.0V) */
47 		socfpga_per_reset(SOCFPGA_RESET(QSPI), 0);
48 		return BOOT_DEVICE_SPI;
49 	default:
50 		printf("Invalid boot device (bsel=%08x)!\n", bsel);
51 		hang();
52 	}
53 }
54 
55 #ifdef CONFIG_SPL_MMC_SUPPORT
56 u32 spl_boot_mode(const u32 boot_device)
57 {
58 #if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
59 	return MMCSD_MODE_FS;
60 #else
61 	return MMCSD_MODE_RAW;
62 #endif
63 }
64 #endif
65 
66 void board_init_f(ulong dummy)
67 {
68 	const struct cm_config *cm_default_cfg = cm_get_default_config();
69 	unsigned long sdram_size;
70 	unsigned long reg;
71 	int ret;
72 
73 	/*
74 	 * First C code to run. Clear fake OCRAM ECC first as SBE
75 	 * and DBE might triggered during power on
76 	 */
77 	reg = readl(&sysmgr_regs->eccgrp_ocram);
78 	if (reg & SYSMGR_ECC_OCRAM_SERR)
79 		writel(SYSMGR_ECC_OCRAM_SERR | SYSMGR_ECC_OCRAM_EN,
80 		       &sysmgr_regs->eccgrp_ocram);
81 	if (reg & SYSMGR_ECC_OCRAM_DERR)
82 		writel(SYSMGR_ECC_OCRAM_DERR  | SYSMGR_ECC_OCRAM_EN,
83 		       &sysmgr_regs->eccgrp_ocram);
84 
85 	memset(__bss_start, 0, __bss_end - __bss_start);
86 
87 	socfpga_sdram_remap_zero();
88 
89 	debug("Freezing all I/O banks\n");
90 	/* freeze all IO banks */
91 	sys_mgr_frzctrl_freeze_req();
92 
93 	/* Put everything into reset but L4WD0. */
94 	socfpga_per_reset_all();
95 
96 	if (!socfpga_is_booting_from_fpga()) {
97 		/* Put FPGA bridges into reset too. */
98 		socfpga_bridges_reset(1);
99 	}
100 
101 	socfpga_per_reset(SOCFPGA_RESET(SDR), 0);
102 	socfpga_per_reset(SOCFPGA_RESET(UART0), 0);
103 	socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0);
104 
105 	timer_init();
106 
107 	debug("Reconfigure Clock Manager\n");
108 	/* reconfigure the PLLs */
109 	if (cm_basic_init(cm_default_cfg))
110 		hang();
111 
112 	/* Enable bootrom to configure IOs. */
113 	sysmgr_config_warmrstcfgio(1);
114 
115 	/* configure the IOCSR / IO buffer settings */
116 	if (scan_mgr_configure_iocsr())
117 		hang();
118 
119 	sysmgr_config_warmrstcfgio(0);
120 
121 	/* configure the pin muxing through system manager */
122 	sysmgr_config_warmrstcfgio(1);
123 	sysmgr_pinmux_init();
124 	sysmgr_config_warmrstcfgio(0);
125 
126 	/* De-assert reset for peripherals and bridges based on handoff */
127 	reset_deassert_peripherals_handoff();
128 	socfpga_bridges_reset(0);
129 
130 	debug("Unfreezing/Thaw all I/O banks\n");
131 	/* unfreeze / thaw all IO banks */
132 	sys_mgr_frzctrl_thaw_req();
133 
134 #ifdef CONFIG_DEBUG_UART
135 	socfpga_per_reset(SOCFPGA_RESET(UART0), 0);
136 	debug_uart_init();
137 #endif
138 
139 	ret = spl_early_init();
140 	if (ret) {
141 		debug("spl_early_init() failed: %d\n", ret);
142 		hang();
143 	}
144 
145 	/* enable console uart printing */
146 	preloader_console_init();
147 
148 	if (sdram_mmr_init_full(0xffffffff) != 0) {
149 		puts("SDRAM init failed.\n");
150 		hang();
151 	}
152 
153 	debug("SDRAM: Calibrating PHY\n");
154 	/* SDRAM calibration */
155 	if (sdram_calibration_full() == 0) {
156 		puts("SDRAM calibration failed.\n");
157 		hang();
158 	}
159 
160 	sdram_size = sdram_calculate_size();
161 	debug("SDRAM: %ld MiB\n", sdram_size >> 20);
162 
163 	/* Sanity check ensure correct SDRAM size specified */
164 	if (get_ram_size(0, sdram_size) != sdram_size) {
165 		puts("SDRAM size check failed!\n");
166 		hang();
167 	}
168 
169 	if (!socfpga_is_booting_from_fpga())
170 		socfpga_bridges_reset(1);
171 }
172