1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2012 Altera Corporation <www.altera.com> 4 */ 5 6 #include <common.h> 7 #include <asm/io.h> 8 #include <asm/pl310.h> 9 #include <asm/u-boot.h> 10 #include <asm/utils.h> 11 #include <image.h> 12 #include <asm/arch/reset_manager.h> 13 #include <spl.h> 14 #include <asm/arch/system_manager.h> 15 #include <asm/arch/freeze_controller.h> 16 #include <asm/arch/clock_manager.h> 17 #include <asm/arch/scan_manager.h> 18 #include <asm/arch/sdram.h> 19 #include <asm/arch/scu.h> 20 #include <asm/arch/nic301.h> 21 #include <asm/sections.h> 22 #include <fdtdec.h> 23 #include <watchdog.h> 24 #include <asm/arch/pinmux.h> 25 26 DECLARE_GLOBAL_DATA_PTR; 27 28 static const struct socfpga_system_manager *sysmgr_regs = 29 (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; 30 31 u32 spl_boot_device(void) 32 { 33 const u32 bsel = readl(&sysmgr_regs->bootinfo); 34 35 switch (SYSMGR_GET_BOOTINFO_BSEL(bsel)) { 36 case 0x1: /* FPGA (HPS2FPGA Bridge) */ 37 return BOOT_DEVICE_RAM; 38 case 0x2: /* NAND Flash (1.8V) */ 39 case 0x3: /* NAND Flash (3.0V) */ 40 socfpga_per_reset(SOCFPGA_RESET(NAND), 0); 41 return BOOT_DEVICE_NAND; 42 case 0x4: /* SD/MMC External Transceiver (1.8V) */ 43 case 0x5: /* SD/MMC Internal Transceiver (3.0V) */ 44 socfpga_per_reset(SOCFPGA_RESET(SDMMC), 0); 45 socfpga_per_reset(SOCFPGA_RESET(DMA), 0); 46 return BOOT_DEVICE_MMC1; 47 case 0x6: /* QSPI Flash (1.8V) */ 48 case 0x7: /* QSPI Flash (3.0V) */ 49 socfpga_per_reset(SOCFPGA_RESET(QSPI), 0); 50 return BOOT_DEVICE_SPI; 51 default: 52 printf("Invalid boot device (bsel=%08x)!\n", bsel); 53 hang(); 54 } 55 } 56 57 #ifdef CONFIG_SPL_MMC_SUPPORT 58 u32 spl_boot_mode(const u32 boot_device) 59 { 60 #if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT) 61 return MMCSD_MODE_FS; 62 #else 63 return MMCSD_MODE_RAW; 64 #endif 65 } 66 #endif 67 68 void spl_board_init(void) 69 { 70 /* configuring the clock based on handoff */ 71 cm_basic_init(gd->fdt_blob); 72 WATCHDOG_RESET(); 73 74 config_dedicated_pins(gd->fdt_blob); 75 WATCHDOG_RESET(); 76 77 /* Release UART from reset */ 78 socfpga_reset_uart(0); 79 80 /* enable console uart printing */ 81 preloader_console_init(); 82 } 83 84 void board_init_f(ulong dummy) 85 { 86 /* 87 * Configure Clock Manager to use intosc clock instead external osc to 88 * ensure success watchdog operation. We do it as early as possible. 89 */ 90 cm_use_intosc(); 91 92 socfpga_watchdog_disable(); 93 94 arch_early_init_r(); 95 96 #ifdef CONFIG_HW_WATCHDOG 97 /* release osc1 watchdog timer 0 from reset */ 98 socfpga_reset_deassert_osc1wd0(); 99 100 /* reconfigure and enable the watchdog */ 101 hw_watchdog_init(); 102 WATCHDOG_RESET(); 103 #endif /* CONFIG_HW_WATCHDOG */ 104 } 105