1*c859f2a7SLey Foon Tan /* 2*c859f2a7SLey Foon Tan * Copyright (C) 2012 Altera Corporation <www.altera.com> 3*c859f2a7SLey Foon Tan * 4*c859f2a7SLey Foon Tan * SPDX-License-Identifier: GPL-2.0+ 5*c859f2a7SLey Foon Tan */ 6*c859f2a7SLey Foon Tan 7*c859f2a7SLey Foon Tan #include <common.h> 8*c859f2a7SLey Foon Tan #include <asm/io.h> 9*c859f2a7SLey Foon Tan #include <asm/pl310.h> 10*c859f2a7SLey Foon Tan #include <asm/u-boot.h> 11*c859f2a7SLey Foon Tan #include <asm/utils.h> 12*c859f2a7SLey Foon Tan #include <image.h> 13*c859f2a7SLey Foon Tan #include <asm/arch/reset_manager.h> 14*c859f2a7SLey Foon Tan #include <spl.h> 15*c859f2a7SLey Foon Tan #include <asm/arch/system_manager.h> 16*c859f2a7SLey Foon Tan #include <asm/arch/freeze_controller.h> 17*c859f2a7SLey Foon Tan #include <asm/arch/clock_manager.h> 18*c859f2a7SLey Foon Tan #include <asm/arch/scan_manager.h> 19*c859f2a7SLey Foon Tan #include <asm/arch/sdram.h> 20*c859f2a7SLey Foon Tan #include <asm/arch/scu.h> 21*c859f2a7SLey Foon Tan #include <asm/arch/nic301.h> 22*c859f2a7SLey Foon Tan #include <asm/sections.h> 23*c859f2a7SLey Foon Tan #include <fdtdec.h> 24*c859f2a7SLey Foon Tan #include <watchdog.h> 25*c859f2a7SLey Foon Tan #include <asm/arch/pinmux.h> 26*c859f2a7SLey Foon Tan 27*c859f2a7SLey Foon Tan DECLARE_GLOBAL_DATA_PTR; 28*c859f2a7SLey Foon Tan 29*c859f2a7SLey Foon Tan static const struct socfpga_system_manager *sysmgr_regs = 30*c859f2a7SLey Foon Tan (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; 31*c859f2a7SLey Foon Tan 32*c859f2a7SLey Foon Tan u32 spl_boot_device(void) 33*c859f2a7SLey Foon Tan { 34*c859f2a7SLey Foon Tan const u32 bsel = readl(&sysmgr_regs->bootinfo); 35*c859f2a7SLey Foon Tan 36*c859f2a7SLey Foon Tan switch (SYSMGR_GET_BOOTINFO_BSEL(bsel)) { 37*c859f2a7SLey Foon Tan case 0x1: /* FPGA (HPS2FPGA Bridge) */ 38*c859f2a7SLey Foon Tan return BOOT_DEVICE_RAM; 39*c859f2a7SLey Foon Tan case 0x2: /* NAND Flash (1.8V) */ 40*c859f2a7SLey Foon Tan case 0x3: /* NAND Flash (3.0V) */ 41*c859f2a7SLey Foon Tan socfpga_per_reset(SOCFPGA_RESET(NAND), 0); 42*c859f2a7SLey Foon Tan return BOOT_DEVICE_NAND; 43*c859f2a7SLey Foon Tan case 0x4: /* SD/MMC External Transceiver (1.8V) */ 44*c859f2a7SLey Foon Tan case 0x5: /* SD/MMC Internal Transceiver (3.0V) */ 45*c859f2a7SLey Foon Tan socfpga_per_reset(SOCFPGA_RESET(SDMMC), 0); 46*c859f2a7SLey Foon Tan socfpga_per_reset(SOCFPGA_RESET(DMA), 0); 47*c859f2a7SLey Foon Tan return BOOT_DEVICE_MMC1; 48*c859f2a7SLey Foon Tan case 0x6: /* QSPI Flash (1.8V) */ 49*c859f2a7SLey Foon Tan case 0x7: /* QSPI Flash (3.0V) */ 50*c859f2a7SLey Foon Tan socfpga_per_reset(SOCFPGA_RESET(QSPI), 0); 51*c859f2a7SLey Foon Tan return BOOT_DEVICE_SPI; 52*c859f2a7SLey Foon Tan default: 53*c859f2a7SLey Foon Tan printf("Invalid boot device (bsel=%08x)!\n", bsel); 54*c859f2a7SLey Foon Tan hang(); 55*c859f2a7SLey Foon Tan } 56*c859f2a7SLey Foon Tan } 57*c859f2a7SLey Foon Tan 58*c859f2a7SLey Foon Tan #ifdef CONFIG_SPL_MMC_SUPPORT 59*c859f2a7SLey Foon Tan u32 spl_boot_mode(const u32 boot_device) 60*c859f2a7SLey Foon Tan { 61*c859f2a7SLey Foon Tan #if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT) 62*c859f2a7SLey Foon Tan return MMCSD_MODE_FS; 63*c859f2a7SLey Foon Tan #else 64*c859f2a7SLey Foon Tan return MMCSD_MODE_RAW; 65*c859f2a7SLey Foon Tan #endif 66*c859f2a7SLey Foon Tan } 67*c859f2a7SLey Foon Tan #endif 68*c859f2a7SLey Foon Tan 69*c859f2a7SLey Foon Tan void spl_board_init(void) 70*c859f2a7SLey Foon Tan { 71*c859f2a7SLey Foon Tan /* configuring the clock based on handoff */ 72*c859f2a7SLey Foon Tan cm_basic_init(gd->fdt_blob); 73*c859f2a7SLey Foon Tan WATCHDOG_RESET(); 74*c859f2a7SLey Foon Tan 75*c859f2a7SLey Foon Tan config_dedicated_pins(gd->fdt_blob); 76*c859f2a7SLey Foon Tan WATCHDOG_RESET(); 77*c859f2a7SLey Foon Tan 78*c859f2a7SLey Foon Tan /* Release UART from reset */ 79*c859f2a7SLey Foon Tan socfpga_reset_uart(0); 80*c859f2a7SLey Foon Tan 81*c859f2a7SLey Foon Tan /* enable console uart printing */ 82*c859f2a7SLey Foon Tan preloader_console_init(); 83*c859f2a7SLey Foon Tan } 84*c859f2a7SLey Foon Tan 85*c859f2a7SLey Foon Tan void board_init_f(ulong dummy) 86*c859f2a7SLey Foon Tan { 87*c859f2a7SLey Foon Tan /* 88*c859f2a7SLey Foon Tan * Configure Clock Manager to use intosc clock instead external osc to 89*c859f2a7SLey Foon Tan * ensure success watchdog operation. We do it as early as possible. 90*c859f2a7SLey Foon Tan */ 91*c859f2a7SLey Foon Tan cm_use_intosc(); 92*c859f2a7SLey Foon Tan 93*c859f2a7SLey Foon Tan socfpga_watchdog_disable(); 94*c859f2a7SLey Foon Tan 95*c859f2a7SLey Foon Tan arch_early_init_r(); 96*c859f2a7SLey Foon Tan 97*c859f2a7SLey Foon Tan #ifdef CONFIG_HW_WATCHDOG 98*c859f2a7SLey Foon Tan /* release osc1 watchdog timer 0 from reset */ 99*c859f2a7SLey Foon Tan socfpga_reset_deassert_osc1wd0(); 100*c859f2a7SLey Foon Tan 101*c859f2a7SLey Foon Tan /* reconfigure and enable the watchdog */ 102*c859f2a7SLey Foon Tan hw_watchdog_init(); 103*c859f2a7SLey Foon Tan WATCHDOG_RESET(); 104*c859f2a7SLey Foon Tan #endif /* CONFIG_HW_WATCHDOG */ 105*c859f2a7SLey Foon Tan } 106