1914bb7eaSTom Rini // SPDX-License-Identifier: GPL-2.0+ 2c859f2a7SLey Foon Tan /* 3c859f2a7SLey Foon Tan * Copyright (C) 2012 Altera Corporation <www.altera.com> 4c859f2a7SLey Foon Tan */ 5c859f2a7SLey Foon Tan 6c859f2a7SLey Foon Tan #include <common.h> 7c859f2a7SLey Foon Tan #include <asm/io.h> 8c859f2a7SLey Foon Tan #include <asm/pl310.h> 9c859f2a7SLey Foon Tan #include <asm/u-boot.h> 10c859f2a7SLey Foon Tan #include <asm/utils.h> 11c859f2a7SLey Foon Tan #include <image.h> 12c859f2a7SLey Foon Tan #include <asm/arch/reset_manager.h> 13c859f2a7SLey Foon Tan #include <spl.h> 14c859f2a7SLey Foon Tan #include <asm/arch/system_manager.h> 15c859f2a7SLey Foon Tan #include <asm/arch/freeze_controller.h> 16c859f2a7SLey Foon Tan #include <asm/arch/clock_manager.h> 17c859f2a7SLey Foon Tan #include <asm/arch/scan_manager.h> 18c859f2a7SLey Foon Tan #include <asm/arch/sdram.h> 19c859f2a7SLey Foon Tan #include <asm/arch/scu.h> 20af74658eSMarek Vasut #include <asm/arch/misc.h> 21c859f2a7SLey Foon Tan #include <asm/arch/nic301.h> 22c859f2a7SLey Foon Tan #include <asm/sections.h> 23c859f2a7SLey Foon Tan #include <fdtdec.h> 24c859f2a7SLey Foon Tan #include <watchdog.h> 25c859f2a7SLey Foon Tan #include <asm/arch/pinmux.h> 26c859f2a7SLey Foon Tan 27c859f2a7SLey Foon Tan DECLARE_GLOBAL_DATA_PTR; 28c859f2a7SLey Foon Tan 29c859f2a7SLey Foon Tan static const struct socfpga_system_manager *sysmgr_regs = 30c859f2a7SLey Foon Tan (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; 31c859f2a7SLey Foon Tan spl_boot_device(void)32c859f2a7SLey Foon Tanu32 spl_boot_device(void) 33c859f2a7SLey Foon Tan { 34c859f2a7SLey Foon Tan const u32 bsel = readl(&sysmgr_regs->bootinfo); 35c859f2a7SLey Foon Tan 36c859f2a7SLey Foon Tan switch (SYSMGR_GET_BOOTINFO_BSEL(bsel)) { 37c859f2a7SLey Foon Tan case 0x1: /* FPGA (HPS2FPGA Bridge) */ 38c859f2a7SLey Foon Tan return BOOT_DEVICE_RAM; 39c859f2a7SLey Foon Tan case 0x2: /* NAND Flash (1.8V) */ 40c859f2a7SLey Foon Tan case 0x3: /* NAND Flash (3.0V) */ 41c859f2a7SLey Foon Tan socfpga_per_reset(SOCFPGA_RESET(NAND), 0); 42c859f2a7SLey Foon Tan return BOOT_DEVICE_NAND; 43c859f2a7SLey Foon Tan case 0x4: /* SD/MMC External Transceiver (1.8V) */ 44c859f2a7SLey Foon Tan case 0x5: /* SD/MMC Internal Transceiver (3.0V) */ 45c859f2a7SLey Foon Tan socfpga_per_reset(SOCFPGA_RESET(SDMMC), 0); 46c859f2a7SLey Foon Tan socfpga_per_reset(SOCFPGA_RESET(DMA), 0); 47c859f2a7SLey Foon Tan return BOOT_DEVICE_MMC1; 48c859f2a7SLey Foon Tan case 0x6: /* QSPI Flash (1.8V) */ 49c859f2a7SLey Foon Tan case 0x7: /* QSPI Flash (3.0V) */ 50c859f2a7SLey Foon Tan socfpga_per_reset(SOCFPGA_RESET(QSPI), 0); 51c859f2a7SLey Foon Tan return BOOT_DEVICE_SPI; 52c859f2a7SLey Foon Tan default: 53c859f2a7SLey Foon Tan printf("Invalid boot device (bsel=%08x)!\n", bsel); 54c859f2a7SLey Foon Tan hang(); 55c859f2a7SLey Foon Tan } 56c859f2a7SLey Foon Tan } 57c859f2a7SLey Foon Tan 58c859f2a7SLey Foon Tan #ifdef CONFIG_SPL_MMC_SUPPORT spl_boot_mode(const u32 boot_device)59c859f2a7SLey Foon Tanu32 spl_boot_mode(const u32 boot_device) 60c859f2a7SLey Foon Tan { 61f4b40924STien Fong Chee #if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4) 62c859f2a7SLey Foon Tan return MMCSD_MODE_FS; 63c859f2a7SLey Foon Tan #else 64c859f2a7SLey Foon Tan return MMCSD_MODE_RAW; 65c859f2a7SLey Foon Tan #endif 66c859f2a7SLey Foon Tan } 67c859f2a7SLey Foon Tan #endif 68c859f2a7SLey Foon Tan spl_board_init(void)69c859f2a7SLey Foon Tanvoid spl_board_init(void) 70c859f2a7SLey Foon Tan { 71c859f2a7SLey Foon Tan /* enable console uart printing */ 72c859f2a7SLey Foon Tan preloader_console_init(); 73af74658eSMarek Vasut WATCHDOG_RESET(); 74af74658eSMarek Vasut 750b8f6378SMarek Vasut arch_early_init_r(); 76c859f2a7SLey Foon Tan } 77c859f2a7SLey Foon Tan board_init_f(ulong dummy)78c859f2a7SLey Foon Tanvoid board_init_f(ulong dummy) 79c859f2a7SLey Foon Tan { 80*7544ad03SMarek Vasut dcache_disable(); 81*7544ad03SMarek Vasut 820b8f6378SMarek Vasut socfpga_init_security_policies(); 830b8f6378SMarek Vasut socfpga_sdram_remap_zero(); 84c859f2a7SLey Foon Tan 850b8f6378SMarek Vasut /* Assert reset to all except L4WD0 and L4TIMER0 */ 860b8f6378SMarek Vasut socfpga_per_reset_all(); 87c859f2a7SLey Foon Tan socfpga_watchdog_disable(); 88c859f2a7SLey Foon Tan 890b8f6378SMarek Vasut spl_early_init(); 900b8f6378SMarek Vasut 910b8f6378SMarek Vasut /* Configure the clock based on handoff */ 920b8f6378SMarek Vasut cm_basic_init(gd->fdt_blob); 93c859f2a7SLey Foon Tan 94c859f2a7SLey Foon Tan #ifdef CONFIG_HW_WATCHDOG 95c859f2a7SLey Foon Tan /* release osc1 watchdog timer 0 from reset */ 96c859f2a7SLey Foon Tan socfpga_reset_deassert_osc1wd0(); 97c859f2a7SLey Foon Tan 98c859f2a7SLey Foon Tan /* reconfigure and enable the watchdog */ 99c859f2a7SLey Foon Tan hw_watchdog_init(); 100c859f2a7SLey Foon Tan WATCHDOG_RESET(); 101c859f2a7SLey Foon Tan #endif /* CONFIG_HW_WATCHDOG */ 1020b8f6378SMarek Vasut 1030b8f6378SMarek Vasut config_dedicated_pins(gd->fdt_blob); 1040b8f6378SMarek Vasut WATCHDOG_RESET(); 105c859f2a7SLey Foon Tan } 106