1 /*
2  *  Copyright (C) 2013 Altera Corporation <www.altera.com>
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 
8 #include <common.h>
9 #include <asm/io.h>
10 #include <asm/arch/fpga_manager.h>
11 #include <asm/arch/reset_manager.h>
12 #include <asm/arch/system_manager.h>
13 
14 DECLARE_GLOBAL_DATA_PTR;
15 
16 static const struct socfpga_reset_manager *reset_manager_base =
17 		(void *)SOCFPGA_RSTMGR_ADDRESS;
18 static const struct socfpga_system_manager *sysmgr_regs =
19 	(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
20 
21 /* Assert or de-assert SoCFPGA reset manager reset. */
22 void socfpga_per_reset(u32 reset, int set)
23 {
24 	const u32 *reg;
25 	u32 rstmgr_bank = RSTMGR_BANK(reset);
26 
27 	switch (rstmgr_bank) {
28 	case 0:
29 		reg = &reset_manager_base->mpu_mod_reset;
30 		break;
31 	case 1:
32 		reg = &reset_manager_base->per_mod_reset;
33 		break;
34 	case 2:
35 		reg = &reset_manager_base->per2_mod_reset;
36 		break;
37 	case 3:
38 		reg = &reset_manager_base->brg_mod_reset;
39 		break;
40 	case 4:
41 		reg = &reset_manager_base->misc_mod_reset;
42 		break;
43 
44 	default:
45 		return;
46 	}
47 
48 	if (set)
49 		setbits_le32(reg, 1 << RSTMGR_RESET(reset));
50 	else
51 		clrbits_le32(reg, 1 << RSTMGR_RESET(reset));
52 }
53 
54 /*
55  * Assert reset on every peripheral but L4WD0.
56  * Watchdog must be kept intact to prevent glitches
57  * and/or hangs.
58  */
59 void socfpga_per_reset_all(void)
60 {
61 	const u32 l4wd0 = 1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0));
62 
63 	writel(~l4wd0, &reset_manager_base->per_mod_reset);
64 	writel(0xffffffff, &reset_manager_base->per2_mod_reset);
65 }
66 
67 /*
68  * Release peripherals from reset based on handoff
69  */
70 void reset_deassert_peripherals_handoff(void)
71 {
72 	writel(0, &reset_manager_base->per_mod_reset);
73 }
74 
75 #if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
76 void socfpga_bridges_reset(int enable)
77 {
78 	/* For SoCFPGA-VT, this is NOP. */
79 	return;
80 }
81 #else
82 
83 #define L3REGS_REMAP_LWHPS2FPGA_MASK	0x10
84 #define L3REGS_REMAP_HPS2FPGA_MASK	0x08
85 #define L3REGS_REMAP_OCRAM_MASK		0x01
86 
87 void socfpga_bridges_reset(int enable)
88 {
89 	const u32 l3mask = L3REGS_REMAP_LWHPS2FPGA_MASK |
90 				L3REGS_REMAP_HPS2FPGA_MASK |
91 				L3REGS_REMAP_OCRAM_MASK;
92 
93 	if (enable) {
94 		/* brdmodrst */
95 		writel(0xffffffff, &reset_manager_base->brg_mod_reset);
96 	} else {
97 		writel(0, &sysmgr_regs->iswgrp_handoff[0]);
98 		writel(l3mask, &sysmgr_regs->iswgrp_handoff[1]);
99 
100 		/* Check signal from FPGA. */
101 		if (!fpgamgr_test_fpga_ready()) {
102 			/* FPGA not ready, do nothing. We allow system to boot
103 			 * without FPGA ready. So, return 0 instead of error. */
104 			printf("%s: FPGA not ready, aborting.\n", __func__);
105 			return;
106 		}
107 
108 		/* brdmodrst */
109 		writel(0, &reset_manager_base->brg_mod_reset);
110 
111 		/* Remap the bridges into memory map */
112 		writel(l3mask, SOCFPGA_L3REGS_ADDRESS);
113 	}
114 	return;
115 }
116 #endif
117