1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  *  Copyright (C) 2013 Altera Corporation <www.altera.com>
4  */
5 
6 
7 #include <common.h>
8 #include <asm/io.h>
9 #include <asm/arch/fpga_manager.h>
10 #include <asm/arch/reset_manager.h>
11 #include <asm/arch/system_manager.h>
12 
13 static const struct socfpga_reset_manager *reset_manager_base =
14 		(void *)SOCFPGA_RSTMGR_ADDRESS;
15 static const struct socfpga_system_manager *sysmgr_regs =
16 	(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
17 
18 /* Assert or de-assert SoCFPGA reset manager reset. */
19 void socfpga_per_reset(u32 reset, int set)
20 {
21 	const u32 *reg;
22 	u32 rstmgr_bank = RSTMGR_BANK(reset);
23 
24 	switch (rstmgr_bank) {
25 	case 0:
26 		reg = &reset_manager_base->mpu_mod_reset;
27 		break;
28 	case 1:
29 		reg = &reset_manager_base->per_mod_reset;
30 		break;
31 	case 2:
32 		reg = &reset_manager_base->per2_mod_reset;
33 		break;
34 	case 3:
35 		reg = &reset_manager_base->brg_mod_reset;
36 		break;
37 	case 4:
38 		reg = &reset_manager_base->misc_mod_reset;
39 		break;
40 
41 	default:
42 		return;
43 	}
44 
45 	if (set)
46 		setbits_le32(reg, 1 << RSTMGR_RESET(reset));
47 	else
48 		clrbits_le32(reg, 1 << RSTMGR_RESET(reset));
49 }
50 
51 /*
52  * Assert reset on every peripheral but L4WD0.
53  * Watchdog must be kept intact to prevent glitches
54  * and/or hangs.
55  */
56 void socfpga_per_reset_all(void)
57 {
58 	const u32 l4wd0 = 1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0));
59 
60 	writel(~l4wd0, &reset_manager_base->per_mod_reset);
61 	writel(0xffffffff, &reset_manager_base->per2_mod_reset);
62 }
63 
64 /*
65  * Release peripherals from reset based on handoff
66  */
67 void reset_deassert_peripherals_handoff(void)
68 {
69 	writel(0, &reset_manager_base->per_mod_reset);
70 }
71 
72 #define L3REGS_REMAP_LWHPS2FPGA_MASK	0x10
73 #define L3REGS_REMAP_HPS2FPGA_MASK	0x08
74 #define L3REGS_REMAP_OCRAM_MASK		0x01
75 
76 void socfpga_bridges_reset(int enable)
77 {
78 	const u32 l3mask = L3REGS_REMAP_LWHPS2FPGA_MASK |
79 				L3REGS_REMAP_HPS2FPGA_MASK |
80 				L3REGS_REMAP_OCRAM_MASK;
81 
82 	if (enable) {
83 		/* brdmodrst */
84 		writel(0xffffffff, &reset_manager_base->brg_mod_reset);
85 	} else {
86 		writel(0, &sysmgr_regs->iswgrp_handoff[0]);
87 		writel(l3mask, &sysmgr_regs->iswgrp_handoff[1]);
88 
89 		/* Check signal from FPGA. */
90 		if (!fpgamgr_test_fpga_ready()) {
91 			/* FPGA not ready, do nothing. We allow system to boot
92 			 * without FPGA ready. So, return 0 instead of error. */
93 			printf("%s: FPGA not ready, aborting.\n", __func__);
94 			return;
95 		}
96 
97 		/* brdmodrst */
98 		writel(0, &reset_manager_base->brg_mod_reset);
99 
100 		/* Remap the bridges into memory map */
101 		writel(l3mask, SOCFPGA_L3REGS_ADDRESS);
102 	}
103 	return;
104 }
105