1#!/bin/sh 2 3# 4# Process iocsr_config_*.[ch] 5# $1: SoC type 6# $2: Input handoff directory 7# $3: Input BSP Generated directory 8# $4: Output directory 9# 10process_iocsr_config() { 11 soc="$1" 12 in_qts_dir="$2" 13 in_bsp_dir="$3" 14 out_dir="$4" 15 16 ( 17 cat << EOF 18/* 19 * Altera SoCFPGA IOCSR configuration 20 * 21 * SPDX-License-Identifier: BSD-3-Clause 22 */ 23 24#ifndef __SOCFPGA_IOCSR_CONFIG_H__ 25#define __SOCFPGA_IOCSR_CONFIG_H__ 26 27EOF 28 29 # Retrieve the scan chain lengths 30 grep 'CONFIG_HPS_IOCSR_SCANCHAIN[0-9]\+_LENGTH' \ 31 ${in_bsp_dir}/generated/iocsr_config_${soc}.h | tr -d "()" 32 33 echo "" 34 35 # Retrieve the scan chain config and zap the ad-hoc length encoding 36 sed -n '/^const/ !b; :next {/^const/ s/(.*)//;p;n;b next}' \ 37 ${in_bsp_dir}/generated/iocsr_config_${soc}.c 38 39 cat << EOF 40 41#endif /* __SOCFPGA_IOCSR_CONFIG_H__ */ 42EOF 43 ) > "${out_dir}/iocsr_config.h" 44} 45 46# 47# Process pinmux_config_*.c (and ignore pinmux_config.h) 48# $1: SoC type 49# $2: Input directory 50# $3: Output directory 51# 52process_pinmux_config() { 53 soc="$1" 54 in_qts_dir="$2" 55 in_bsp_dir="$3" 56 out_dir="$4" 57 58 ( 59 cat << EOF 60/* 61 * Altera SoCFPGA PinMux configuration 62 * 63 * SPDX-License-Identifier: BSD-3-Clause 64 */ 65 66#ifndef __SOCFPGA_PINMUX_CONFIG_H__ 67#define __SOCFPGA_PINMUX_CONFIG_H__ 68 69EOF 70 71 # Retrieve the pinmux config and zap the ad-hoc length encoding 72 sed -n '/^unsigned/ !b; :next {/^unsigned/ {s/\[.*\]/[]/;s/unsigned long/const u8/};p;n;b next}' \ 73 ${in_bsp_dir}/generated/pinmux_config_${soc}.c 74 75 cat << EOF 76 77#endif /* __SOCFPGA_PINMUX_CONFIG_H__ */ 78EOF 79 ) > "${out_dir}/pinmux_config.h" 80} 81 82# 83# Process pll_config.h 84# $1: SoC type (not used) 85# $2: Input directory 86# $3: Output directory 87# 88process_pll_config() { 89 soc="$1" 90 in_qts_dir="$2" 91 in_bsp_dir="$3" 92 out_dir="$4" 93 94 ( 95 cat << EOF 96/* 97 * Altera SoCFPGA Clock and PLL configuration 98 * 99 * SPDX-License-Identifier: BSD-3-Clause 100 */ 101 102#ifndef __SOCFPGA_PLL_CONFIG_H__ 103#define __SOCFPGA_PLL_CONFIG_H__ 104 105EOF 106 107 # Retrieve the pll config and zap parenthesis 108 sed -n '/CONFIG_HPS/ !b; :next {/CONFIG_HPS/ s/[()]//g;/endif/ b;p;n;b next}' \ 109 ${in_bsp_dir}/generated/pll_config.h 110 111 cat << EOF 112 113#endif /* __SOCFPGA_PLL_CONFIG_H__ */ 114EOF 115 ) > "${out_dir}/pll_config.h" 116} 117 118# 119# Filter out only the macros which are actually used by the code 120# 121grep_sdram_config() { 122 egrep "#define (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT|CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES|CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES|CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ|CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH|CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH|CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN|CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK|CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL|CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA|CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH|CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH|CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP|CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP|CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP|CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP|CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR|CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN|CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST|CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE|CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC|CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46|CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0|CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0|CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32|CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0|CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4|CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36|CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0|CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32|CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64|RW_MGR_ACTIVATE_0_AND_1|RW_MGR_ACTIVATE_0_AND_1_WAIT1|RW_MGR_ACTIVATE_0_AND_1_WAIT2|RW_MGR_ACTIVATE_1|RW_MGR_CLEAR_DQS_ENABLE|RW_MGR_GUARANTEED_READ|RW_MGR_GUARANTEED_READ_CONT|RW_MGR_GUARANTEED_WRITE|RW_MGR_GUARANTEED_WRITE_WAIT0|RW_MGR_GUARANTEED_WRITE_WAIT1|RW_MGR_GUARANTEED_WRITE_WAIT2|RW_MGR_GUARANTEED_WRITE_WAIT3|RW_MGR_IDLE|RW_MGR_IDLE_LOOP1|RW_MGR_IDLE_LOOP2|RW_MGR_INIT_RESET_0_CKE_0|RW_MGR_INIT_RESET_1_CKE_0|RW_MGR_LFSR_WR_RD_BANK_0|RW_MGR_LFSR_WR_RD_BANK_0_DATA|RW_MGR_LFSR_WR_RD_BANK_0_DQS|RW_MGR_LFSR_WR_RD_BANK_0_NOP|RW_MGR_LFSR_WR_RD_BANK_0_WAIT|RW_MGR_LFSR_WR_RD_BANK_0_WL_1|RW_MGR_LFSR_WR_RD_DM_BANK_0|RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA|RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS|RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP|RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT|RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1|RW_MGR_MRS0_DLL_RESET|RW_MGR_MRS0_DLL_RESET_MIRR|RW_MGR_MRS0_USER|RW_MGR_MRS0_USER_MIRR|RW_MGR_MRS1|RW_MGR_MRS1_MIRR|RW_MGR_MRS2|RW_MGR_MRS2_MIRR|RW_MGR_MRS3|RW_MGR_MRS3_MIRR|RW_MGR_PRECHARGE_ALL|RW_MGR_READ_B2B|RW_MGR_READ_B2B_WAIT1|RW_MGR_READ_B2B_WAIT2|RW_MGR_REFRESH_ALL|RW_MGR_RETURN|RW_MGR_SGLE_READ|RW_MGR_ZQCL|RW_MGR_TRUE_MEM_DATA_MASK_WIDTH|RW_MGR_MEM_ADDRESS_MIRRORING|RW_MGR_MEM_DATA_MASK_WIDTH|RW_MGR_MEM_DATA_WIDTH|RW_MGR_MEM_DQ_PER_READ_DQS|RW_MGR_MEM_DQ_PER_WRITE_DQS|RW_MGR_MEM_IF_READ_DQS_WIDTH|RW_MGR_MEM_IF_WRITE_DQS_WIDTH|RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM|RW_MGR_MEM_NUMBER_OF_RANKS|RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS|RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS|IO_DELAY_PER_DCHAIN_TAP|IO_DELAY_PER_DQS_EN_DCHAIN_TAP|IO_DELAY_PER_OPA_TAP|IO_DLL_CHAIN_LENGTH|IO_DQDQS_OUT_PHASE_MAX|IO_DQS_EN_DELAY_MAX|IO_DQS_EN_DELAY_OFFSET|IO_DQS_EN_PHASE_MAX|IO_DQS_IN_DELAY_MAX|IO_DQS_IN_RESERVE|IO_DQS_OUT_RESERVE|IO_IO_IN_DELAY_MAX|IO_IO_OUT1_DELAY_MAX|IO_IO_OUT2_DELAY_MAX|IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS|AFI_RATE_RATIO|CALIB_LFIFO_OFFSET|CALIB_VFIFO_OFFSET|ENABLE_SUPER_QUICK_CALIBRATION|MAX_LATENCY_COUNT_WIDTH|READ_VALID_FIFO_SIZE|REG_FILE_INIT_SEQ_SIGNATURE|TINIT_CNTR0_VAL|TINIT_CNTR1_VAL|TINIT_CNTR2_VAL|TRESET_CNTR0_VAL|TRESET_CNTR1_VAL|TRESET_CNTR2_VAL)[[:space:]]" 123} 124 125# 126# Process sdram_config.h, sequencer_auto*h and sequencer_defines.h 127# $1: SoC type (not used) 128# $2: Input directory 129# $3: Output directory 130# 131process_sdram_config() { 132 soc="$1" 133 in_qts_dir="$2" 134 in_bsp_dir="$3" 135 out_dir="$4" 136 137 ( 138 cat << EOF 139/* 140 * Altera SoCFPGA SDRAM configuration 141 * 142 * SPDX-License-Identifier: BSD-3-Clause 143 */ 144 145#ifndef __SOCFPGA_SDRAM_CONFIG_H__ 146#define __SOCFPGA_SDRAM_CONFIG_H__ 147 148EOF 149 150 echo "/* SDRAM configuration */" 151 # Retrieve the sdram config, zap broken lines and zap parenthesis 152 sed -n "/\\\\$/ {N;s/ \\\\\n/\t/};p" \ 153 ${in_bsp_dir}/generated/sdram/sdram_config.h | 154 sed -n '/CONFIG_HPS/ !b; :next {/CONFIG_HPS/ s/[()]//g;/endif/ b;p;n;b next}' | 155 sort -u | grep_sdram_config 156 157 echo "" 158 echo "/* Sequencer auto configuration */" 159 sed -n "/__RW_MGR/ {s/__//;s/ \+\([^ ]\+\)$/\t\1/p}" \ 160 ${in_qts_dir}/hps_isw_handoff/*/sequencer_auto.h | 161 sort -u | grep_sdram_config 162 163 echo "" 164 echo "/* Sequencer defines configuration */" 165 sed -n "/^#define [^_]/ {s/__//;s/ \+\([^ ]\+\)$/\t\1/p}" \ 166 ${in_qts_dir}/hps_isw_handoff/*/sequencer_defines.h | 167 sort -u | grep_sdram_config 168 169 echo "" 170 echo "/* Sequencer ac_rom_init configuration */" 171 sed -n '/^const.*\[/ !b; :next {/^const.*\[/ {N;s/\n//;s/alt_u32/u32/;s/\[.*\]/[]/};/endif/ b;p;n;b next}'\ 172 ${in_qts_dir}/hps_isw_handoff/*/sequencer_auto_ac_init.c 173 174 echo "" 175 echo "/* Sequencer inst_rom_init configuration */" 176 sed -n '/^const.*\[/ !b; :next {/^const.*\[/ {N;s/\n//;s/alt_u32/u32/;s/\[.*\]/[]/};/endif/ b;p;n;b next}'\ 177 ${in_qts_dir}/hps_isw_handoff/*/sequencer_auto_inst_init.c 178 179 cat << EOF 180 181#endif /* __SOCFPGA_SDRAM_CONFIG_H__ */ 182EOF 183 ) > "${out_dir}/sdram_config.h" 184} 185 186usage() { 187 echo "$0 [soc_type] [input_qts_dir] [input_bsp_dir] [output_dir]" 188 echo "Process QTS-generated headers into U-Boot compatible ones." 189 echo "" 190 echo " soc_type - Type of SoC, either 'cyclone5' or 'arria5'." 191 echo " input_qts_dir - Directory with compiled Quartus project" 192 echo " and containing the Quartus project file (QPF)." 193 echo " input_bsp_dir - Directory with generated bsp containing" 194 echo " the settings.bsp file." 195 echo " output_dir - Directory to store the U-Boot compatible" 196 echo " headers." 197 echo "" 198} 199 200soc="$1" 201in_qts_dir="$2" 202in_bsp_dir="$3" 203out_dir="$4" 204 205if [ "$#" -ne 4 ] ; then 206 usage 207 exit 1 208fi 209 210if [ ! -d "${in_qts_dir}" -o ! -d "${in_bsp_dir}" -o \ 211 ! -d "${out_dir}" -o -z "${soc}" ] ; then 212 usage 213 exit 3 214fi 215 216process_iocsr_config "${soc}" "${in_qts_dir}" "${in_bsp_dir}" "${out_dir}" 217process_pinmux_config "${soc}" "${in_qts_dir}" "${in_bsp_dir}" "${out_dir}" 218process_pll_config "${soc}" "${in_qts_dir}" "${in_bsp_dir}" "${out_dir}" 219process_sdram_config "${soc}" "${in_qts_dir}" "${in_bsp_dir}" "${out_dir}" 220