1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
4  *
5  */
6 
7 #include <altera.h>
8 #include <common.h>
9 #include <errno.h>
10 #include <fdtdec.h>
11 #include <miiphy.h>
12 #include <netdev.h>
13 #include <asm/io.h>
14 #include <asm/arch/reset_manager.h>
15 #include <asm/arch/system_manager.h>
16 #include <asm/arch/misc.h>
17 #include <asm/pl310.h>
18 #include <linux/libfdt.h>
19 
20 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
21 
22 DECLARE_GLOBAL_DATA_PTR;
23 
24 static struct socfpga_system_manager *sysmgr_regs =
25 	(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
26 
27 /*
28  * DesignWare Ethernet initialization
29  */
30 #ifdef CONFIG_ETH_DESIGNWARE
31 
32 static u32 socfpga_phymode_setup(u32 gmac_index, const char *phymode)
33 {
34 	u32 modereg;
35 
36 	if (!phymode)
37 		return -EINVAL;
38 
39 	if (!strcmp(phymode, "mii") || !strcmp(phymode, "gmii") ||
40 	    !strcmp(phymode, "sgmii"))
41 		modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;
42 	else if (!strcmp(phymode, "rgmii"))
43 		modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII;
44 	else if (!strcmp(phymode, "rmii"))
45 		modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII;
46 	else
47 		return -EINVAL;
48 
49 	clrsetbits_le32(&sysmgr_regs->emac0 + gmac_index,
50 			SYSMGR_EMACGRP_CTRL_PHYSEL_MASK,
51 			modereg);
52 
53 	return 0;
54 }
55 
56 static int socfpga_set_phymode(void)
57 {
58 	const void *fdt = gd->fdt_blob;
59 	struct fdtdec_phandle_args args;
60 	const char *phy_mode;
61 	u32 gmac_index;
62 	int nodes[3];	/* Max. 3 GMACs */
63 	int ret, count;
64 	int i, node;
65 
66 	count = fdtdec_find_aliases_for_id(fdt, "ethernet",
67 					   COMPAT_ALTERA_SOCFPGA_DWMAC,
68 					   nodes, ARRAY_SIZE(nodes));
69 	for (i = 0; i < count; i++) {
70 		node = nodes[i];
71 		if (node <= 0)
72 			continue;
73 
74 		ret = fdtdec_parse_phandle_with_args(fdt, node, "resets",
75 						     "#reset-cells", 1, 0,
76 						     &args);
77 		if (ret || args.args_count != 1) {
78 			debug("GMAC%i: Failed to parse DT 'resets'!\n", i);
79 			continue;
80 		}
81 
82 		gmac_index = args.args[0] - EMAC0_RESET;
83 
84 		phy_mode = fdt_getprop(fdt, node, "phy-mode", NULL);
85 		ret = socfpga_phymode_setup(gmac_index, phy_mode);
86 		if (ret) {
87 			debug("GMAC%i: Failed to parse DT 'phy-mode'!\n", i);
88 			continue;
89 		}
90 	}
91 
92 	return 0;
93 }
94 #else
95 static int socfpga_set_phymode(void)
96 {
97 	return 0;
98 };
99 #endif
100 
101 /*
102  * Print CPU information
103  */
104 #if defined(CONFIG_DISPLAY_CPUINFO)
105 int print_cpuinfo(void)
106 {
107 	puts("CPU:   Intel FPGA SoCFPGA Platform (ARMv8 64bit Cortex-A53)\n");
108 
109 	return 0;
110 }
111 #endif
112 
113 #ifdef CONFIG_ARCH_MISC_INIT
114 int arch_misc_init(void)
115 {
116 	char qspi_string[13];
117 
118 	sprintf(qspi_string, "<0x%08x>", cm_get_qspi_controller_clk_hz());
119 	env_set("qspi_clock", qspi_string);
120 
121 	socfpga_set_phymode();
122 	return 0;
123 }
124 #endif
125 
126 int arch_early_init_r(void)
127 {
128 	return 0;
129 }
130 
131 void do_bridge_reset(int enable)
132 {
133 	socfpga_bridges_reset(enable);
134 }
135