1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2012-2017 Altera Corporation <www.altera.com> 4 */ 5 6 #include <common.h> 7 #include <asm/io.h> 8 #include <errno.h> 9 #include <fdtdec.h> 10 #include <linux/libfdt.h> 11 #include <altera.h> 12 #include <miiphy.h> 13 #include <netdev.h> 14 #include <watchdog.h> 15 #include <asm/arch/misc.h> 16 #include <asm/arch/reset_manager.h> 17 #include <asm/arch/scan_manager.h> 18 #include <asm/arch/sdram.h> 19 #include <asm/arch/system_manager.h> 20 #include <asm/arch/nic301.h> 21 #include <asm/arch/scu.h> 22 #include <asm/pl310.h> 23 24 #include <dt-bindings/reset/altr,rst-mgr.h> 25 26 DECLARE_GLOBAL_DATA_PTR; 27 28 static struct pl310_regs *const pl310 = 29 (struct pl310_regs *)CONFIG_SYS_PL310_BASE; 30 static struct socfpga_system_manager *sysmgr_regs = 31 (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; 32 static struct nic301_registers *nic301_regs = 33 (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS; 34 static struct scu_registers *scu_regs = 35 (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS; 36 37 /* 38 * FPGA programming support for SoC FPGA Cyclone V 39 */ 40 static Altera_desc altera_fpga[] = { 41 { 42 /* Family */ 43 Altera_SoCFPGA, 44 /* Interface type */ 45 fast_passive_parallel, 46 /* No limitation as additional data will be ignored */ 47 -1, 48 /* No device function table */ 49 NULL, 50 /* Base interface address specified in driver */ 51 NULL, 52 /* No cookie implementation */ 53 0 54 }, 55 }; 56 57 static const struct { 58 const u16 pn; 59 const char *name; 60 const char *var; 61 } socfpga_fpga_model[] = { 62 /* Cyclone V E */ 63 { 0x2b15, "Cyclone V, E/A2", "cv_e_a2" }, 64 { 0x2b05, "Cyclone V, E/A4", "cv_e_a4" }, 65 { 0x2b22, "Cyclone V, E/A5", "cv_e_a5" }, 66 { 0x2b13, "Cyclone V, E/A7", "cv_e_a7" }, 67 { 0x2b14, "Cyclone V, E/A9", "cv_e_a9" }, 68 /* Cyclone V GX/GT */ 69 { 0x2b01, "Cyclone V, GX/C3", "cv_gx_c3" }, 70 { 0x2b12, "Cyclone V, GX/C4", "cv_gx_c4" }, 71 { 0x2b02, "Cyclone V, GX/C5 or GT/D5", "cv_gx_c5" }, 72 { 0x2b03, "Cyclone V, GX/C7 or GT/D7", "cv_gx_c7" }, 73 { 0x2b04, "Cyclone V, GX/C9 or GT/D9", "cv_gx_c9" }, 74 /* Cyclone V SE/SX/ST */ 75 { 0x2d11, "Cyclone V, SE/A2 or SX/C2", "cv_se_a2" }, 76 { 0x2d01, "Cyclone V, SE/A4 or SX/C4", "cv_se_a4" }, 77 { 0x2d12, "Cyclone V, SE/A5 or SX/C5 or ST/D5", "cv_se_a5" }, 78 { 0x2d02, "Cyclone V, SE/A6 or SX/C6 or ST/D6", "cv_se_a6" }, 79 /* Arria V */ 80 { 0x2d03, "Arria V, D5", "av_d5" }, 81 }; 82 83 static int socfpga_fpga_id(const bool print_id) 84 { 85 const u32 altera_mi = 0x6e; 86 const u32 id = scan_mgr_get_fpga_id(); 87 88 const u32 lsb = id & 0x00000001; 89 const u32 mi = (id >> 1) & 0x000007ff; 90 const u32 pn = (id >> 12) & 0x0000ffff; 91 const u32 version = (id >> 28) & 0x0000000f; 92 int i; 93 94 if ((mi != altera_mi) || (lsb != 1)) { 95 printf("FPGA: Not Altera chip ID\n"); 96 return -EINVAL; 97 } 98 99 for (i = 0; i < ARRAY_SIZE(socfpga_fpga_model); i++) 100 if (pn == socfpga_fpga_model[i].pn) 101 break; 102 103 if (i == ARRAY_SIZE(socfpga_fpga_model)) { 104 printf("FPGA: Unknown Altera chip, ID 0x%08x\n", id); 105 return -EINVAL; 106 } 107 108 if (print_id) 109 printf("FPGA: Altera %s, version 0x%01x\n", 110 socfpga_fpga_model[i].name, version); 111 return i; 112 } 113 114 /* 115 * Print CPU information 116 */ 117 #if defined(CONFIG_DISPLAY_CPUINFO) 118 int print_cpuinfo(void) 119 { 120 const u32 bsel = 121 SYSMGR_GET_BOOTINFO_BSEL(readl(&sysmgr_regs->bootinfo)); 122 123 puts("CPU: Altera SoCFPGA Platform\n"); 124 socfpga_fpga_id(1); 125 126 printf("BOOT: %s\n", bsel_str[bsel].name); 127 return 0; 128 } 129 #endif 130 131 #ifdef CONFIG_ARCH_MISC_INIT 132 int arch_misc_init(void) 133 { 134 const u32 bsel = readl(&sysmgr_regs->bootinfo) & 0x7; 135 const int fpga_id = socfpga_fpga_id(0); 136 env_set("bootmode", bsel_str[bsel].mode); 137 if (fpga_id >= 0) 138 env_set("fpgatype", socfpga_fpga_model[fpga_id].var); 139 return 0; 140 } 141 #endif 142 143 /* 144 * Convert all NIC-301 AMBA slaves from secure to non-secure 145 */ 146 static void socfpga_nic301_slave_ns(void) 147 { 148 writel(0x1, &nic301_regs->lwhps2fpgaregs); 149 writel(0x1, &nic301_regs->hps2fpgaregs); 150 writel(0x1, &nic301_regs->acp); 151 writel(0x1, &nic301_regs->rom); 152 writel(0x1, &nic301_regs->ocram); 153 writel(0x1, &nic301_regs->sdrdata); 154 } 155 156 void socfpga_sdram_remap_zero(void) 157 { 158 u32 remap; 159 160 socfpga_nic301_slave_ns(); 161 162 /* 163 * Private components security: 164 * U-Boot : configure private timer, global timer and cpu component 165 * access as non secure for kernel stage (as required by Linux) 166 */ 167 setbits_le32(&scu_regs->sacr, 0xfff); 168 169 /* Configure the L2 controller to make SDRAM start at 0 */ 170 remap = 0x1; /* remap.mpuzero */ 171 /* Keep fpga bridge enabled when running from FPGA onchip RAM */ 172 if (socfpga_is_booting_from_fpga()) 173 remap |= 0x8; /* remap.hps2fpga */ 174 writel(remap, &nic301_regs->remap); 175 176 writel(0x1, &pl310->pl310_addr_filter_start); 177 } 178 179 static u32 iswgrp_handoff[8]; 180 181 int arch_early_init_r(void) 182 { 183 int i; 184 185 /* 186 * Write magic value into magic register to unlock support for 187 * issuing warm reset. The ancient kernel code expects this 188 * value to be written into the register by the bootloader, so 189 * to support that old code, we write it here instead of in the 190 * reset_cpu() function just before resetting the CPU. 191 */ 192 writel(0xae9efebc, &sysmgr_regs->romcodegrp_warmramgrp_enable); 193 194 for (i = 0; i < 8; i++) /* Cache initial SW setting regs */ 195 iswgrp_handoff[i] = readl(&sysmgr_regs->iswgrp_handoff[i]); 196 197 socfpga_bridges_reset(1); 198 199 socfpga_sdram_remap_zero(); 200 201 /* Add device descriptor to FPGA device table */ 202 socfpga_fpga_add(&altera_fpga[0]); 203 204 #ifdef CONFIG_DESIGNWARE_SPI 205 /* Get Designware SPI controller out of reset */ 206 socfpga_per_reset(SOCFPGA_RESET(SPIM0), 0); 207 socfpga_per_reset(SOCFPGA_RESET(SPIM1), 0); 208 #endif 209 210 #ifdef CONFIG_NAND_DENALI 211 socfpga_per_reset(SOCFPGA_RESET(NAND), 0); 212 #endif 213 214 return 0; 215 } 216 217 #ifndef CONFIG_SPL_BUILD 218 static struct socfpga_reset_manager *reset_manager_base = 219 (struct socfpga_reset_manager *)SOCFPGA_RSTMGR_ADDRESS; 220 static struct socfpga_sdr_ctrl *sdr_ctrl = 221 (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS; 222 223 static void socfpga_sdram_apply_static_cfg(void) 224 { 225 const u32 applymask = 0x8; 226 u32 val = readl(&sdr_ctrl->static_cfg) | applymask; 227 228 /* 229 * SDRAM staticcfg register specific: 230 * When applying the register setting, the CPU must not access 231 * SDRAM. Luckily for us, we can abuse i-cache here to help us 232 * circumvent the SDRAM access issue. The idea is to make sure 233 * that the code is in one full i-cache line by branching past 234 * it and back. Once it is in the i-cache, we execute the core 235 * of the code and apply the register settings. 236 * 237 * The code below uses 7 instructions, while the Cortex-A9 has 238 * 32-byte cachelines, thus the limit is 8 instructions total. 239 */ 240 asm volatile( 241 ".align 5 \n" 242 " b 2f \n" 243 "1: str %0, [%1] \n" 244 " dsb \n" 245 " isb \n" 246 " b 3f \n" 247 "2: b 1b \n" 248 "3: nop \n" 249 : : "r"(val), "r"(&sdr_ctrl->static_cfg) : "memory", "cc"); 250 } 251 252 void do_bridge_reset(int enable) 253 { 254 if (enable) { 255 writel(iswgrp_handoff[2], &sysmgr_regs->fpgaintfgrp_module); 256 socfpga_sdram_apply_static_cfg(); 257 writel(iswgrp_handoff[3], &sdr_ctrl->fpgaport_rst); 258 writel(iswgrp_handoff[0], &reset_manager_base->brg_mod_reset); 259 writel(iswgrp_handoff[1], &nic301_regs->remap); 260 } else { 261 writel(0, &sysmgr_regs->fpgaintfgrp_module); 262 writel(0, &sdr_ctrl->fpgaport_rst); 263 socfpga_sdram_apply_static_cfg(); 264 writel(0, &reset_manager_base->brg_mod_reset); 265 writel(1, &nic301_regs->remap); 266 } 267 } 268 #endif 269