1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  *  Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
4  */
5 
6 #include <common.h>
7 #include <asm/io.h>
8 #include <errno.h>
9 #include <fdtdec.h>
10 #include <linux/libfdt.h>
11 #include <altera.h>
12 #include <miiphy.h>
13 #include <netdev.h>
14 #include <watchdog.h>
15 #include <asm/arch/misc.h>
16 #include <asm/arch/reset_manager.h>
17 #include <asm/arch/scan_manager.h>
18 #include <asm/arch/sdram.h>
19 #include <asm/arch/system_manager.h>
20 #include <asm/arch/nic301.h>
21 #include <asm/arch/scu.h>
22 #include <asm/pl310.h>
23 
24 #include <dt-bindings/reset/altr,rst-mgr.h>
25 
26 DECLARE_GLOBAL_DATA_PTR;
27 
28 static struct pl310_regs *const pl310 =
29 	(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
30 static struct socfpga_system_manager *sysmgr_regs =
31 	(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
32 static struct nic301_registers *nic301_regs =
33 	(struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
34 static struct scu_registers *scu_regs =
35 	(struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
36 
37 /*
38  * FPGA programming support for SoC FPGA Cyclone V
39  */
40 static Altera_desc altera_fpga[] = {
41 	{
42 		/* Family */
43 		Altera_SoCFPGA,
44 		/* Interface type */
45 		fast_passive_parallel,
46 		/* No limitation as additional data will be ignored */
47 		-1,
48 		/* No device function table */
49 		NULL,
50 		/* Base interface address specified in driver */
51 		NULL,
52 		/* No cookie implementation */
53 		0
54 	},
55 };
56 
57 /*
58  * DesignWare Ethernet initialization
59  */
60 #ifdef CONFIG_ETH_DESIGNWARE
61 static void gen5_dwmac_reset(const u8 of_reset_id, const u8 phymode)
62 {
63 	u32 physhift, reset;
64 
65 	if (of_reset_id == EMAC0_RESET) {
66 		physhift = SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB;
67 		reset = SOCFPGA_RESET(EMAC0);
68 	} else if (of_reset_id == EMAC1_RESET) {
69 		physhift = SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB;
70 		reset = SOCFPGA_RESET(EMAC1);
71 	} else {
72 		printf("GMAC: Invalid reset ID (%i)!\n", of_reset_id);
73 		return;
74 	}
75 
76 	/* configure to PHY interface select choosed */
77 	clrsetbits_le32(&sysmgr_regs->emacgrp_ctrl,
78 			SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << physhift,
79 			phymode << physhift);
80 
81 	/* Release the EMAC controller from reset */
82 	socfpga_per_reset(reset, 0);
83 }
84 
85 static int socfpga_eth_reset(void)
86 {
87 	/* Put all GMACs into RESET state. */
88 	socfpga_per_reset(SOCFPGA_RESET(EMAC0), 1);
89 	socfpga_per_reset(SOCFPGA_RESET(EMAC1), 1);
90 	return socfpga_eth_reset_common(gen5_dwmac_reset);
91 };
92 #else
93 static int socfpga_eth_reset(void)
94 {
95 	return 0;
96 };
97 #endif
98 
99 static const struct {
100 	const u16	pn;
101 	const char	*name;
102 	const char	*var;
103 } socfpga_fpga_model[] = {
104 	/* Cyclone V E */
105 	{ 0x2b15, "Cyclone V, E/A2", "cv_e_a2" },
106 	{ 0x2b05, "Cyclone V, E/A4", "cv_e_a4" },
107 	{ 0x2b22, "Cyclone V, E/A5", "cv_e_a5" },
108 	{ 0x2b13, "Cyclone V, E/A7", "cv_e_a7" },
109 	{ 0x2b14, "Cyclone V, E/A9", "cv_e_a9" },
110 	/* Cyclone V GX/GT */
111 	{ 0x2b01, "Cyclone V, GX/C3", "cv_gx_c3" },
112 	{ 0x2b12, "Cyclone V, GX/C4", "cv_gx_c4" },
113 	{ 0x2b02, "Cyclone V, GX/C5 or GT/D5", "cv_gx_c5" },
114 	{ 0x2b03, "Cyclone V, GX/C7 or GT/D7", "cv_gx_c7" },
115 	{ 0x2b04, "Cyclone V, GX/C9 or GT/D9", "cv_gx_c9" },
116 	/* Cyclone V SE/SX/ST */
117 	{ 0x2d11, "Cyclone V, SE/A2 or SX/C2", "cv_se_a2" },
118 	{ 0x2d01, "Cyclone V, SE/A4 or SX/C4", "cv_se_a4" },
119 	{ 0x2d12, "Cyclone V, SE/A5 or SX/C5 or ST/D5", "cv_se_a5" },
120 	{ 0x2d02, "Cyclone V, SE/A6 or SX/C6 or ST/D6", "cv_se_a6" },
121 	/* Arria V */
122 	{ 0x2d03, "Arria V, D5", "av_d5" },
123 };
124 
125 static int socfpga_fpga_id(const bool print_id)
126 {
127 	const u32 altera_mi = 0x6e;
128 	const u32 id = scan_mgr_get_fpga_id();
129 
130 	const u32 lsb = id & 0x00000001;
131 	const u32 mi = (id >> 1) & 0x000007ff;
132 	const u32 pn = (id >> 12) & 0x0000ffff;
133 	const u32 version = (id >> 28) & 0x0000000f;
134 	int i;
135 
136 	if ((mi != altera_mi) || (lsb != 1)) {
137 		printf("FPGA:  Not Altera chip ID\n");
138 		return -EINVAL;
139 	}
140 
141 	for (i = 0; i < ARRAY_SIZE(socfpga_fpga_model); i++)
142 		if (pn == socfpga_fpga_model[i].pn)
143 			break;
144 
145 	if (i == ARRAY_SIZE(socfpga_fpga_model)) {
146 		printf("FPGA:  Unknown Altera chip, ID 0x%08x\n", id);
147 		return -EINVAL;
148 	}
149 
150 	if (print_id)
151 		printf("FPGA:  Altera %s, version 0x%01x\n",
152 		       socfpga_fpga_model[i].name, version);
153 	return i;
154 }
155 
156 /*
157  * Print CPU information
158  */
159 #if defined(CONFIG_DISPLAY_CPUINFO)
160 int print_cpuinfo(void)
161 {
162 	const u32 bsel =
163 		SYSMGR_GET_BOOTINFO_BSEL(readl(&sysmgr_regs->bootinfo));
164 
165 	puts("CPU:   Altera SoCFPGA Platform\n");
166 	socfpga_fpga_id(1);
167 
168 	printf("BOOT:  %s\n", bsel_str[bsel].name);
169 	return 0;
170 }
171 #endif
172 
173 #ifdef CONFIG_ARCH_MISC_INIT
174 int arch_misc_init(void)
175 {
176 	const u32 bsel = readl(&sysmgr_regs->bootinfo) & 0x7;
177 	const int fpga_id = socfpga_fpga_id(0);
178 	env_set("bootmode", bsel_str[bsel].mode);
179 	if (fpga_id >= 0)
180 		env_set("fpgatype", socfpga_fpga_model[fpga_id].var);
181 	return socfpga_eth_reset();
182 }
183 #endif
184 
185 /*
186  * Convert all NIC-301 AMBA slaves from secure to non-secure
187  */
188 static void socfpga_nic301_slave_ns(void)
189 {
190 	writel(0x1, &nic301_regs->lwhps2fpgaregs);
191 	writel(0x1, &nic301_regs->hps2fpgaregs);
192 	writel(0x1, &nic301_regs->acp);
193 	writel(0x1, &nic301_regs->rom);
194 	writel(0x1, &nic301_regs->ocram);
195 	writel(0x1, &nic301_regs->sdrdata);
196 }
197 
198 void socfpga_sdram_remap_zero(void)
199 {
200 	u32 remap;
201 
202 	socfpga_nic301_slave_ns();
203 
204 	/*
205 	 * Private components security:
206 	 * U-Boot : configure private timer, global timer and cpu component
207 	 * access as non secure for kernel stage (as required by Linux)
208 	 */
209 	setbits_le32(&scu_regs->sacr, 0xfff);
210 
211 	/* Configure the L2 controller to make SDRAM start at 0 */
212 	remap = 0x1; /* remap.mpuzero */
213 	/* Keep fpga bridge enabled when running from FPGA onchip RAM */
214 	if (socfpga_is_booting_from_fpga())
215 		remap |= 0x8; /* remap.hps2fpga */
216 	writel(remap, &nic301_regs->remap);
217 
218 	writel(0x1, &pl310->pl310_addr_filter_start);
219 }
220 
221 static u32 iswgrp_handoff[8];
222 
223 int arch_early_init_r(void)
224 {
225 	int i;
226 
227 	/*
228 	 * Write magic value into magic register to unlock support for
229 	 * issuing warm reset. The ancient kernel code expects this
230 	 * value to be written into the register by the bootloader, so
231 	 * to support that old code, we write it here instead of in the
232 	 * reset_cpu() function just before resetting the CPU.
233 	 */
234 	writel(0xae9efebc, &sysmgr_regs->romcodegrp_warmramgrp_enable);
235 
236 	for (i = 0; i < 8; i++)	/* Cache initial SW setting regs */
237 		iswgrp_handoff[i] = readl(&sysmgr_regs->iswgrp_handoff[i]);
238 
239 	socfpga_bridges_reset(1);
240 
241 	socfpga_sdram_remap_zero();
242 
243 	/* Add device descriptor to FPGA device table */
244 	socfpga_fpga_add(&altera_fpga[0]);
245 
246 #ifdef CONFIG_DESIGNWARE_SPI
247 	/* Get Designware SPI controller out of reset */
248 	socfpga_per_reset(SOCFPGA_RESET(SPIM0), 0);
249 	socfpga_per_reset(SOCFPGA_RESET(SPIM1), 0);
250 #endif
251 
252 #ifdef CONFIG_NAND_DENALI
253 	socfpga_per_reset(SOCFPGA_RESET(NAND), 0);
254 #endif
255 
256 	return 0;
257 }
258 
259 #ifndef CONFIG_SPL_BUILD
260 static struct socfpga_reset_manager *reset_manager_base =
261 	(struct socfpga_reset_manager *)SOCFPGA_RSTMGR_ADDRESS;
262 static struct socfpga_sdr_ctrl *sdr_ctrl =
263 	(struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
264 
265 static void socfpga_sdram_apply_static_cfg(void)
266 {
267 	const u32 applymask = 0x8;
268 	u32 val = readl(&sdr_ctrl->static_cfg) | applymask;
269 
270 	/*
271 	 * SDRAM staticcfg register specific:
272 	 * When applying the register setting, the CPU must not access
273 	 * SDRAM. Luckily for us, we can abuse i-cache here to help us
274 	 * circumvent the SDRAM access issue. The idea is to make sure
275 	 * that the code is in one full i-cache line by branching past
276 	 * it and back. Once it is in the i-cache, we execute the core
277 	 * of the code and apply the register settings.
278 	 *
279 	 * The code below uses 7 instructions, while the Cortex-A9 has
280 	 * 32-byte cachelines, thus the limit is 8 instructions total.
281 	 */
282 	asm volatile(
283 		".align	5			\n"
284 		"	b	2f		\n"
285 		"1:	str	%0,	[%1]	\n"
286 		"	dsb			\n"
287 		"	isb			\n"
288 		"	b	3f		\n"
289 		"2:	b	1b		\n"
290 		"3:	nop			\n"
291 	: : "r"(val), "r"(&sdr_ctrl->static_cfg) : "memory", "cc");
292 }
293 
294 void do_bridge_reset(int enable)
295 {
296 	if (enable) {
297 		writel(iswgrp_handoff[2], &sysmgr_regs->fpgaintfgrp_module);
298 		socfpga_sdram_apply_static_cfg();
299 		writel(iswgrp_handoff[3], &sdr_ctrl->fpgaport_rst);
300 		writel(iswgrp_handoff[0], &reset_manager_base->brg_mod_reset);
301 		writel(iswgrp_handoff[1], &nic301_regs->remap);
302 	} else {
303 		writel(0, &sysmgr_regs->fpgaintfgrp_module);
304 		writel(0, &sdr_ctrl->fpgaport_rst);
305 		socfpga_sdram_apply_static_cfg();
306 		writel(0, &reset_manager_base->brg_mod_reset);
307 		writel(1, &nic301_regs->remap);
308 	}
309 }
310 #endif
311