1d1c559afSLey Foon Tan /* 2d1c559afSLey Foon Tan * Copyright (C) 2012-2017 Altera Corporation <www.altera.com> 3d1c559afSLey Foon Tan * 4d1c559afSLey Foon Tan * SPDX-License-Identifier: GPL-2.0+ 5d1c559afSLey Foon Tan */ 6d1c559afSLey Foon Tan 7d1c559afSLey Foon Tan #include <common.h> 8d1c559afSLey Foon Tan #include <asm/io.h> 9d1c559afSLey Foon Tan #include <errno.h> 10d1c559afSLey Foon Tan #include <fdtdec.h> 11d1c559afSLey Foon Tan #include <libfdt.h> 12d1c559afSLey Foon Tan #include <altera.h> 13d1c559afSLey Foon Tan #include <miiphy.h> 14d1c559afSLey Foon Tan #include <netdev.h> 15d1c559afSLey Foon Tan #include <watchdog.h> 16d1c559afSLey Foon Tan #include <asm/arch/misc.h> 17d1c559afSLey Foon Tan #include <asm/arch/reset_manager.h> 18d1c559afSLey Foon Tan #include <asm/arch/scan_manager.h> 19d1c559afSLey Foon Tan #include <asm/arch/sdram.h> 20d1c559afSLey Foon Tan #include <asm/arch/system_manager.h> 21d1c559afSLey Foon Tan #include <asm/arch/nic301.h> 22d1c559afSLey Foon Tan #include <asm/arch/scu.h> 23d1c559afSLey Foon Tan #include <asm/pl310.h> 24d1c559afSLey Foon Tan 25d1c559afSLey Foon Tan #include <dt-bindings/reset/altr,rst-mgr.h> 26d1c559afSLey Foon Tan 27d1c559afSLey Foon Tan DECLARE_GLOBAL_DATA_PTR; 28d1c559afSLey Foon Tan 29d1c559afSLey Foon Tan static struct pl310_regs *const pl310 = 30d1c559afSLey Foon Tan (struct pl310_regs *)CONFIG_SYS_PL310_BASE; 31d1c559afSLey Foon Tan static struct socfpga_system_manager *sysmgr_regs = 32d1c559afSLey Foon Tan (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; 33d1c559afSLey Foon Tan static struct socfpga_reset_manager *reset_manager_base = 34d1c559afSLey Foon Tan (struct socfpga_reset_manager *)SOCFPGA_RSTMGR_ADDRESS; 35d1c559afSLey Foon Tan static struct nic301_registers *nic301_regs = 36d1c559afSLey Foon Tan (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS; 37d1c559afSLey Foon Tan static struct scu_registers *scu_regs = 38d1c559afSLey Foon Tan (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS; 39d1c559afSLey Foon Tan static struct socfpga_sdr_ctrl *sdr_ctrl = 40d1c559afSLey Foon Tan (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS; 41d1c559afSLey Foon Tan 42d1c559afSLey Foon Tan /* 43d1c559afSLey Foon Tan * DesignWare Ethernet initialization 44d1c559afSLey Foon Tan */ 45d1c559afSLey Foon Tan #ifdef CONFIG_ETH_DESIGNWARE 46d1c559afSLey Foon Tan void dwmac_deassert_reset(const unsigned int of_reset_id, 47d1c559afSLey Foon Tan const u32 phymode) 48d1c559afSLey Foon Tan { 49d1c559afSLey Foon Tan u32 physhift, reset; 50d1c559afSLey Foon Tan 51d1c559afSLey Foon Tan if (of_reset_id == EMAC0_RESET) { 52d1c559afSLey Foon Tan physhift = SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB; 53d1c559afSLey Foon Tan reset = SOCFPGA_RESET(EMAC0); 54d1c559afSLey Foon Tan } else if (of_reset_id == EMAC1_RESET) { 55d1c559afSLey Foon Tan physhift = SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB; 56d1c559afSLey Foon Tan reset = SOCFPGA_RESET(EMAC1); 57d1c559afSLey Foon Tan } else { 58d1c559afSLey Foon Tan printf("GMAC: Invalid reset ID (%i)!\n", of_reset_id); 59d1c559afSLey Foon Tan return; 60d1c559afSLey Foon Tan } 61d1c559afSLey Foon Tan 62d1c559afSLey Foon Tan /* configure to PHY interface select choosed */ 63d1c559afSLey Foon Tan clrsetbits_le32(&sysmgr_regs->emacgrp_ctrl, 64d1c559afSLey Foon Tan SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << physhift, 65d1c559afSLey Foon Tan phymode << physhift); 66d1c559afSLey Foon Tan 67d1c559afSLey Foon Tan /* Release the EMAC controller from reset */ 68d1c559afSLey Foon Tan socfpga_per_reset(reset, 0); 69d1c559afSLey Foon Tan } 70d1c559afSLey Foon Tan 71d1c559afSLey Foon Tan static u32 dwmac_phymode_to_modereg(const char *phymode, u32 *modereg) 72d1c559afSLey Foon Tan { 73d1c559afSLey Foon Tan if (!phymode) 74d1c559afSLey Foon Tan return -EINVAL; 75d1c559afSLey Foon Tan 76d1c559afSLey Foon Tan if (!strcmp(phymode, "mii") || !strcmp(phymode, "gmii")) { 77d1c559afSLey Foon Tan *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII; 78d1c559afSLey Foon Tan return 0; 79d1c559afSLey Foon Tan } 80d1c559afSLey Foon Tan 81d1c559afSLey Foon Tan if (!strcmp(phymode, "rgmii")) { 82d1c559afSLey Foon Tan *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII; 83d1c559afSLey Foon Tan return 0; 84d1c559afSLey Foon Tan } 85d1c559afSLey Foon Tan 86d1c559afSLey Foon Tan if (!strcmp(phymode, "rmii")) { 87d1c559afSLey Foon Tan *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII; 88d1c559afSLey Foon Tan return 0; 89d1c559afSLey Foon Tan } 90d1c559afSLey Foon Tan 91d1c559afSLey Foon Tan return -EINVAL; 92d1c559afSLey Foon Tan } 93d1c559afSLey Foon Tan 94d1c559afSLey Foon Tan static int socfpga_eth_reset(void) 95d1c559afSLey Foon Tan { 96d1c559afSLey Foon Tan const void *fdt = gd->fdt_blob; 97d1c559afSLey Foon Tan struct fdtdec_phandle_args args; 98d1c559afSLey Foon Tan const char *phy_mode; 99d1c559afSLey Foon Tan u32 phy_modereg; 100d1c559afSLey Foon Tan int nodes[2]; /* Max. two GMACs */ 101d1c559afSLey Foon Tan int ret, count; 102d1c559afSLey Foon Tan int i, node; 103d1c559afSLey Foon Tan 104d1c559afSLey Foon Tan /* Put both GMACs into RESET state. */ 105d1c559afSLey Foon Tan socfpga_per_reset(SOCFPGA_RESET(EMAC0), 1); 106d1c559afSLey Foon Tan socfpga_per_reset(SOCFPGA_RESET(EMAC1), 1); 107d1c559afSLey Foon Tan 108d1c559afSLey Foon Tan count = fdtdec_find_aliases_for_id(fdt, "ethernet", 109d1c559afSLey Foon Tan COMPAT_ALTERA_SOCFPGA_DWMAC, 110d1c559afSLey Foon Tan nodes, ARRAY_SIZE(nodes)); 111d1c559afSLey Foon Tan for (i = 0; i < count; i++) { 112d1c559afSLey Foon Tan node = nodes[i]; 113d1c559afSLey Foon Tan if (node <= 0) 114d1c559afSLey Foon Tan continue; 115d1c559afSLey Foon Tan 116d1c559afSLey Foon Tan ret = fdtdec_parse_phandle_with_args(fdt, node, "resets", 117d1c559afSLey Foon Tan "#reset-cells", 1, 0, 118d1c559afSLey Foon Tan &args); 119d1c559afSLey Foon Tan if (ret || (args.args_count != 1)) { 120d1c559afSLey Foon Tan debug("GMAC%i: Failed to parse DT 'resets'!\n", i); 121d1c559afSLey Foon Tan continue; 122d1c559afSLey Foon Tan } 123d1c559afSLey Foon Tan 124d1c559afSLey Foon Tan phy_mode = fdt_getprop(fdt, node, "phy-mode", NULL); 125d1c559afSLey Foon Tan ret = dwmac_phymode_to_modereg(phy_mode, &phy_modereg); 126d1c559afSLey Foon Tan if (ret) { 127d1c559afSLey Foon Tan debug("GMAC%i: Failed to parse DT 'phy-mode'!\n", i); 128d1c559afSLey Foon Tan continue; 129d1c559afSLey Foon Tan } 130d1c559afSLey Foon Tan 131d1c559afSLey Foon Tan dwmac_deassert_reset(args.args[0], phy_modereg); 132d1c559afSLey Foon Tan } 133d1c559afSLey Foon Tan 134d1c559afSLey Foon Tan return 0; 135d1c559afSLey Foon Tan } 136d1c559afSLey Foon Tan #else 137d1c559afSLey Foon Tan static int socfpga_eth_reset(void) 138d1c559afSLey Foon Tan { 139d1c559afSLey Foon Tan return 0; 140d1c559afSLey Foon Tan }; 141d1c559afSLey Foon Tan #endif 142d1c559afSLey Foon Tan 143d1c559afSLey Foon Tan static const struct { 144d1c559afSLey Foon Tan const u16 pn; 145d1c559afSLey Foon Tan const char *name; 146d1c559afSLey Foon Tan const char *var; 147d1c559afSLey Foon Tan } const socfpga_fpga_model[] = { 148d1c559afSLey Foon Tan /* Cyclone V E */ 149d1c559afSLey Foon Tan { 0x2b15, "Cyclone V, E/A2", "cv_e_a2" }, 150d1c559afSLey Foon Tan { 0x2b05, "Cyclone V, E/A4", "cv_e_a4" }, 151d1c559afSLey Foon Tan { 0x2b22, "Cyclone V, E/A5", "cv_e_a5" }, 152d1c559afSLey Foon Tan { 0x2b13, "Cyclone V, E/A7", "cv_e_a7" }, 153d1c559afSLey Foon Tan { 0x2b14, "Cyclone V, E/A9", "cv_e_a9" }, 154d1c559afSLey Foon Tan /* Cyclone V GX/GT */ 155d1c559afSLey Foon Tan { 0x2b01, "Cyclone V, GX/C3", "cv_gx_c3" }, 156d1c559afSLey Foon Tan { 0x2b12, "Cyclone V, GX/C4", "cv_gx_c4" }, 157d1c559afSLey Foon Tan { 0x2b02, "Cyclone V, GX/C5 or GT/D5", "cv_gx_c5" }, 158d1c559afSLey Foon Tan { 0x2b03, "Cyclone V, GX/C7 or GT/D7", "cv_gx_c7" }, 159d1c559afSLey Foon Tan { 0x2b04, "Cyclone V, GX/C9 or GT/D9", "cv_gx_c9" }, 160d1c559afSLey Foon Tan /* Cyclone V SE/SX/ST */ 161d1c559afSLey Foon Tan { 0x2d11, "Cyclone V, SE/A2 or SX/C2", "cv_se_a2" }, 162d1c559afSLey Foon Tan { 0x2d01, "Cyclone V, SE/A4 or SX/C4", "cv_se_a4" }, 163d1c559afSLey Foon Tan { 0x2d12, "Cyclone V, SE/A5 or SX/C5 or ST/D5", "cv_se_a5" }, 164d1c559afSLey Foon Tan { 0x2d02, "Cyclone V, SE/A6 or SX/C6 or ST/D6", "cv_se_a6" }, 165d1c559afSLey Foon Tan /* Arria V */ 166d1c559afSLey Foon Tan { 0x2d03, "Arria V, D5", "av_d5" }, 167d1c559afSLey Foon Tan }; 168d1c559afSLey Foon Tan 169d1c559afSLey Foon Tan static int socfpga_fpga_id(const bool print_id) 170d1c559afSLey Foon Tan { 171d1c559afSLey Foon Tan const u32 altera_mi = 0x6e; 172d1c559afSLey Foon Tan const u32 id = scan_mgr_get_fpga_id(); 173d1c559afSLey Foon Tan 174d1c559afSLey Foon Tan const u32 lsb = id & 0x00000001; 175d1c559afSLey Foon Tan const u32 mi = (id >> 1) & 0x000007ff; 176d1c559afSLey Foon Tan const u32 pn = (id >> 12) & 0x0000ffff; 177d1c559afSLey Foon Tan const u32 version = (id >> 28) & 0x0000000f; 178d1c559afSLey Foon Tan int i; 179d1c559afSLey Foon Tan 180d1c559afSLey Foon Tan if ((mi != altera_mi) || (lsb != 1)) { 181d1c559afSLey Foon Tan printf("FPGA: Not Altera chip ID\n"); 182d1c559afSLey Foon Tan return -EINVAL; 183d1c559afSLey Foon Tan } 184d1c559afSLey Foon Tan 185d1c559afSLey Foon Tan for (i = 0; i < ARRAY_SIZE(socfpga_fpga_model); i++) 186d1c559afSLey Foon Tan if (pn == socfpga_fpga_model[i].pn) 187d1c559afSLey Foon Tan break; 188d1c559afSLey Foon Tan 189d1c559afSLey Foon Tan if (i == ARRAY_SIZE(socfpga_fpga_model)) { 190d1c559afSLey Foon Tan printf("FPGA: Unknown Altera chip, ID 0x%08x\n", id); 191d1c559afSLey Foon Tan return -EINVAL; 192d1c559afSLey Foon Tan } 193d1c559afSLey Foon Tan 194d1c559afSLey Foon Tan if (print_id) 195d1c559afSLey Foon Tan printf("FPGA: Altera %s, version 0x%01x\n", 196d1c559afSLey Foon Tan socfpga_fpga_model[i].name, version); 197d1c559afSLey Foon Tan return i; 198d1c559afSLey Foon Tan } 199d1c559afSLey Foon Tan 200d1c559afSLey Foon Tan /* 201d1c559afSLey Foon Tan * Print CPU information 202d1c559afSLey Foon Tan */ 203d1c559afSLey Foon Tan #if defined(CONFIG_DISPLAY_CPUINFO) 204d1c559afSLey Foon Tan int print_cpuinfo(void) 205d1c559afSLey Foon Tan { 206d1c559afSLey Foon Tan const u32 bsel = 207d1c559afSLey Foon Tan SYSMGR_GET_BOOTINFO_BSEL(readl(&sysmgr_regs->bootinfo)); 208d1c559afSLey Foon Tan 209d1c559afSLey Foon Tan puts("CPU: Altera SoCFPGA Platform\n"); 210d1c559afSLey Foon Tan socfpga_fpga_id(1); 211d1c559afSLey Foon Tan 212d1c559afSLey Foon Tan printf("BOOT: %s\n", bsel_str[bsel].name); 213d1c559afSLey Foon Tan return 0; 214d1c559afSLey Foon Tan } 215d1c559afSLey Foon Tan #endif 216d1c559afSLey Foon Tan 217d1c559afSLey Foon Tan #ifdef CONFIG_ARCH_MISC_INIT 218d1c559afSLey Foon Tan int arch_misc_init(void) 219d1c559afSLey Foon Tan { 220d1c559afSLey Foon Tan const u32 bsel = readl(&sysmgr_regs->bootinfo) & 0x7; 221d1c559afSLey Foon Tan const int fpga_id = socfpga_fpga_id(0); 222*382bee57SSimon Glass env_set("bootmode", bsel_str[bsel].mode); 223d1c559afSLey Foon Tan if (fpga_id >= 0) 224*382bee57SSimon Glass env_set("fpgatype", socfpga_fpga_model[fpga_id].var); 225d1c559afSLey Foon Tan return socfpga_eth_reset(); 226d1c559afSLey Foon Tan } 227d1c559afSLey Foon Tan #endif 228d1c559afSLey Foon Tan 229d1c559afSLey Foon Tan /* 230d1c559afSLey Foon Tan * Convert all NIC-301 AMBA slaves from secure to non-secure 231d1c559afSLey Foon Tan */ 232d1c559afSLey Foon Tan static void socfpga_nic301_slave_ns(void) 233d1c559afSLey Foon Tan { 234d1c559afSLey Foon Tan writel(0x1, &nic301_regs->lwhps2fpgaregs); 235d1c559afSLey Foon Tan writel(0x1, &nic301_regs->hps2fpgaregs); 236d1c559afSLey Foon Tan writel(0x1, &nic301_regs->acp); 237d1c559afSLey Foon Tan writel(0x1, &nic301_regs->rom); 238d1c559afSLey Foon Tan writel(0x1, &nic301_regs->ocram); 239d1c559afSLey Foon Tan writel(0x1, &nic301_regs->sdrdata); 240d1c559afSLey Foon Tan } 241d1c559afSLey Foon Tan 242d1c559afSLey Foon Tan static u32 iswgrp_handoff[8]; 243d1c559afSLey Foon Tan 244d1c559afSLey Foon Tan int arch_early_init_r(void) 245d1c559afSLey Foon Tan { 246d1c559afSLey Foon Tan int i; 247d1c559afSLey Foon Tan 248d1c559afSLey Foon Tan /* 249d1c559afSLey Foon Tan * Write magic value into magic register to unlock support for 250d1c559afSLey Foon Tan * issuing warm reset. The ancient kernel code expects this 251d1c559afSLey Foon Tan * value to be written into the register by the bootloader, so 252d1c559afSLey Foon Tan * to support that old code, we write it here instead of in the 253d1c559afSLey Foon Tan * reset_cpu() function just before resetting the CPU. 254d1c559afSLey Foon Tan */ 255d1c559afSLey Foon Tan writel(0xae9efebc, &sysmgr_regs->romcodegrp_warmramgrp_enable); 256d1c559afSLey Foon Tan 257d1c559afSLey Foon Tan for (i = 0; i < 8; i++) /* Cache initial SW setting regs */ 258d1c559afSLey Foon Tan iswgrp_handoff[i] = readl(&sysmgr_regs->iswgrp_handoff[i]); 259d1c559afSLey Foon Tan 260d1c559afSLey Foon Tan socfpga_bridges_reset(1); 261d1c559afSLey Foon Tan 262d1c559afSLey Foon Tan socfpga_nic301_slave_ns(); 263d1c559afSLey Foon Tan 264d1c559afSLey Foon Tan /* 265d1c559afSLey Foon Tan * Private components security: 266d1c559afSLey Foon Tan * U-Boot : configure private timer, global timer and cpu component 267d1c559afSLey Foon Tan * access as non secure for kernel stage (as required by Linux) 268d1c559afSLey Foon Tan */ 269d1c559afSLey Foon Tan setbits_le32(&scu_regs->sacr, 0xfff); 270d1c559afSLey Foon Tan 271d1c559afSLey Foon Tan /* Configure the L2 controller to make SDRAM start at 0 */ 272d1c559afSLey Foon Tan #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET 273d1c559afSLey Foon Tan writel(0x2, &nic301_regs->remap); 274d1c559afSLey Foon Tan #else 275d1c559afSLey Foon Tan writel(0x1, &nic301_regs->remap); /* remap.mpuzero */ 276d1c559afSLey Foon Tan writel(0x1, &pl310->pl310_addr_filter_start); 277d1c559afSLey Foon Tan #endif 278d1c559afSLey Foon Tan 279d1c559afSLey Foon Tan /* Add device descriptor to FPGA device table */ 280d1c559afSLey Foon Tan socfpga_fpga_add(); 281d1c559afSLey Foon Tan 282d1c559afSLey Foon Tan #ifdef CONFIG_DESIGNWARE_SPI 283d1c559afSLey Foon Tan /* Get Designware SPI controller out of reset */ 284d1c559afSLey Foon Tan socfpga_per_reset(SOCFPGA_RESET(SPIM0), 0); 285d1c559afSLey Foon Tan socfpga_per_reset(SOCFPGA_RESET(SPIM1), 0); 286d1c559afSLey Foon Tan #endif 287d1c559afSLey Foon Tan 288d1c559afSLey Foon Tan #ifdef CONFIG_NAND_DENALI 289d1c559afSLey Foon Tan socfpga_per_reset(SOCFPGA_RESET(NAND), 0); 290d1c559afSLey Foon Tan #endif 291d1c559afSLey Foon Tan 292d1c559afSLey Foon Tan return 0; 293d1c559afSLey Foon Tan } 294d1c559afSLey Foon Tan 295d1c559afSLey Foon Tan static void socfpga_sdram_apply_static_cfg(void) 296d1c559afSLey Foon Tan { 297d1c559afSLey Foon Tan const u32 applymask = 0x8; 298d1c559afSLey Foon Tan u32 val = readl(&sdr_ctrl->static_cfg) | applymask; 299d1c559afSLey Foon Tan 300d1c559afSLey Foon Tan /* 301d1c559afSLey Foon Tan * SDRAM staticcfg register specific: 302d1c559afSLey Foon Tan * When applying the register setting, the CPU must not access 303d1c559afSLey Foon Tan * SDRAM. Luckily for us, we can abuse i-cache here to help us 304d1c559afSLey Foon Tan * circumvent the SDRAM access issue. The idea is to make sure 305d1c559afSLey Foon Tan * that the code is in one full i-cache line by branching past 306d1c559afSLey Foon Tan * it and back. Once it is in the i-cache, we execute the core 307d1c559afSLey Foon Tan * of the code and apply the register settings. 308d1c559afSLey Foon Tan * 309d1c559afSLey Foon Tan * The code below uses 7 instructions, while the Cortex-A9 has 310d1c559afSLey Foon Tan * 32-byte cachelines, thus the limit is 8 instructions total. 311d1c559afSLey Foon Tan */ 312d1c559afSLey Foon Tan asm volatile( 313d1c559afSLey Foon Tan ".align 5 \n" 314d1c559afSLey Foon Tan " b 2f \n" 315d1c559afSLey Foon Tan "1: str %0, [%1] \n" 316d1c559afSLey Foon Tan " dsb \n" 317d1c559afSLey Foon Tan " isb \n" 318d1c559afSLey Foon Tan " b 3f \n" 319d1c559afSLey Foon Tan "2: b 1b \n" 320d1c559afSLey Foon Tan "3: nop \n" 321d1c559afSLey Foon Tan : : "r"(val), "r"(&sdr_ctrl->static_cfg) : "memory", "cc"); 322d1c559afSLey Foon Tan } 323d1c559afSLey Foon Tan 324d1c559afSLey Foon Tan int do_bridge(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 325d1c559afSLey Foon Tan { 326d1c559afSLey Foon Tan if (argc != 2) 327d1c559afSLey Foon Tan return CMD_RET_USAGE; 328d1c559afSLey Foon Tan 329d1c559afSLey Foon Tan argv++; 330d1c559afSLey Foon Tan 331d1c559afSLey Foon Tan switch (*argv[0]) { 332d1c559afSLey Foon Tan case 'e': /* Enable */ 333d1c559afSLey Foon Tan writel(iswgrp_handoff[2], &sysmgr_regs->fpgaintfgrp_module); 334d1c559afSLey Foon Tan socfpga_sdram_apply_static_cfg(); 335d1c559afSLey Foon Tan writel(iswgrp_handoff[3], &sdr_ctrl->fpgaport_rst); 336d1c559afSLey Foon Tan writel(iswgrp_handoff[0], &reset_manager_base->brg_mod_reset); 337d1c559afSLey Foon Tan writel(iswgrp_handoff[1], &nic301_regs->remap); 338d1c559afSLey Foon Tan break; 339d1c559afSLey Foon Tan case 'd': /* Disable */ 340d1c559afSLey Foon Tan writel(0, &sysmgr_regs->fpgaintfgrp_module); 341d1c559afSLey Foon Tan writel(0, &sdr_ctrl->fpgaport_rst); 342d1c559afSLey Foon Tan socfpga_sdram_apply_static_cfg(); 343d1c559afSLey Foon Tan writel(0, &reset_manager_base->brg_mod_reset); 344d1c559afSLey Foon Tan writel(1, &nic301_regs->remap); 345d1c559afSLey Foon Tan break; 346d1c559afSLey Foon Tan default: 347d1c559afSLey Foon Tan return CMD_RET_USAGE; 348d1c559afSLey Foon Tan } 349d1c559afSLey Foon Tan 350d1c559afSLey Foon Tan return 0; 351d1c559afSLey Foon Tan } 352d1c559afSLey Foon Tan 353d1c559afSLey Foon Tan U_BOOT_CMD( 354d1c559afSLey Foon Tan bridge, 2, 1, do_bridge, 355d1c559afSLey Foon Tan "SoCFPGA HPS FPGA bridge control", 356d1c559afSLey Foon Tan "enable - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n" 357d1c559afSLey Foon Tan "bridge disable - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n" 358d1c559afSLey Foon Tan "" 359d1c559afSLey Foon Tan ); 360