1 /* 2 * Copyright (C) 2012-2017 Altera Corporation <www.altera.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <asm/io.h> 9 #include <errno.h> 10 #include <fdtdec.h> 11 #include <libfdt.h> 12 #include <altera.h> 13 #include <miiphy.h> 14 #include <netdev.h> 15 #include <watchdog.h> 16 #include <asm/arch/misc.h> 17 #include <asm/arch/reset_manager.h> 18 #include <asm/arch/scan_manager.h> 19 #include <asm/arch/system_manager.h> 20 #include <asm/arch/nic301.h> 21 #include <asm/arch/scu.h> 22 #include <asm/pl310.h> 23 24 DECLARE_GLOBAL_DATA_PTR; 25 26 static const struct pl310_regs *const pl310 = 27 (struct pl310_regs *)CONFIG_SYS_PL310_BASE; 28 29 struct bsel bsel_str[] = { 30 { "rsvd", "Reserved", }, 31 { "fpga", "FPGA (HPS2FPGA Bridge)", }, 32 { "nand", "NAND Flash (1.8V)", }, 33 { "nand", "NAND Flash (3.0V)", }, 34 { "sd", "SD/MMC External Transceiver (1.8V)", }, 35 { "sd", "SD/MMC Internal Transceiver (3.0V)", }, 36 { "qspi", "QSPI Flash (1.8V)", }, 37 { "qspi", "QSPI Flash (3.0V)", }, 38 }; 39 40 int dram_init(void) 41 { 42 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); 43 return 0; 44 } 45 46 void enable_caches(void) 47 { 48 #ifndef CONFIG_SYS_ICACHE_OFF 49 icache_enable(); 50 #endif 51 #ifndef CONFIG_SYS_DCACHE_OFF 52 dcache_enable(); 53 #endif 54 } 55 56 void v7_outer_cache_enable(void) 57 { 58 /* Disable the L2 cache */ 59 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); 60 61 /* enable BRESP, instruction and data prefetch, full line of zeroes */ 62 setbits_le32(&pl310->pl310_aux_ctrl, 63 L310_AUX_CTRL_DATA_PREFETCH_MASK | 64 L310_AUX_CTRL_INST_PREFETCH_MASK | 65 L310_SHARED_ATT_OVERRIDE_ENABLE); 66 67 /* Enable the L2 cache */ 68 setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); 69 } 70 71 void v7_outer_cache_disable(void) 72 { 73 /* Disable the L2 cache */ 74 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); 75 } 76 77 #if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && \ 78 defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE) 79 int overwrite_console(void) 80 { 81 return 0; 82 } 83 #endif 84 85 #ifdef CONFIG_FPGA 86 /* 87 * FPGA programming support for SoC FPGA Cyclone V 88 */ 89 static Altera_desc altera_fpga[] = { 90 { 91 /* Family */ 92 Altera_SoCFPGA, 93 /* Interface type */ 94 fast_passive_parallel, 95 /* No limitation as additional data will be ignored */ 96 -1, 97 /* No device function table */ 98 NULL, 99 /* Base interface address specified in driver */ 100 NULL, 101 /* No cookie implementation */ 102 0 103 }, 104 }; 105 106 /* add device descriptor to FPGA device table */ 107 void socfpga_fpga_add(void) 108 { 109 int i; 110 fpga_init(); 111 for (i = 0; i < ARRAY_SIZE(altera_fpga); i++) 112 fpga_add(fpga_altera, &altera_fpga[i]); 113 } 114 #endif 115 116 int arch_cpu_init(void) 117 { 118 #ifdef CONFIG_HW_WATCHDOG 119 /* 120 * In case the watchdog is enabled, make sure to (re-)configure it 121 * so that the defined timeout is valid. Otherwise the SPL (Perloader) 122 * timeout value is still active which might too short for Linux 123 * booting. 124 */ 125 hw_watchdog_init(); 126 #else 127 /* 128 * If the HW watchdog is NOT enabled, make sure it is not running, 129 * for example because it was enabled in the preloader. This might 130 * trigger a watchdog-triggered reboot of Linux kernel later. 131 * Toggle watchdog reset, so watchdog in not running state. 132 */ 133 socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1); 134 socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0); 135 #endif 136 137 return 0; 138 } 139