1 /* 2 * Copyright (C) 2012 Altera Corporation <www.altera.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <asm/io.h> 9 #include <errno.h> 10 #include <fdtdec.h> 11 #include <libfdt.h> 12 #include <altera.h> 13 #include <miiphy.h> 14 #include <netdev.h> 15 #include <watchdog.h> 16 #include <asm/arch/reset_manager.h> 17 #include <asm/arch/scan_manager.h> 18 #include <asm/arch/system_manager.h> 19 #include <asm/arch/nic301.h> 20 #include <asm/arch/scu.h> 21 #include <asm/pl310.h> 22 23 #include <dt-bindings/reset/altr,rst-mgr.h> 24 25 DECLARE_GLOBAL_DATA_PTR; 26 27 static struct pl310_regs *const pl310 = 28 (struct pl310_regs *)CONFIG_SYS_PL310_BASE; 29 static struct socfpga_system_manager *sysmgr_regs = 30 (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; 31 static struct socfpga_reset_manager *reset_manager_base = 32 (struct socfpga_reset_manager *)SOCFPGA_RSTMGR_ADDRESS; 33 static struct nic301_registers *nic301_regs = 34 (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS; 35 static struct scu_registers *scu_regs = 36 (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS; 37 38 int dram_init(void) 39 { 40 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); 41 return 0; 42 } 43 44 void enable_caches(void) 45 { 46 #ifndef CONFIG_SYS_ICACHE_OFF 47 icache_enable(); 48 #endif 49 #ifndef CONFIG_SYS_DCACHE_OFF 50 dcache_enable(); 51 #endif 52 } 53 54 void v7_outer_cache_enable(void) 55 { 56 /* Disable the L2 cache */ 57 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); 58 59 /* enable BRESP, instruction and data prefetch, full line of zeroes */ 60 setbits_le32(&pl310->pl310_aux_ctrl, 61 L310_AUX_CTRL_DATA_PREFETCH_MASK | 62 L310_AUX_CTRL_INST_PREFETCH_MASK | 63 L310_SHARED_ATT_OVERRIDE_ENABLE); 64 65 /* Enable the L2 cache */ 66 setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); 67 } 68 69 void v7_outer_cache_disable(void) 70 { 71 /* Disable the L2 cache */ 72 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); 73 } 74 75 /* 76 * DesignWare Ethernet initialization 77 */ 78 #ifdef CONFIG_ETH_DESIGNWARE 79 static void dwmac_deassert_reset(const unsigned int of_reset_id, 80 const u32 phymode) 81 { 82 u32 physhift, reset; 83 84 if (of_reset_id == EMAC0_RESET) { 85 physhift = SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB; 86 reset = SOCFPGA_RESET(EMAC0); 87 } else if (of_reset_id == EMAC1_RESET) { 88 physhift = SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB; 89 reset = SOCFPGA_RESET(EMAC1); 90 } else { 91 printf("GMAC: Invalid reset ID (%i)!\n", of_reset_id); 92 return; 93 } 94 95 /* Clearing emac0 PHY interface select to 0 */ 96 clrbits_le32(&sysmgr_regs->emacgrp_ctrl, 97 SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << physhift); 98 99 /* configure to PHY interface select choosed */ 100 setbits_le32(&sysmgr_regs->emacgrp_ctrl, 101 phymode << physhift); 102 103 /* Release the EMAC controller from reset */ 104 socfpga_per_reset(reset, 0); 105 } 106 107 static u32 dwmac_phymode_to_modereg(const char *phymode, u32 *modereg) 108 { 109 if (!phymode) 110 return -EINVAL; 111 112 if (!strcmp(phymode, "mii") || !strcmp(phymode, "gmii")) { 113 *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII; 114 return 0; 115 } 116 117 if (!strcmp(phymode, "rgmii")) { 118 *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII; 119 return 0; 120 } 121 122 if (!strcmp(phymode, "rmii")) { 123 *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII; 124 return 0; 125 } 126 127 return -EINVAL; 128 } 129 130 static int socfpga_eth_reset(void) 131 { 132 const void *fdt = gd->fdt_blob; 133 struct fdtdec_phandle_args args; 134 const char *phy_mode; 135 u32 phy_modereg; 136 int nodes[2]; /* Max. two GMACs */ 137 int ret, count; 138 int i, node; 139 140 /* Put both GMACs into RESET state. */ 141 socfpga_per_reset(SOCFPGA_RESET(EMAC0), 1); 142 socfpga_per_reset(SOCFPGA_RESET(EMAC1), 1); 143 144 count = fdtdec_find_aliases_for_id(fdt, "ethernet", 145 COMPAT_ALTERA_SOCFPGA_DWMAC, 146 nodes, ARRAY_SIZE(nodes)); 147 for (i = 0; i < count; i++) { 148 node = nodes[i]; 149 if (node <= 0) 150 continue; 151 152 ret = fdtdec_parse_phandle_with_args(fdt, node, "resets", 153 "#reset-cells", 1, 0, 154 &args); 155 if (ret || (args.args_count != 1)) { 156 debug("GMAC%i: Failed to parse DT 'resets'!\n", i); 157 continue; 158 } 159 160 phy_mode = fdt_getprop(fdt, node, "phy-mode", NULL); 161 ret = dwmac_phymode_to_modereg(phy_mode, &phy_modereg); 162 if (ret) { 163 debug("GMAC%i: Failed to parse DT 'phy-mode'!\n", i); 164 continue; 165 } 166 167 dwmac_deassert_reset(args.args[0], phy_modereg); 168 } 169 170 return 0; 171 } 172 #else 173 static int socfpga_eth_reset(void) 174 { 175 return 0; 176 }; 177 #endif 178 179 struct { 180 const char *mode; 181 const char *name; 182 } bsel_str[] = { 183 { "rsvd", "Reserved", }, 184 { "fpga", "FPGA (HPS2FPGA Bridge)", }, 185 { "nand", "NAND Flash (1.8V)", }, 186 { "nand", "NAND Flash (3.0V)", }, 187 { "sd", "SD/MMC External Transceiver (1.8V)", }, 188 { "sd", "SD/MMC Internal Transceiver (3.0V)", }, 189 { "qspi", "QSPI Flash (1.8V)", }, 190 { "qspi", "QSPI Flash (3.0V)", }, 191 }; 192 193 static const struct { 194 const u16 pn; 195 const char *name; 196 const char *var; 197 } const socfpga_fpga_model[] = { 198 /* Cyclone V E */ 199 { 0x2b15, "Cyclone V, E/A2", "cv_e_a2" }, 200 { 0x2b05, "Cyclone V, E/A4", "cv_e_a4" }, 201 { 0x2b22, "Cyclone V, E/A5", "cv_e_a5" }, 202 { 0x2b13, "Cyclone V, E/A7", "cv_e_a7" }, 203 { 0x2b14, "Cyclone V, E/A9", "cv_e_a9" }, 204 /* Cyclone V GX/GT */ 205 { 0x2b01, "Cyclone V, GX/C3", "cv_gx_c3" }, 206 { 0x2b12, "Cyclone V, GX/C4", "cv_gx_c4" }, 207 { 0x2b02, "Cyclone V, GX/C5 or GT/D5", "cv_gx_c5" }, 208 { 0x2b03, "Cyclone V, GX/C7 or GT/D7", "cv_gx_c7" }, 209 { 0x2b04, "Cyclone V, GX/C9 or GT/D9", "cv_gx_c9" }, 210 /* Cyclone V SE/SX/ST */ 211 { 0x2d11, "Cyclone V, SE/A2 or SX/C2", "cv_se_a2" }, 212 { 0x2d01, "Cyclone V, SE/A4 or SX/C4", "cv_se_a4" }, 213 { 0x2d12, "Cyclone V, SE/A5 or SX/C5 or ST/D5", "cv_se_a5" }, 214 { 0x2d02, "Cyclone V, SE/A6 or SX/C6 or ST/D6", "cv_se_a6" }, 215 /* Arria V */ 216 { 0x2d03, "Arria V, D5", "av_d5" }, 217 }; 218 219 static int socfpga_fpga_id(const bool print_id) 220 { 221 const u32 altera_mi = 0x6e; 222 const u32 id = scan_mgr_get_fpga_id(); 223 224 const u32 lsb = id & 0x00000001; 225 const u32 mi = (id >> 1) & 0x000007ff; 226 const u32 pn = (id >> 12) & 0x0000ffff; 227 const u32 version = (id >> 28) & 0x0000000f; 228 int i; 229 230 if ((mi != altera_mi) || (lsb != 1)) { 231 printf("FPGA: Not Altera chip ID\n"); 232 return -EINVAL; 233 } 234 235 for (i = 0; i < ARRAY_SIZE(socfpga_fpga_model); i++) 236 if (pn == socfpga_fpga_model[i].pn) 237 break; 238 239 if (i == ARRAY_SIZE(socfpga_fpga_model)) { 240 printf("FPGA: Unknown Altera chip, ID 0x%08x\n", id); 241 return -EINVAL; 242 } 243 244 if (print_id) 245 printf("FPGA: Altera %s, version 0x%01x\n", 246 socfpga_fpga_model[i].name, version); 247 return i; 248 } 249 250 /* 251 * Print CPU information 252 */ 253 #if defined(CONFIG_DISPLAY_CPUINFO) 254 int print_cpuinfo(void) 255 { 256 const u32 bsel = readl(&sysmgr_regs->bootinfo) & 0x7; 257 puts("CPU: Altera SoCFPGA Platform\n"); 258 socfpga_fpga_id(1); 259 printf("BOOT: %s\n", bsel_str[bsel].name); 260 return 0; 261 } 262 #endif 263 264 #ifdef CONFIG_ARCH_MISC_INIT 265 int arch_misc_init(void) 266 { 267 const u32 bsel = readl(&sysmgr_regs->bootinfo) & 0x7; 268 const int fpga_id = socfpga_fpga_id(0); 269 setenv("bootmode", bsel_str[bsel].mode); 270 if (fpga_id >= 0) 271 setenv("fpgatype", socfpga_fpga_model[fpga_id].var); 272 return socfpga_eth_reset(); 273 } 274 #endif 275 276 #if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && \ 277 defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE) 278 int overwrite_console(void) 279 { 280 return 0; 281 } 282 #endif 283 284 #ifdef CONFIG_FPGA 285 /* 286 * FPGA programming support for SoC FPGA Cyclone V 287 */ 288 static Altera_desc altera_fpga[] = { 289 { 290 /* Family */ 291 Altera_SoCFPGA, 292 /* Interface type */ 293 fast_passive_parallel, 294 /* No limitation as additional data will be ignored */ 295 -1, 296 /* No device function table */ 297 NULL, 298 /* Base interface address specified in driver */ 299 NULL, 300 /* No cookie implementation */ 301 0 302 }, 303 }; 304 305 /* add device descriptor to FPGA device table */ 306 static void socfpga_fpga_add(void) 307 { 308 int i; 309 fpga_init(); 310 for (i = 0; i < ARRAY_SIZE(altera_fpga); i++) 311 fpga_add(fpga_altera, &altera_fpga[i]); 312 } 313 #else 314 static inline void socfpga_fpga_add(void) {} 315 #endif 316 317 int arch_cpu_init(void) 318 { 319 #ifdef CONFIG_HW_WATCHDOG 320 /* 321 * In case the watchdog is enabled, make sure to (re-)configure it 322 * so that the defined timeout is valid. Otherwise the SPL (Perloader) 323 * timeout value is still active which might too short for Linux 324 * booting. 325 */ 326 hw_watchdog_init(); 327 #else 328 /* 329 * If the HW watchdog is NOT enabled, make sure it is not running, 330 * for example because it was enabled in the preloader. This might 331 * trigger a watchdog-triggered reboot of Linux kernel later. 332 * Toggle watchdog reset, so watchdog in not running state. 333 */ 334 socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1); 335 socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0); 336 #endif 337 338 return 0; 339 } 340 341 /* 342 * Convert all NIC-301 AMBA slaves from secure to non-secure 343 */ 344 static void socfpga_nic301_slave_ns(void) 345 { 346 writel(0x1, &nic301_regs->lwhps2fpgaregs); 347 writel(0x1, &nic301_regs->hps2fpgaregs); 348 writel(0x1, &nic301_regs->acp); 349 writel(0x1, &nic301_regs->rom); 350 writel(0x1, &nic301_regs->ocram); 351 writel(0x1, &nic301_regs->sdrdata); 352 } 353 354 static uint32_t iswgrp_handoff[8]; 355 356 int arch_early_init_r(void) 357 { 358 int i; 359 360 /* 361 * Write magic value into magic register to unlock support for 362 * issuing warm reset. The ancient kernel code expects this 363 * value to be written into the register by the bootloader, so 364 * to support that old code, we write it here instead of in the 365 * reset_cpu() function just before resetting the CPU. 366 */ 367 writel(0xae9efebc, &sysmgr_regs->romcodegrp_warmramgrp_enable); 368 369 for (i = 0; i < 8; i++) /* Cache initial SW setting regs */ 370 iswgrp_handoff[i] = readl(&sysmgr_regs->iswgrp_handoff[i]); 371 372 socfpga_bridges_reset(1); 373 socfpga_nic301_slave_ns(); 374 375 /* 376 * Private components security: 377 * U-Boot : configure private timer, global timer and cpu component 378 * access as non secure for kernel stage (as required by Linux) 379 */ 380 setbits_le32(&scu_regs->sacr, 0xfff); 381 382 /* Configure the L2 controller to make SDRAM start at 0 */ 383 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET 384 writel(0x2, &nic301_regs->remap); 385 #else 386 writel(0x1, &nic301_regs->remap); /* remap.mpuzero */ 387 writel(0x1, &pl310->pl310_addr_filter_start); 388 #endif 389 390 /* Add device descriptor to FPGA device table */ 391 socfpga_fpga_add(); 392 393 #ifdef CONFIG_DESIGNWARE_SPI 394 /* Get Designware SPI controller out of reset */ 395 socfpga_per_reset(SOCFPGA_RESET(SPIM0), 0); 396 socfpga_per_reset(SOCFPGA_RESET(SPIM1), 0); 397 #endif 398 399 #ifdef CONFIG_NAND_DENALI 400 socfpga_per_reset(SOCFPGA_RESET(NAND), 0); 401 #endif 402 403 return 0; 404 } 405 406 static void socfpga_sdram_apply_static_cfg(void) 407 { 408 const uint32_t staticcfg = SOCFPGA_SDR_ADDRESS + 0x505c; 409 const uint32_t applymask = 0x8; 410 uint32_t val = readl(staticcfg) | applymask; 411 412 /* 413 * SDRAM staticcfg register specific: 414 * When applying the register setting, the CPU must not access 415 * SDRAM. Luckily for us, we can abuse i-cache here to help us 416 * circumvent the SDRAM access issue. The idea is to make sure 417 * that the code is in one full i-cache line by branching past 418 * it and back. Once it is in the i-cache, we execute the core 419 * of the code and apply the register settings. 420 * 421 * The code below uses 7 instructions, while the Cortex-A9 has 422 * 32-byte cachelines, thus the limit is 8 instructions total. 423 */ 424 asm volatile( 425 ".align 5 \n" 426 " b 2f \n" 427 "1: str %0, [%1] \n" 428 " dsb \n" 429 " isb \n" 430 " b 3f \n" 431 "2: b 1b \n" 432 "3: nop \n" 433 : : "r"(val), "r"(staticcfg) : "memory", "cc"); 434 } 435 436 int do_bridge(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 437 { 438 if (argc != 2) 439 return CMD_RET_USAGE; 440 441 argv++; 442 443 switch (*argv[0]) { 444 case 'e': /* Enable */ 445 writel(iswgrp_handoff[2], &sysmgr_regs->fpgaintfgrp_module); 446 socfpga_sdram_apply_static_cfg(); 447 writel(iswgrp_handoff[3], SOCFPGA_SDR_ADDRESS + 0x5080); 448 writel(iswgrp_handoff[0], &reset_manager_base->brg_mod_reset); 449 writel(iswgrp_handoff[1], &nic301_regs->remap); 450 break; 451 case 'd': /* Disable */ 452 writel(0, &sysmgr_regs->fpgaintfgrp_module); 453 writel(0, SOCFPGA_SDR_ADDRESS + 0x5080); 454 socfpga_sdram_apply_static_cfg(); 455 writel(0, &reset_manager_base->brg_mod_reset); 456 writel(1, &nic301_regs->remap); 457 break; 458 default: 459 return CMD_RET_USAGE; 460 } 461 462 return 0; 463 } 464 465 U_BOOT_CMD( 466 bridge, 2, 1, do_bridge, 467 "SoCFPGA HPS FPGA bridge control", 468 "enable - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n" 469 "bridge disable - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n" 470 "" 471 ); 472