1 /* 2 * Copyright (C) 2012 Altera Corporation <www.altera.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <asm/io.h> 9 #include <errno.h> 10 #include <fdtdec.h> 11 #include <libfdt.h> 12 #include <altera.h> 13 #include <miiphy.h> 14 #include <netdev.h> 15 #include <watchdog.h> 16 #include <asm/arch/reset_manager.h> 17 #include <asm/arch/scan_manager.h> 18 #include <asm/arch/system_manager.h> 19 #include <asm/arch/dwmmc.h> 20 #include <asm/arch/nic301.h> 21 #include <asm/arch/scu.h> 22 #include <asm/pl310.h> 23 24 #include <dt-bindings/reset/altr,rst-mgr.h> 25 26 DECLARE_GLOBAL_DATA_PTR; 27 28 static struct pl310_regs *const pl310 = 29 (struct pl310_regs *)CONFIG_SYS_PL310_BASE; 30 static struct socfpga_system_manager *sysmgr_regs = 31 (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; 32 static struct socfpga_reset_manager *reset_manager_base = 33 (struct socfpga_reset_manager *)SOCFPGA_RSTMGR_ADDRESS; 34 static struct nic301_registers *nic301_regs = 35 (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS; 36 static struct scu_registers *scu_regs = 37 (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS; 38 39 int dram_init(void) 40 { 41 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); 42 return 0; 43 } 44 45 void enable_caches(void) 46 { 47 #ifndef CONFIG_SYS_ICACHE_OFF 48 icache_enable(); 49 #endif 50 #ifndef CONFIG_SYS_DCACHE_OFF 51 dcache_enable(); 52 #endif 53 } 54 55 /* 56 * DesignWare Ethernet initialization 57 */ 58 #ifdef CONFIG_ETH_DESIGNWARE 59 static void dwmac_deassert_reset(const unsigned int of_reset_id) 60 { 61 u32 physhift, reset; 62 63 if (of_reset_id == EMAC0_RESET) { 64 physhift = SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB; 65 reset = SOCFPGA_RESET(EMAC0); 66 } else if (of_reset_id == EMAC1_RESET) { 67 physhift = SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB; 68 reset = SOCFPGA_RESET(EMAC1); 69 } else { 70 printf("GMAC: Invalid reset ID (%i)!\n", of_reset_id); 71 return; 72 } 73 74 /* Clearing emac0 PHY interface select to 0 */ 75 clrbits_le32(&sysmgr_regs->emacgrp_ctrl, 76 SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << physhift); 77 78 /* configure to PHY interface select choosed */ 79 setbits_le32(&sysmgr_regs->emacgrp_ctrl, 80 SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII << physhift); 81 82 /* Release the EMAC controller from reset */ 83 socfpga_per_reset(reset, 0); 84 } 85 86 int cpu_eth_init(bd_t *bis) 87 { 88 const void *fdt = gd->fdt_blob; 89 struct fdtdec_phandle_args args; 90 int nodes[2]; /* Max. two GMACs */ 91 int ret, count; 92 int i, node; 93 94 /* Put both GMACs into RESET state. */ 95 socfpga_per_reset(SOCFPGA_RESET(EMAC0), 1); 96 socfpga_per_reset(SOCFPGA_RESET(EMAC1), 1); 97 98 count = fdtdec_find_aliases_for_id(fdt, "ethernet", 99 COMPAT_ALTERA_SOCFPGA_DWMAC, 100 nodes, ARRAY_SIZE(nodes)); 101 for (i = 0; i < count; i++) { 102 node = nodes[i]; 103 if (node <= 0) 104 continue; 105 106 ret = fdtdec_parse_phandle_with_args(fdt, node, "resets", 107 "#reset-cells", 1, 0, 108 &args); 109 if (ret || (args.args_count != 1)) { 110 debug("GMAC%i: Failed to parse DT 'resets'!\n", i); 111 continue; 112 } 113 114 dwmac_deassert_reset(args.args[0]); 115 } 116 117 return 0; 118 } 119 #endif 120 121 #ifdef CONFIG_DWMMC 122 /* 123 * Initializes MMC controllers. 124 * to override, implement board_mmc_init() 125 */ 126 int cpu_mmc_init(bd_t *bis) 127 { 128 /* 129 * FIXME: Temporarily define CONFIG_HPS_SDMMC_BUSWIDTH to prevent breakage 130 * due to missing patches in u-boot/master . The upcoming patch will 131 * switch this to OF probing, so this whole block will go away. 132 */ 133 #define CONFIG_HPS_SDMMC_BUSWIDTH 8 134 return socfpga_dwmmc_init(SOCFPGA_SDMMC_ADDRESS, 135 CONFIG_HPS_SDMMC_BUSWIDTH, 0); 136 } 137 #endif 138 139 struct { 140 const char *mode; 141 const char *name; 142 } bsel_str[] = { 143 { "rsvd", "Reserved", }, 144 { "fpga", "FPGA (HPS2FPGA Bridge)", }, 145 { "nand", "NAND Flash (1.8V)", }, 146 { "nand", "NAND Flash (3.0V)", }, 147 { "sd", "SD/MMC External Transceiver (1.8V)", }, 148 { "sd", "SD/MMC Internal Transceiver (3.0V)", }, 149 { "qspi", "QSPI Flash (1.8V)", }, 150 { "qspi", "QSPI Flash (3.0V)", }, 151 }; 152 153 static const struct { 154 const u16 pn; 155 const char *name; 156 const char *var; 157 } const socfpga_fpga_model[] = { 158 /* Cyclone V E */ 159 { 0x2b15, "Cyclone V, E/A2", "cv_e_a2" }, 160 { 0x2b05, "Cyclone V, E/A4", "cv_e_a4" }, 161 { 0x2b22, "Cyclone V, E/A5", "cv_e_a5" }, 162 { 0x2b13, "Cyclone V, E/A7", "cv_e_a7" }, 163 { 0x2b14, "Cyclone V, E/A9", "cv_e_a9" }, 164 /* Cyclone V GX/GT */ 165 { 0x2b01, "Cyclone V, GX/C3", "cv_gx_c3" }, 166 { 0x2b12, "Cyclone V, GX/C4", "cv_gx_c4" }, 167 { 0x2b02, "Cyclone V, GX/C5 or GT/D5", "cv_gx_c5" }, 168 { 0x2b03, "Cyclone V, GX/C7 or GT/D7", "cv_gx_c7" }, 169 { 0x2b04, "Cyclone V, GX/C9 or GT/D9", "cv_gx_c9" }, 170 /* Cyclone V SE/SX/ST */ 171 { 0x2d11, "Cyclone V, SE/A2 or SX/C2", "cv_se_a2" }, 172 { 0x2d01, "Cyclone V, SE/A4 or SX/C4", "cv_se_a4" }, 173 { 0x2d12, "Cyclone V, SE/A5 or SX/C5 or ST/D5", "cv_se_a5" }, 174 { 0x2d02, "Cyclone V, SE/A6 or SX/C6 or ST/D6", "cv_se_a6" }, 175 /* Arria V */ 176 { 0x2d03, "Arria V, D5", "av_d5" }, 177 }; 178 179 static int socfpga_fpga_id(const bool print_id) 180 { 181 const u32 altera_mi = 0x6e; 182 const u32 id = scan_mgr_get_fpga_id(); 183 184 const u32 lsb = id & 0x00000001; 185 const u32 mi = (id >> 1) & 0x000007ff; 186 const u32 pn = (id >> 12) & 0x0000ffff; 187 const u32 version = (id >> 28) & 0x0000000f; 188 int i; 189 190 if ((mi != altera_mi) || (lsb != 1)) { 191 printf("FPGA: Not Altera chip ID\n"); 192 return -EINVAL; 193 } 194 195 for (i = 0; i < ARRAY_SIZE(socfpga_fpga_model); i++) 196 if (pn == socfpga_fpga_model[i].pn) 197 break; 198 199 if (i == ARRAY_SIZE(socfpga_fpga_model)) { 200 printf("FPGA: Unknown Altera chip, ID 0x%08x\n", id); 201 return -EINVAL; 202 } 203 204 if (print_id) 205 printf("FPGA: Altera %s, version 0x%01x\n", 206 socfpga_fpga_model[i].name, version); 207 return i; 208 } 209 210 /* 211 * Print CPU information 212 */ 213 #if defined(CONFIG_DISPLAY_CPUINFO) 214 int print_cpuinfo(void) 215 { 216 const u32 bsel = readl(&sysmgr_regs->bootinfo) & 0x7; 217 puts("CPU: Altera SoCFPGA Platform\n"); 218 socfpga_fpga_id(1); 219 printf("BOOT: %s\n", bsel_str[bsel].name); 220 return 0; 221 } 222 #endif 223 224 #ifdef CONFIG_ARCH_MISC_INIT 225 int arch_misc_init(void) 226 { 227 const u32 bsel = readl(&sysmgr_regs->bootinfo) & 0x7; 228 const int fpga_id = socfpga_fpga_id(0); 229 setenv("bootmode", bsel_str[bsel].mode); 230 if (fpga_id >= 0) 231 setenv("fpgatype", socfpga_fpga_model[fpga_id].var); 232 return 0; 233 } 234 #endif 235 236 #if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && \ 237 defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE) 238 int overwrite_console(void) 239 { 240 return 0; 241 } 242 #endif 243 244 #ifdef CONFIG_FPGA 245 /* 246 * FPGA programming support for SoC FPGA Cyclone V 247 */ 248 static Altera_desc altera_fpga[] = { 249 { 250 /* Family */ 251 Altera_SoCFPGA, 252 /* Interface type */ 253 fast_passive_parallel, 254 /* No limitation as additional data will be ignored */ 255 -1, 256 /* No device function table */ 257 NULL, 258 /* Base interface address specified in driver */ 259 NULL, 260 /* No cookie implementation */ 261 0 262 }, 263 }; 264 265 /* add device descriptor to FPGA device table */ 266 static void socfpga_fpga_add(void) 267 { 268 int i; 269 fpga_init(); 270 for (i = 0; i < ARRAY_SIZE(altera_fpga); i++) 271 fpga_add(fpga_altera, &altera_fpga[i]); 272 } 273 #else 274 static inline void socfpga_fpga_add(void) {} 275 #endif 276 277 int arch_cpu_init(void) 278 { 279 #ifdef CONFIG_HW_WATCHDOG 280 /* 281 * In case the watchdog is enabled, make sure to (re-)configure it 282 * so that the defined timeout is valid. Otherwise the SPL (Perloader) 283 * timeout value is still active which might too short for Linux 284 * booting. 285 */ 286 hw_watchdog_init(); 287 #else 288 /* 289 * If the HW watchdog is NOT enabled, make sure it is not running, 290 * for example because it was enabled in the preloader. This might 291 * trigger a watchdog-triggered reboot of Linux kernel later. 292 * Toggle watchdog reset, so watchdog in not running state. 293 */ 294 socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1); 295 socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0); 296 #endif 297 298 return 0; 299 } 300 301 /* 302 * Convert all NIC-301 AMBA slaves from secure to non-secure 303 */ 304 static void socfpga_nic301_slave_ns(void) 305 { 306 writel(0x1, &nic301_regs->lwhps2fpgaregs); 307 writel(0x1, &nic301_regs->hps2fpgaregs); 308 writel(0x1, &nic301_regs->acp); 309 writel(0x1, &nic301_regs->rom); 310 writel(0x1, &nic301_regs->ocram); 311 writel(0x1, &nic301_regs->sdrdata); 312 } 313 314 static uint32_t iswgrp_handoff[8]; 315 316 int arch_early_init_r(void) 317 { 318 int i; 319 320 /* 321 * Write magic value into magic register to unlock support for 322 * issuing warm reset. The ancient kernel code expects this 323 * value to be written into the register by the bootloader, so 324 * to support that old code, we write it here instead of in the 325 * reset_cpu() function just before reseting the CPU. 326 */ 327 writel(0xae9efebc, &sysmgr_regs->romcodegrp_warmramgrp_enable); 328 329 for (i = 0; i < 8; i++) /* Cache initial SW setting regs */ 330 iswgrp_handoff[i] = readl(&sysmgr_regs->iswgrp_handoff[i]); 331 332 socfpga_bridges_reset(1); 333 socfpga_nic301_slave_ns(); 334 335 /* 336 * Private components security: 337 * U-Boot : configure private timer, global timer and cpu component 338 * access as non secure for kernel stage (as required by Linux) 339 */ 340 setbits_le32(&scu_regs->sacr, 0xfff); 341 342 /* Configure the L2 controller to make SDRAM start at 0 */ 343 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET 344 writel(0x2, &nic301_regs->remap); 345 #else 346 writel(0x1, &nic301_regs->remap); /* remap.mpuzero */ 347 writel(0x1, &pl310->pl310_addr_filter_start); 348 #endif 349 350 /* Add device descriptor to FPGA device table */ 351 socfpga_fpga_add(); 352 353 #ifdef CONFIG_DESIGNWARE_SPI 354 /* Get Designware SPI controller out of reset */ 355 socfpga_per_reset(SOCFPGA_RESET(SPIM0), 0); 356 socfpga_per_reset(SOCFPGA_RESET(SPIM1), 0); 357 #endif 358 359 return 0; 360 } 361 362 static void socfpga_sdram_apply_static_cfg(void) 363 { 364 const uint32_t staticcfg = SOCFPGA_SDR_ADDRESS + 0x505c; 365 const uint32_t applymask = 0x8; 366 uint32_t val = readl(staticcfg) | applymask; 367 368 /* 369 * SDRAM staticcfg register specific: 370 * When applying the register setting, the CPU must not access 371 * SDRAM. Luckily for us, we can abuse i-cache here to help us 372 * circumvent the SDRAM access issue. The idea is to make sure 373 * that the code is in one full i-cache line by branching past 374 * it and back. Once it is in the i-cache, we execute the core 375 * of the code and apply the register settings. 376 * 377 * The code below uses 7 instructions, while the Cortex-A9 has 378 * 32-byte cachelines, thus the limit is 8 instructions total. 379 */ 380 asm volatile( 381 ".align 5 \n" 382 " b 2f \n" 383 "1: str %0, [%1] \n" 384 " dsb \n" 385 " isb \n" 386 " b 3f \n" 387 "2: b 1b \n" 388 "3: nop \n" 389 : : "r"(val), "r"(staticcfg) : "memory", "cc"); 390 } 391 392 int do_bridge(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 393 { 394 if (argc != 2) 395 return CMD_RET_USAGE; 396 397 argv++; 398 399 switch (*argv[0]) { 400 case 'e': /* Enable */ 401 writel(iswgrp_handoff[2], &sysmgr_regs->fpgaintfgrp_module); 402 socfpga_sdram_apply_static_cfg(); 403 writel(iswgrp_handoff[3], SOCFPGA_SDR_ADDRESS + 0x5080); 404 writel(iswgrp_handoff[0], &reset_manager_base->brg_mod_reset); 405 writel(iswgrp_handoff[1], &nic301_regs->remap); 406 break; 407 case 'd': /* Disable */ 408 writel(0, &sysmgr_regs->fpgaintfgrp_module); 409 writel(0, SOCFPGA_SDR_ADDRESS + 0x5080); 410 socfpga_sdram_apply_static_cfg(); 411 writel(0, &reset_manager_base->brg_mod_reset); 412 writel(1, &nic301_regs->remap); 413 break; 414 default: 415 return CMD_RET_USAGE; 416 } 417 418 return 0; 419 } 420 421 U_BOOT_CMD( 422 bridge, 2, 1, do_bridge, 423 "SoCFPGA HPS FPGA bridge control", 424 "enable - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n" 425 "bridge disable - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n" 426 "" 427 ); 428