1 /* 2 * Copyright (C) 2012 Altera Corporation <www.altera.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <asm/io.h> 9 #include <errno.h> 10 #include <fdtdec.h> 11 #include <libfdt.h> 12 #include <altera.h> 13 #include <miiphy.h> 14 #include <netdev.h> 15 #include <watchdog.h> 16 #include <asm/arch/reset_manager.h> 17 #include <asm/arch/scan_manager.h> 18 #include <asm/arch/system_manager.h> 19 #include <asm/arch/dwmmc.h> 20 #include <asm/arch/nic301.h> 21 #include <asm/arch/scu.h> 22 #include <asm/pl310.h> 23 24 #include <dt-bindings/reset/altr,rst-mgr.h> 25 26 DECLARE_GLOBAL_DATA_PTR; 27 28 static struct pl310_regs *const pl310 = 29 (struct pl310_regs *)CONFIG_SYS_PL310_BASE; 30 static struct socfpga_system_manager *sysmgr_regs = 31 (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; 32 static struct socfpga_reset_manager *reset_manager_base = 33 (struct socfpga_reset_manager *)SOCFPGA_RSTMGR_ADDRESS; 34 static struct nic301_registers *nic301_regs = 35 (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS; 36 static struct scu_registers *scu_regs = 37 (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS; 38 39 int dram_init(void) 40 { 41 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); 42 return 0; 43 } 44 45 void enable_caches(void) 46 { 47 #ifndef CONFIG_SYS_ICACHE_OFF 48 icache_enable(); 49 #endif 50 #ifndef CONFIG_SYS_DCACHE_OFF 51 dcache_enable(); 52 #endif 53 } 54 55 void v7_outer_cache_enable(void) 56 { 57 /* Disable the L2 cache */ 58 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); 59 60 /* enable BRESP, instruction and data prefetch, full line of zeroes */ 61 setbits_le32(&pl310->pl310_aux_ctrl, 62 L310_AUX_CTRL_DATA_PREFETCH_MASK | 63 L310_AUX_CTRL_INST_PREFETCH_MASK | 64 L310_SHARED_ATT_OVERRIDE_ENABLE); 65 66 /* Enable the L2 cache */ 67 setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); 68 } 69 70 void v7_outer_cache_disable(void) 71 { 72 /* Disable the L2 cache */ 73 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); 74 } 75 76 /* 77 * DesignWare Ethernet initialization 78 */ 79 #ifdef CONFIG_ETH_DESIGNWARE 80 static void dwmac_deassert_reset(const unsigned int of_reset_id) 81 { 82 u32 physhift, reset; 83 84 if (of_reset_id == EMAC0_RESET) { 85 physhift = SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB; 86 reset = SOCFPGA_RESET(EMAC0); 87 } else if (of_reset_id == EMAC1_RESET) { 88 physhift = SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB; 89 reset = SOCFPGA_RESET(EMAC1); 90 } else { 91 printf("GMAC: Invalid reset ID (%i)!\n", of_reset_id); 92 return; 93 } 94 95 /* Clearing emac0 PHY interface select to 0 */ 96 clrbits_le32(&sysmgr_regs->emacgrp_ctrl, 97 SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << physhift); 98 99 /* configure to PHY interface select choosed */ 100 setbits_le32(&sysmgr_regs->emacgrp_ctrl, 101 SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII << physhift); 102 103 /* Release the EMAC controller from reset */ 104 socfpga_per_reset(reset, 0); 105 } 106 107 static int socfpga_eth_reset(void) 108 { 109 const void *fdt = gd->fdt_blob; 110 struct fdtdec_phandle_args args; 111 int nodes[2]; /* Max. two GMACs */ 112 int ret, count; 113 int i, node; 114 115 /* Put both GMACs into RESET state. */ 116 socfpga_per_reset(SOCFPGA_RESET(EMAC0), 1); 117 socfpga_per_reset(SOCFPGA_RESET(EMAC1), 1); 118 119 count = fdtdec_find_aliases_for_id(fdt, "ethernet", 120 COMPAT_ALTERA_SOCFPGA_DWMAC, 121 nodes, ARRAY_SIZE(nodes)); 122 for (i = 0; i < count; i++) { 123 node = nodes[i]; 124 if (node <= 0) 125 continue; 126 127 ret = fdtdec_parse_phandle_with_args(fdt, node, "resets", 128 "#reset-cells", 1, 0, 129 &args); 130 if (ret || (args.args_count != 1)) { 131 debug("GMAC%i: Failed to parse DT 'resets'!\n", i); 132 continue; 133 } 134 135 dwmac_deassert_reset(args.args[0]); 136 } 137 138 return 0; 139 } 140 #else 141 static int socfpga_eth_reset(void) 142 { 143 return 0 144 }; 145 #endif 146 147 struct { 148 const char *mode; 149 const char *name; 150 } bsel_str[] = { 151 { "rsvd", "Reserved", }, 152 { "fpga", "FPGA (HPS2FPGA Bridge)", }, 153 { "nand", "NAND Flash (1.8V)", }, 154 { "nand", "NAND Flash (3.0V)", }, 155 { "sd", "SD/MMC External Transceiver (1.8V)", }, 156 { "sd", "SD/MMC Internal Transceiver (3.0V)", }, 157 { "qspi", "QSPI Flash (1.8V)", }, 158 { "qspi", "QSPI Flash (3.0V)", }, 159 }; 160 161 static const struct { 162 const u16 pn; 163 const char *name; 164 const char *var; 165 } const socfpga_fpga_model[] = { 166 /* Cyclone V E */ 167 { 0x2b15, "Cyclone V, E/A2", "cv_e_a2" }, 168 { 0x2b05, "Cyclone V, E/A4", "cv_e_a4" }, 169 { 0x2b22, "Cyclone V, E/A5", "cv_e_a5" }, 170 { 0x2b13, "Cyclone V, E/A7", "cv_e_a7" }, 171 { 0x2b14, "Cyclone V, E/A9", "cv_e_a9" }, 172 /* Cyclone V GX/GT */ 173 { 0x2b01, "Cyclone V, GX/C3", "cv_gx_c3" }, 174 { 0x2b12, "Cyclone V, GX/C4", "cv_gx_c4" }, 175 { 0x2b02, "Cyclone V, GX/C5 or GT/D5", "cv_gx_c5" }, 176 { 0x2b03, "Cyclone V, GX/C7 or GT/D7", "cv_gx_c7" }, 177 { 0x2b04, "Cyclone V, GX/C9 or GT/D9", "cv_gx_c9" }, 178 /* Cyclone V SE/SX/ST */ 179 { 0x2d11, "Cyclone V, SE/A2 or SX/C2", "cv_se_a2" }, 180 { 0x2d01, "Cyclone V, SE/A4 or SX/C4", "cv_se_a4" }, 181 { 0x2d12, "Cyclone V, SE/A5 or SX/C5 or ST/D5", "cv_se_a5" }, 182 { 0x2d02, "Cyclone V, SE/A6 or SX/C6 or ST/D6", "cv_se_a6" }, 183 /* Arria V */ 184 { 0x2d03, "Arria V, D5", "av_d5" }, 185 }; 186 187 static int socfpga_fpga_id(const bool print_id) 188 { 189 const u32 altera_mi = 0x6e; 190 const u32 id = scan_mgr_get_fpga_id(); 191 192 const u32 lsb = id & 0x00000001; 193 const u32 mi = (id >> 1) & 0x000007ff; 194 const u32 pn = (id >> 12) & 0x0000ffff; 195 const u32 version = (id >> 28) & 0x0000000f; 196 int i; 197 198 if ((mi != altera_mi) || (lsb != 1)) { 199 printf("FPGA: Not Altera chip ID\n"); 200 return -EINVAL; 201 } 202 203 for (i = 0; i < ARRAY_SIZE(socfpga_fpga_model); i++) 204 if (pn == socfpga_fpga_model[i].pn) 205 break; 206 207 if (i == ARRAY_SIZE(socfpga_fpga_model)) { 208 printf("FPGA: Unknown Altera chip, ID 0x%08x\n", id); 209 return -EINVAL; 210 } 211 212 if (print_id) 213 printf("FPGA: Altera %s, version 0x%01x\n", 214 socfpga_fpga_model[i].name, version); 215 return i; 216 } 217 218 /* 219 * Print CPU information 220 */ 221 #if defined(CONFIG_DISPLAY_CPUINFO) 222 int print_cpuinfo(void) 223 { 224 const u32 bsel = readl(&sysmgr_regs->bootinfo) & 0x7; 225 puts("CPU: Altera SoCFPGA Platform\n"); 226 socfpga_fpga_id(1); 227 printf("BOOT: %s\n", bsel_str[bsel].name); 228 return 0; 229 } 230 #endif 231 232 #ifdef CONFIG_ARCH_MISC_INIT 233 int arch_misc_init(void) 234 { 235 const u32 bsel = readl(&sysmgr_regs->bootinfo) & 0x7; 236 const int fpga_id = socfpga_fpga_id(0); 237 setenv("bootmode", bsel_str[bsel].mode); 238 if (fpga_id >= 0) 239 setenv("fpgatype", socfpga_fpga_model[fpga_id].var); 240 return socfpga_eth_reset(); 241 } 242 #endif 243 244 #if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && \ 245 defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE) 246 int overwrite_console(void) 247 { 248 return 0; 249 } 250 #endif 251 252 #ifdef CONFIG_FPGA 253 /* 254 * FPGA programming support for SoC FPGA Cyclone V 255 */ 256 static Altera_desc altera_fpga[] = { 257 { 258 /* Family */ 259 Altera_SoCFPGA, 260 /* Interface type */ 261 fast_passive_parallel, 262 /* No limitation as additional data will be ignored */ 263 -1, 264 /* No device function table */ 265 NULL, 266 /* Base interface address specified in driver */ 267 NULL, 268 /* No cookie implementation */ 269 0 270 }, 271 }; 272 273 /* add device descriptor to FPGA device table */ 274 static void socfpga_fpga_add(void) 275 { 276 int i; 277 fpga_init(); 278 for (i = 0; i < ARRAY_SIZE(altera_fpga); i++) 279 fpga_add(fpga_altera, &altera_fpga[i]); 280 } 281 #else 282 static inline void socfpga_fpga_add(void) {} 283 #endif 284 285 int arch_cpu_init(void) 286 { 287 #ifdef CONFIG_HW_WATCHDOG 288 /* 289 * In case the watchdog is enabled, make sure to (re-)configure it 290 * so that the defined timeout is valid. Otherwise the SPL (Perloader) 291 * timeout value is still active which might too short for Linux 292 * booting. 293 */ 294 hw_watchdog_init(); 295 #else 296 /* 297 * If the HW watchdog is NOT enabled, make sure it is not running, 298 * for example because it was enabled in the preloader. This might 299 * trigger a watchdog-triggered reboot of Linux kernel later. 300 * Toggle watchdog reset, so watchdog in not running state. 301 */ 302 socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1); 303 socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0); 304 #endif 305 306 return 0; 307 } 308 309 /* 310 * Convert all NIC-301 AMBA slaves from secure to non-secure 311 */ 312 static void socfpga_nic301_slave_ns(void) 313 { 314 writel(0x1, &nic301_regs->lwhps2fpgaregs); 315 writel(0x1, &nic301_regs->hps2fpgaregs); 316 writel(0x1, &nic301_regs->acp); 317 writel(0x1, &nic301_regs->rom); 318 writel(0x1, &nic301_regs->ocram); 319 writel(0x1, &nic301_regs->sdrdata); 320 } 321 322 static uint32_t iswgrp_handoff[8]; 323 324 int arch_early_init_r(void) 325 { 326 int i; 327 328 /* 329 * Write magic value into magic register to unlock support for 330 * issuing warm reset. The ancient kernel code expects this 331 * value to be written into the register by the bootloader, so 332 * to support that old code, we write it here instead of in the 333 * reset_cpu() function just before reseting the CPU. 334 */ 335 writel(0xae9efebc, &sysmgr_regs->romcodegrp_warmramgrp_enable); 336 337 for (i = 0; i < 8; i++) /* Cache initial SW setting regs */ 338 iswgrp_handoff[i] = readl(&sysmgr_regs->iswgrp_handoff[i]); 339 340 socfpga_bridges_reset(1); 341 socfpga_nic301_slave_ns(); 342 343 /* 344 * Private components security: 345 * U-Boot : configure private timer, global timer and cpu component 346 * access as non secure for kernel stage (as required by Linux) 347 */ 348 setbits_le32(&scu_regs->sacr, 0xfff); 349 350 /* Configure the L2 controller to make SDRAM start at 0 */ 351 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET 352 writel(0x2, &nic301_regs->remap); 353 #else 354 writel(0x1, &nic301_regs->remap); /* remap.mpuzero */ 355 writel(0x1, &pl310->pl310_addr_filter_start); 356 #endif 357 358 /* Add device descriptor to FPGA device table */ 359 socfpga_fpga_add(); 360 361 #ifdef CONFIG_DESIGNWARE_SPI 362 /* Get Designware SPI controller out of reset */ 363 socfpga_per_reset(SOCFPGA_RESET(SPIM0), 0); 364 socfpga_per_reset(SOCFPGA_RESET(SPIM1), 0); 365 #endif 366 367 #ifdef CONFIG_NAND_DENALI 368 socfpga_per_reset(SOCFPGA_RESET(NAND), 0); 369 #endif 370 371 return 0; 372 } 373 374 static void socfpga_sdram_apply_static_cfg(void) 375 { 376 const uint32_t staticcfg = SOCFPGA_SDR_ADDRESS + 0x505c; 377 const uint32_t applymask = 0x8; 378 uint32_t val = readl(staticcfg) | applymask; 379 380 /* 381 * SDRAM staticcfg register specific: 382 * When applying the register setting, the CPU must not access 383 * SDRAM. Luckily for us, we can abuse i-cache here to help us 384 * circumvent the SDRAM access issue. The idea is to make sure 385 * that the code is in one full i-cache line by branching past 386 * it and back. Once it is in the i-cache, we execute the core 387 * of the code and apply the register settings. 388 * 389 * The code below uses 7 instructions, while the Cortex-A9 has 390 * 32-byte cachelines, thus the limit is 8 instructions total. 391 */ 392 asm volatile( 393 ".align 5 \n" 394 " b 2f \n" 395 "1: str %0, [%1] \n" 396 " dsb \n" 397 " isb \n" 398 " b 3f \n" 399 "2: b 1b \n" 400 "3: nop \n" 401 : : "r"(val), "r"(staticcfg) : "memory", "cc"); 402 } 403 404 int do_bridge(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 405 { 406 if (argc != 2) 407 return CMD_RET_USAGE; 408 409 argv++; 410 411 switch (*argv[0]) { 412 case 'e': /* Enable */ 413 writel(iswgrp_handoff[2], &sysmgr_regs->fpgaintfgrp_module); 414 socfpga_sdram_apply_static_cfg(); 415 writel(iswgrp_handoff[3], SOCFPGA_SDR_ADDRESS + 0x5080); 416 writel(iswgrp_handoff[0], &reset_manager_base->brg_mod_reset); 417 writel(iswgrp_handoff[1], &nic301_regs->remap); 418 break; 419 case 'd': /* Disable */ 420 writel(0, &sysmgr_regs->fpgaintfgrp_module); 421 writel(0, SOCFPGA_SDR_ADDRESS + 0x5080); 422 socfpga_sdram_apply_static_cfg(); 423 writel(0, &reset_manager_base->brg_mod_reset); 424 writel(1, &nic301_regs->remap); 425 break; 426 default: 427 return CMD_RET_USAGE; 428 } 429 430 return 0; 431 } 432 433 U_BOOT_CMD( 434 bridge, 2, 1, do_bridge, 435 "SoCFPGA HPS FPGA bridge control", 436 "enable - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n" 437 "bridge disable - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n" 438 "" 439 ); 440