1 /* 2 * Copyright (C) 2012 Altera Corporation <www.altera.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <asm/io.h> 9 #include <fdtdec.h> 10 #include <libfdt.h> 11 #include <altera.h> 12 #include <miiphy.h> 13 #include <netdev.h> 14 #include <watchdog.h> 15 #include <asm/arch/reset_manager.h> 16 #include <asm/arch/system_manager.h> 17 #include <asm/arch/dwmmc.h> 18 #include <asm/arch/nic301.h> 19 #include <asm/arch/scu.h> 20 #include <asm/pl310.h> 21 22 #include <dt-bindings/reset/altr,rst-mgr.h> 23 24 DECLARE_GLOBAL_DATA_PTR; 25 26 static struct pl310_regs *const pl310 = 27 (struct pl310_regs *)CONFIG_SYS_PL310_BASE; 28 static struct socfpga_system_manager *sysmgr_regs = 29 (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; 30 static struct socfpga_reset_manager *reset_manager_base = 31 (struct socfpga_reset_manager *)SOCFPGA_RSTMGR_ADDRESS; 32 static struct nic301_registers *nic301_regs = 33 (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS; 34 static struct scu_registers *scu_regs = 35 (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS; 36 37 int dram_init(void) 38 { 39 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); 40 return 0; 41 } 42 43 void enable_caches(void) 44 { 45 #ifndef CONFIG_SYS_ICACHE_OFF 46 icache_enable(); 47 #endif 48 #ifndef CONFIG_SYS_DCACHE_OFF 49 dcache_enable(); 50 #endif 51 } 52 53 /* 54 * DesignWare Ethernet initialization 55 */ 56 #ifdef CONFIG_ETH_DESIGNWARE 57 static void dwmac_deassert_reset(const unsigned int of_reset_id) 58 { 59 u32 physhift, reset; 60 61 if (of_reset_id == EMAC0_RESET) { 62 physhift = SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB; 63 reset = SOCFPGA_RESET(EMAC0); 64 } else if (of_reset_id == EMAC1_RESET) { 65 physhift = SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB; 66 reset = SOCFPGA_RESET(EMAC1); 67 } else { 68 printf("GMAC: Invalid reset ID (%i)!\n", of_reset_id); 69 return; 70 } 71 72 /* Clearing emac0 PHY interface select to 0 */ 73 clrbits_le32(&sysmgr_regs->emacgrp_ctrl, 74 SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << physhift); 75 76 /* configure to PHY interface select choosed */ 77 setbits_le32(&sysmgr_regs->emacgrp_ctrl, 78 SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII << physhift); 79 80 /* Release the EMAC controller from reset */ 81 socfpga_per_reset(reset, 0); 82 } 83 84 int cpu_eth_init(bd_t *bis) 85 { 86 const void *fdt = gd->fdt_blob; 87 struct fdtdec_phandle_args args; 88 int nodes[2]; /* Max. two GMACs */ 89 int ret, count; 90 int i, node; 91 92 /* Put both GMACs into RESET state. */ 93 socfpga_per_reset(SOCFPGA_RESET(EMAC0), 1); 94 socfpga_per_reset(SOCFPGA_RESET(EMAC1), 1); 95 96 count = fdtdec_find_aliases_for_id(fdt, "ethernet", 97 COMPAT_ALTERA_SOCFPGA_DWMAC, 98 nodes, ARRAY_SIZE(nodes)); 99 for (i = 0; i < count; i++) { 100 node = nodes[i]; 101 if (node <= 0) 102 continue; 103 104 ret = fdtdec_parse_phandle_with_args(fdt, node, "resets", 105 "#reset-cells", 1, 0, 106 &args); 107 if (ret || (args.args_count != 1)) { 108 debug("GMAC%i: Failed to parse DT 'resets'!\n", i); 109 continue; 110 } 111 112 dwmac_deassert_reset(args.args[0]); 113 } 114 115 return 0; 116 } 117 #endif 118 119 #ifdef CONFIG_DWMMC 120 /* 121 * Initializes MMC controllers. 122 * to override, implement board_mmc_init() 123 */ 124 int cpu_mmc_init(bd_t *bis) 125 { 126 return socfpga_dwmmc_init(SOCFPGA_SDMMC_ADDRESS, 127 CONFIG_HPS_SDMMC_BUSWIDTH, 0); 128 } 129 #endif 130 131 struct { 132 const char *mode; 133 const char *name; 134 } bsel_str[] = { 135 { "rsvd", "Reserved", }, 136 { "fpga", "FPGA (HPS2FPGA Bridge)", }, 137 { "nand", "NAND Flash (1.8V)", }, 138 { "nand", "NAND Flash (3.0V)", }, 139 { "sd", "SD/MMC External Transceiver (1.8V)", }, 140 { "sd", "SD/MMC Internal Transceiver (3.0V)", }, 141 { "qspi", "QSPI Flash (1.8V)", }, 142 { "qspi", "QSPI Flash (3.0V)", }, 143 }; 144 145 /* 146 * Print CPU information 147 */ 148 #if defined(CONFIG_DISPLAY_CPUINFO) 149 int print_cpuinfo(void) 150 { 151 const u32 bsel = readl(&sysmgr_regs->bootinfo) & 0x7; 152 puts("CPU: Altera SoCFPGA Platform\n"); 153 printf("BOOT: %s\n", bsel_str[bsel].name); 154 return 0; 155 } 156 #endif 157 158 #ifdef CONFIG_ARCH_MISC_INIT 159 int arch_misc_init(void) 160 { 161 const u32 bsel = readl(&sysmgr_regs->bootinfo) & 0x7; 162 setenv("bootmode", bsel_str[bsel].mode); 163 return 0; 164 } 165 #endif 166 167 #if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && \ 168 defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE) 169 int overwrite_console(void) 170 { 171 return 0; 172 } 173 #endif 174 175 #ifdef CONFIG_FPGA 176 /* 177 * FPGA programming support for SoC FPGA Cyclone V 178 */ 179 static Altera_desc altera_fpga[] = { 180 { 181 /* Family */ 182 Altera_SoCFPGA, 183 /* Interface type */ 184 fast_passive_parallel, 185 /* No limitation as additional data will be ignored */ 186 -1, 187 /* No device function table */ 188 NULL, 189 /* Base interface address specified in driver */ 190 NULL, 191 /* No cookie implementation */ 192 0 193 }, 194 }; 195 196 /* add device descriptor to FPGA device table */ 197 static void socfpga_fpga_add(void) 198 { 199 int i; 200 fpga_init(); 201 for (i = 0; i < ARRAY_SIZE(altera_fpga); i++) 202 fpga_add(fpga_altera, &altera_fpga[i]); 203 } 204 #else 205 static inline void socfpga_fpga_add(void) {} 206 #endif 207 208 int arch_cpu_init(void) 209 { 210 #ifdef CONFIG_HW_WATCHDOG 211 /* 212 * In case the watchdog is enabled, make sure to (re-)configure it 213 * so that the defined timeout is valid. Otherwise the SPL (Perloader) 214 * timeout value is still active which might too short for Linux 215 * booting. 216 */ 217 hw_watchdog_init(); 218 #else 219 /* 220 * If the HW watchdog is NOT enabled, make sure it is not running, 221 * for example because it was enabled in the preloader. This might 222 * trigger a watchdog-triggered reboot of Linux kernel later. 223 * Toggle watchdog reset, so watchdog in not running state. 224 */ 225 socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1); 226 socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0); 227 #endif 228 229 return 0; 230 } 231 232 /* 233 * Convert all NIC-301 AMBA slaves from secure to non-secure 234 */ 235 static void socfpga_nic301_slave_ns(void) 236 { 237 writel(0x1, &nic301_regs->lwhps2fpgaregs); 238 writel(0x1, &nic301_regs->hps2fpgaregs); 239 writel(0x1, &nic301_regs->acp); 240 writel(0x1, &nic301_regs->rom); 241 writel(0x1, &nic301_regs->ocram); 242 writel(0x1, &nic301_regs->sdrdata); 243 } 244 245 static uint32_t iswgrp_handoff[8]; 246 247 int arch_early_init_r(void) 248 { 249 int i; 250 251 /* 252 * Write magic value into magic register to unlock support for 253 * issuing warm reset. The ancient kernel code expects this 254 * value to be written into the register by the bootloader, so 255 * to support that old code, we write it here instead of in the 256 * reset_cpu() function just before reseting the CPU. 257 */ 258 writel(0xae9efebc, &sysmgr_regs->romcodegrp_warmramgrp_enable); 259 260 for (i = 0; i < 8; i++) /* Cache initial SW setting regs */ 261 iswgrp_handoff[i] = readl(&sysmgr_regs->iswgrp_handoff[i]); 262 263 socfpga_bridges_reset(1); 264 socfpga_nic301_slave_ns(); 265 266 /* 267 * Private components security: 268 * U-Boot : configure private timer, global timer and cpu component 269 * access as non secure for kernel stage (as required by Linux) 270 */ 271 setbits_le32(&scu_regs->sacr, 0xfff); 272 273 /* Configure the L2 controller to make SDRAM start at 0 */ 274 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET 275 writel(0x2, &nic301_regs->remap); 276 #else 277 writel(0x1, &nic301_regs->remap); /* remap.mpuzero */ 278 writel(0x1, &pl310->pl310_addr_filter_start); 279 #endif 280 281 /* Add device descriptor to FPGA device table */ 282 socfpga_fpga_add(); 283 284 #ifdef CONFIG_DESIGNWARE_SPI 285 /* Get Designware SPI controller out of reset */ 286 socfpga_per_reset(SOCFPGA_RESET(SPIM0), 0); 287 socfpga_per_reset(SOCFPGA_RESET(SPIM1), 0); 288 #endif 289 290 return 0; 291 } 292 293 static void socfpga_sdram_apply_static_cfg(void) 294 { 295 const uint32_t staticcfg = SOCFPGA_SDR_ADDRESS + 0x505c; 296 const uint32_t applymask = 0x8; 297 uint32_t val = readl(staticcfg) | applymask; 298 299 /* 300 * SDRAM staticcfg register specific: 301 * When applying the register setting, the CPU must not access 302 * SDRAM. Luckily for us, we can abuse i-cache here to help us 303 * circumvent the SDRAM access issue. The idea is to make sure 304 * that the code is in one full i-cache line by branching past 305 * it and back. Once it is in the i-cache, we execute the core 306 * of the code and apply the register settings. 307 * 308 * The code below uses 7 instructions, while the Cortex-A9 has 309 * 32-byte cachelines, thus the limit is 8 instructions total. 310 */ 311 asm volatile( 312 ".align 5 \n" 313 " b 2f \n" 314 "1: str %0, [%1] \n" 315 " dsb \n" 316 " isb \n" 317 " b 3f \n" 318 "2: b 1b \n" 319 "3: nop \n" 320 : : "r"(val), "r"(staticcfg) : "memory", "cc"); 321 } 322 323 int do_bridge(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 324 { 325 if (argc != 2) 326 return CMD_RET_USAGE; 327 328 argv++; 329 330 switch (*argv[0]) { 331 case 'e': /* Enable */ 332 writel(iswgrp_handoff[2], &sysmgr_regs->fpgaintfgrp_module); 333 socfpga_sdram_apply_static_cfg(); 334 writel(iswgrp_handoff[3], SOCFPGA_SDR_ADDRESS + 0x5080); 335 writel(iswgrp_handoff[0], &reset_manager_base->brg_mod_reset); 336 writel(iswgrp_handoff[1], &nic301_regs->remap); 337 break; 338 case 'd': /* Disable */ 339 writel(0, &sysmgr_regs->fpgaintfgrp_module); 340 writel(0, SOCFPGA_SDR_ADDRESS + 0x5080); 341 socfpga_sdram_apply_static_cfg(); 342 writel(0, &reset_manager_base->brg_mod_reset); 343 writel(1, &nic301_regs->remap); 344 break; 345 default: 346 return CMD_RET_USAGE; 347 } 348 349 return 0; 350 } 351 352 U_BOOT_CMD( 353 bridge, 2, 1, do_bridge, 354 "SoCFPGA HPS FPGA bridge control", 355 "enable - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n" 356 "bridge disable - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n" 357 "" 358 ); 359