1 /* 2 * Copyright (C) 2012 Altera Corporation <www.altera.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <asm/io.h> 9 #include <errno.h> 10 #include <fdtdec.h> 11 #include <libfdt.h> 12 #include <altera.h> 13 #include <miiphy.h> 14 #include <netdev.h> 15 #include <watchdog.h> 16 #include <asm/arch/reset_manager.h> 17 #include <asm/arch/scan_manager.h> 18 #include <asm/arch/system_manager.h> 19 #include <asm/arch/dwmmc.h> 20 #include <asm/arch/nic301.h> 21 #include <asm/arch/scu.h> 22 #include <asm/pl310.h> 23 24 #include <dt-bindings/reset/altr,rst-mgr.h> 25 26 DECLARE_GLOBAL_DATA_PTR; 27 28 static struct pl310_regs *const pl310 = 29 (struct pl310_regs *)CONFIG_SYS_PL310_BASE; 30 static struct socfpga_system_manager *sysmgr_regs = 31 (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; 32 static struct socfpga_reset_manager *reset_manager_base = 33 (struct socfpga_reset_manager *)SOCFPGA_RSTMGR_ADDRESS; 34 static struct nic301_registers *nic301_regs = 35 (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS; 36 static struct scu_registers *scu_regs = 37 (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS; 38 39 int dram_init(void) 40 { 41 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); 42 return 0; 43 } 44 45 void enable_caches(void) 46 { 47 #ifndef CONFIG_SYS_ICACHE_OFF 48 icache_enable(); 49 #endif 50 #ifndef CONFIG_SYS_DCACHE_OFF 51 dcache_enable(); 52 #endif 53 } 54 55 /* 56 * DesignWare Ethernet initialization 57 */ 58 #ifdef CONFIG_ETH_DESIGNWARE 59 static void dwmac_deassert_reset(const unsigned int of_reset_id) 60 { 61 u32 physhift, reset; 62 63 if (of_reset_id == EMAC0_RESET) { 64 physhift = SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB; 65 reset = SOCFPGA_RESET(EMAC0); 66 } else if (of_reset_id == EMAC1_RESET) { 67 physhift = SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB; 68 reset = SOCFPGA_RESET(EMAC1); 69 } else { 70 printf("GMAC: Invalid reset ID (%i)!\n", of_reset_id); 71 return; 72 } 73 74 /* Clearing emac0 PHY interface select to 0 */ 75 clrbits_le32(&sysmgr_regs->emacgrp_ctrl, 76 SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << physhift); 77 78 /* configure to PHY interface select choosed */ 79 setbits_le32(&sysmgr_regs->emacgrp_ctrl, 80 SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII << physhift); 81 82 /* Release the EMAC controller from reset */ 83 socfpga_per_reset(reset, 0); 84 } 85 86 int cpu_eth_init(bd_t *bis) 87 { 88 const void *fdt = gd->fdt_blob; 89 struct fdtdec_phandle_args args; 90 int nodes[2]; /* Max. two GMACs */ 91 int ret, count; 92 int i, node; 93 94 /* Put both GMACs into RESET state. */ 95 socfpga_per_reset(SOCFPGA_RESET(EMAC0), 1); 96 socfpga_per_reset(SOCFPGA_RESET(EMAC1), 1); 97 98 count = fdtdec_find_aliases_for_id(fdt, "ethernet", 99 COMPAT_ALTERA_SOCFPGA_DWMAC, 100 nodes, ARRAY_SIZE(nodes)); 101 for (i = 0; i < count; i++) { 102 node = nodes[i]; 103 if (node <= 0) 104 continue; 105 106 ret = fdtdec_parse_phandle_with_args(fdt, node, "resets", 107 "#reset-cells", 1, 0, 108 &args); 109 if (ret || (args.args_count != 1)) { 110 debug("GMAC%i: Failed to parse DT 'resets'!\n", i); 111 continue; 112 } 113 114 dwmac_deassert_reset(args.args[0]); 115 } 116 117 return 0; 118 } 119 #endif 120 121 #ifdef CONFIG_DWMMC 122 /* 123 * Initializes MMC controllers. 124 * to override, implement board_mmc_init() 125 */ 126 int cpu_mmc_init(bd_t *bis) 127 { 128 return socfpga_dwmmc_init(gd->fdt_blob); 129 } 130 #endif 131 132 struct { 133 const char *mode; 134 const char *name; 135 } bsel_str[] = { 136 { "rsvd", "Reserved", }, 137 { "fpga", "FPGA (HPS2FPGA Bridge)", }, 138 { "nand", "NAND Flash (1.8V)", }, 139 { "nand", "NAND Flash (3.0V)", }, 140 { "sd", "SD/MMC External Transceiver (1.8V)", }, 141 { "sd", "SD/MMC Internal Transceiver (3.0V)", }, 142 { "qspi", "QSPI Flash (1.8V)", }, 143 { "qspi", "QSPI Flash (3.0V)", }, 144 }; 145 146 static const struct { 147 const u16 pn; 148 const char *name; 149 const char *var; 150 } const socfpga_fpga_model[] = { 151 /* Cyclone V E */ 152 { 0x2b15, "Cyclone V, E/A2", "cv_e_a2" }, 153 { 0x2b05, "Cyclone V, E/A4", "cv_e_a4" }, 154 { 0x2b22, "Cyclone V, E/A5", "cv_e_a5" }, 155 { 0x2b13, "Cyclone V, E/A7", "cv_e_a7" }, 156 { 0x2b14, "Cyclone V, E/A9", "cv_e_a9" }, 157 /* Cyclone V GX/GT */ 158 { 0x2b01, "Cyclone V, GX/C3", "cv_gx_c3" }, 159 { 0x2b12, "Cyclone V, GX/C4", "cv_gx_c4" }, 160 { 0x2b02, "Cyclone V, GX/C5 or GT/D5", "cv_gx_c5" }, 161 { 0x2b03, "Cyclone V, GX/C7 or GT/D7", "cv_gx_c7" }, 162 { 0x2b04, "Cyclone V, GX/C9 or GT/D9", "cv_gx_c9" }, 163 /* Cyclone V SE/SX/ST */ 164 { 0x2d11, "Cyclone V, SE/A2 or SX/C2", "cv_se_a2" }, 165 { 0x2d01, "Cyclone V, SE/A4 or SX/C4", "cv_se_a4" }, 166 { 0x2d12, "Cyclone V, SE/A5 or SX/C5 or ST/D5", "cv_se_a5" }, 167 { 0x2d02, "Cyclone V, SE/A6 or SX/C6 or ST/D6", "cv_se_a6" }, 168 /* Arria V */ 169 { 0x2d03, "Arria V, D5", "av_d5" }, 170 }; 171 172 static int socfpga_fpga_id(const bool print_id) 173 { 174 const u32 altera_mi = 0x6e; 175 const u32 id = scan_mgr_get_fpga_id(); 176 177 const u32 lsb = id & 0x00000001; 178 const u32 mi = (id >> 1) & 0x000007ff; 179 const u32 pn = (id >> 12) & 0x0000ffff; 180 const u32 version = (id >> 28) & 0x0000000f; 181 int i; 182 183 if ((mi != altera_mi) || (lsb != 1)) { 184 printf("FPGA: Not Altera chip ID\n"); 185 return -EINVAL; 186 } 187 188 for (i = 0; i < ARRAY_SIZE(socfpga_fpga_model); i++) 189 if (pn == socfpga_fpga_model[i].pn) 190 break; 191 192 if (i == ARRAY_SIZE(socfpga_fpga_model)) { 193 printf("FPGA: Unknown Altera chip, ID 0x%08x\n", id); 194 return -EINVAL; 195 } 196 197 if (print_id) 198 printf("FPGA: Altera %s, version 0x%01x\n", 199 socfpga_fpga_model[i].name, version); 200 return i; 201 } 202 203 /* 204 * Print CPU information 205 */ 206 #if defined(CONFIG_DISPLAY_CPUINFO) 207 int print_cpuinfo(void) 208 { 209 const u32 bsel = readl(&sysmgr_regs->bootinfo) & 0x7; 210 puts("CPU: Altera SoCFPGA Platform\n"); 211 socfpga_fpga_id(1); 212 printf("BOOT: %s\n", bsel_str[bsel].name); 213 return 0; 214 } 215 #endif 216 217 #ifdef CONFIG_ARCH_MISC_INIT 218 int arch_misc_init(void) 219 { 220 const u32 bsel = readl(&sysmgr_regs->bootinfo) & 0x7; 221 const int fpga_id = socfpga_fpga_id(0); 222 setenv("bootmode", bsel_str[bsel].mode); 223 if (fpga_id >= 0) 224 setenv("fpgatype", socfpga_fpga_model[fpga_id].var); 225 return 0; 226 } 227 #endif 228 229 #if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && \ 230 defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE) 231 int overwrite_console(void) 232 { 233 return 0; 234 } 235 #endif 236 237 #ifdef CONFIG_FPGA 238 /* 239 * FPGA programming support for SoC FPGA Cyclone V 240 */ 241 static Altera_desc altera_fpga[] = { 242 { 243 /* Family */ 244 Altera_SoCFPGA, 245 /* Interface type */ 246 fast_passive_parallel, 247 /* No limitation as additional data will be ignored */ 248 -1, 249 /* No device function table */ 250 NULL, 251 /* Base interface address specified in driver */ 252 NULL, 253 /* No cookie implementation */ 254 0 255 }, 256 }; 257 258 /* add device descriptor to FPGA device table */ 259 static void socfpga_fpga_add(void) 260 { 261 int i; 262 fpga_init(); 263 for (i = 0; i < ARRAY_SIZE(altera_fpga); i++) 264 fpga_add(fpga_altera, &altera_fpga[i]); 265 } 266 #else 267 static inline void socfpga_fpga_add(void) {} 268 #endif 269 270 int arch_cpu_init(void) 271 { 272 #ifdef CONFIG_HW_WATCHDOG 273 /* 274 * In case the watchdog is enabled, make sure to (re-)configure it 275 * so that the defined timeout is valid. Otherwise the SPL (Perloader) 276 * timeout value is still active which might too short for Linux 277 * booting. 278 */ 279 hw_watchdog_init(); 280 #else 281 /* 282 * If the HW watchdog is NOT enabled, make sure it is not running, 283 * for example because it was enabled in the preloader. This might 284 * trigger a watchdog-triggered reboot of Linux kernel later. 285 * Toggle watchdog reset, so watchdog in not running state. 286 */ 287 socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1); 288 socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0); 289 #endif 290 291 return 0; 292 } 293 294 /* 295 * Convert all NIC-301 AMBA slaves from secure to non-secure 296 */ 297 static void socfpga_nic301_slave_ns(void) 298 { 299 writel(0x1, &nic301_regs->lwhps2fpgaregs); 300 writel(0x1, &nic301_regs->hps2fpgaregs); 301 writel(0x1, &nic301_regs->acp); 302 writel(0x1, &nic301_regs->rom); 303 writel(0x1, &nic301_regs->ocram); 304 writel(0x1, &nic301_regs->sdrdata); 305 } 306 307 static uint32_t iswgrp_handoff[8]; 308 309 int arch_early_init_r(void) 310 { 311 int i; 312 313 /* 314 * Write magic value into magic register to unlock support for 315 * issuing warm reset. The ancient kernel code expects this 316 * value to be written into the register by the bootloader, so 317 * to support that old code, we write it here instead of in the 318 * reset_cpu() function just before reseting the CPU. 319 */ 320 writel(0xae9efebc, &sysmgr_regs->romcodegrp_warmramgrp_enable); 321 322 for (i = 0; i < 8; i++) /* Cache initial SW setting regs */ 323 iswgrp_handoff[i] = readl(&sysmgr_regs->iswgrp_handoff[i]); 324 325 socfpga_bridges_reset(1); 326 socfpga_nic301_slave_ns(); 327 328 /* 329 * Private components security: 330 * U-Boot : configure private timer, global timer and cpu component 331 * access as non secure for kernel stage (as required by Linux) 332 */ 333 setbits_le32(&scu_regs->sacr, 0xfff); 334 335 /* Configure the L2 controller to make SDRAM start at 0 */ 336 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET 337 writel(0x2, &nic301_regs->remap); 338 #else 339 writel(0x1, &nic301_regs->remap); /* remap.mpuzero */ 340 writel(0x1, &pl310->pl310_addr_filter_start); 341 #endif 342 343 /* Add device descriptor to FPGA device table */ 344 socfpga_fpga_add(); 345 346 #ifdef CONFIG_DESIGNWARE_SPI 347 /* Get Designware SPI controller out of reset */ 348 socfpga_per_reset(SOCFPGA_RESET(SPIM0), 0); 349 socfpga_per_reset(SOCFPGA_RESET(SPIM1), 0); 350 #endif 351 352 return 0; 353 } 354 355 static void socfpga_sdram_apply_static_cfg(void) 356 { 357 const uint32_t staticcfg = SOCFPGA_SDR_ADDRESS + 0x505c; 358 const uint32_t applymask = 0x8; 359 uint32_t val = readl(staticcfg) | applymask; 360 361 /* 362 * SDRAM staticcfg register specific: 363 * When applying the register setting, the CPU must not access 364 * SDRAM. Luckily for us, we can abuse i-cache here to help us 365 * circumvent the SDRAM access issue. The idea is to make sure 366 * that the code is in one full i-cache line by branching past 367 * it and back. Once it is in the i-cache, we execute the core 368 * of the code and apply the register settings. 369 * 370 * The code below uses 7 instructions, while the Cortex-A9 has 371 * 32-byte cachelines, thus the limit is 8 instructions total. 372 */ 373 asm volatile( 374 ".align 5 \n" 375 " b 2f \n" 376 "1: str %0, [%1] \n" 377 " dsb \n" 378 " isb \n" 379 " b 3f \n" 380 "2: b 1b \n" 381 "3: nop \n" 382 : : "r"(val), "r"(staticcfg) : "memory", "cc"); 383 } 384 385 int do_bridge(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 386 { 387 if (argc != 2) 388 return CMD_RET_USAGE; 389 390 argv++; 391 392 switch (*argv[0]) { 393 case 'e': /* Enable */ 394 writel(iswgrp_handoff[2], &sysmgr_regs->fpgaintfgrp_module); 395 socfpga_sdram_apply_static_cfg(); 396 writel(iswgrp_handoff[3], SOCFPGA_SDR_ADDRESS + 0x5080); 397 writel(iswgrp_handoff[0], &reset_manager_base->brg_mod_reset); 398 writel(iswgrp_handoff[1], &nic301_regs->remap); 399 break; 400 case 'd': /* Disable */ 401 writel(0, &sysmgr_regs->fpgaintfgrp_module); 402 writel(0, SOCFPGA_SDR_ADDRESS + 0x5080); 403 socfpga_sdram_apply_static_cfg(); 404 writel(0, &reset_manager_base->brg_mod_reset); 405 writel(1, &nic301_regs->remap); 406 break; 407 default: 408 return CMD_RET_USAGE; 409 } 410 411 return 0; 412 } 413 414 U_BOOT_CMD( 415 bridge, 2, 1, do_bridge, 416 "SoCFPGA HPS FPGA bridge control", 417 "enable - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n" 418 "bridge disable - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n" 419 "" 420 ); 421